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src/northbridge: Remove unnecessary whitespace before "\n" and "\t" 

Change-Id: I6a533667c7c8ff5ec6ab9d4e1cfc51e993a90084
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16280
Tested-by: build bot (Jenkins)
Reviewed-by: Omar Pakker
This commit is contained in:
Elyes HAOUAS 2016-08-21 12:01:04 +02:00 committed by Martin Roth
parent ccf78f083c
commit 38424987c6
7 changed files with 15 additions and 15 deletions
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2
src/northbridge/amd/agesa/eventlog.c
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@ -555,7 +555,7 @@ static void agesa_critical(EVENT_PARAMS *event)
break; break;
case HT_EVENT_COH_PROCESSOR_TYPE_MIX: case HT_EVENT_COH_PROCESSOR_TYPE_MIX:
printk(BIOS_DEBUG, "Socket %x Link %x TotalSockets %x, HT_EVENT_COH_PROCESSOR_TYPE_MIX \n", printk(BIOS_DEBUG, "Socket %x Link %x TotalSockets %x, HT_EVENT_COH_PROCESSOR_TYPE_MIX\n",
(unsigned int)event->DataParam1, (unsigned int)event->DataParam1,
(unsigned int)event->DataParam2, (unsigned int)event->DataParam2,
(unsigned int)event->DataParam3); (unsigned int)event->DataParam3);

2
src/northbridge/amd/amdk8/exit_from_self.c
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@ -116,7 +116,7 @@ void exit_from_self(int controllers, const struct mem_controller *ctrl,
"orb %1, %%al\n\t" "orb %1, %%al\n\t"
"not %1\n\t" "not %1\n\t"
".align 64\n\t" ".align 64\n\t"
"outl %%eax, (%%dx) \n\t" "outl %%eax, (%%dx)\n\t"
"andb %1, %%al\n\t" "andb %1, %%al\n\t"
"outl %%eax, (%%dx)\n\t" "outl %%eax, (%%dx)\n\t"
"popl %0\n\t"::"a"(pcidev), "popl %0\n\t"::"a"(pcidev),

6
src/northbridge/amd/amdmct/mct/mct_d.c
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@ -644,7 +644,7 @@ static void HTMemMapInit_D(struct MCTStatStruc *pMCTstat,
devx = pDCTstat->dev_map; devx = pDCTstat->dev_map;
if (pDCTstat->NodePresent) { if (pDCTstat->NodePresent) {
printk(BIOS_DEBUG, " Copy dram map from Node 0 to Node %02x \n", Node); printk(BIOS_DEBUG, " Copy dram map from Node 0 to Node %02x\n", Node);
reg = 0x40; /*Dram Base 0*/ reg = 0x40; /*Dram Base 0*/
do { do {
val = Get_NB32(dev, reg); val = Get_NB32(dev, reg);
@ -892,7 +892,7 @@ static void StartupDCT_D(struct MCTStatStruc *pMCTstat,
byte = mctGet_NVbits(NV_DQSTrainCTL); byte = mctGet_NVbits(NV_DQSTrainCTL);
if (byte == 1) { if (byte == 1) {
/* Enable DQSRcvEn training mode */ /* Enable DQSRcvEn training mode */
print_t("\t\t\tStartupDCT_D: DqsRcvEnTrain set \n"); print_t("\t\t\tStartupDCT_D: DqsRcvEnTrain set\n");
reg = 0x78 + reg_off; reg = 0x78 + reg_off;
val = Get_NB32(dev, reg); val = Get_NB32(dev, reg);
/* Setting this bit forces a 1T window with hard left /* Setting this bit forces a 1T window with hard left
@ -903,7 +903,7 @@ static void StartupDCT_D(struct MCTStatStruc *pMCTstat,
Set_NB32(dev, reg, val); Set_NB32(dev, reg, val);
} }
mctHookBeforeDramInit(); /* generalized Hook */ mctHookBeforeDramInit(); /* generalized Hook */
print_t("\t\t\tStartupDCT_D: DramInit \n"); print_t("\t\t\tStartupDCT_D: DramInit\n");
mct_DramInit(pMCTstat, pDCTstat, dct); mct_DramInit(pMCTstat, pDCTstat, dct);
AfterDramInit_D(pDCTstat, dct); AfterDramInit_D(pDCTstat, dct);
mctHookAfterDramInit(); /* generalized Hook*/ mctHookAfterDramInit(); /* generalized Hook*/

2
src/northbridge/amd/amdmct/mct/mctdqs_d.c
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@ -511,7 +511,7 @@ static void TrainDQSPos_D(struct MCTStatStruc *pMCTstat,
} }
MutualCSPassW[DQSDelay] &= tmp; MutualCSPassW[DQSDelay] &= tmp;
print_debug_dqs("\t\t\t\t\tTrainDQSPos: 146 \tMutualCSPassW ", MutualCSPassW[DQSDelay], 5); print_debug_dqs("\t\t\t\t\tTrainDQSPos: 146\tMutualCSPassW ", MutualCSPassW[DQSDelay], 5);
SetTargetWTIO_D(TestAddr); SetTargetWTIO_D(TestAddr);
FlushDQSTestPattern_D(pDCTstat, TestAddr << 8); FlushDQSTestPattern_D(pDCTstat, TestAddr << 8);

4
src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
View File

@ -3973,7 +3973,7 @@ static void HTMemMapInit_D(struct MCTStatStruc *pMCTstat,
val |= Node; val |= Node;
Set_NB32(dev, 0x44 + (Node << 3), val); /* set DstNode */ Set_NB32(dev, 0x44 + (Node << 3), val); /* set DstNode */
printk(BIOS_DEBUG, " Node: %02x base: %02x limit: %02x \n", Node, base, limit); printk(BIOS_DEBUG, " Node: %02x base: %02x limit: %02x\n", Node, base, limit);
limit = pDCTstat->DCTSysLimit; limit = pDCTstat->DCTSysLimit;
if (limit) { if (limit) {
NextBase = (limit & 0xFFFF0000) + 0x10000; NextBase = (limit & 0xFFFF0000) + 0x10000;
@ -3987,7 +3987,7 @@ static void HTMemMapInit_D(struct MCTStatStruc *pMCTstat,
devx = pDCTstat->dev_map; devx = pDCTstat->dev_map;
if (pDCTstat->NodePresent) { if (pDCTstat->NodePresent) {
printk(BIOS_DEBUG, " Copy dram map from Node 0 to Node %02x \n", Node); printk(BIOS_DEBUG, " Copy dram map from Node 0 to Node %02x\n", Node);
reg = 0x40; /*Dram Base 0*/ reg = 0x40; /*Dram Base 0*/
do { do {
val = Get_NB32(dev, reg); val = Get_NB32(dev, reg);

10
src/northbridge/intel/i945/raminit.c
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@ -1235,7 +1235,7 @@ static void sdram_program_dll_timings(struct sys_info *sysinfo)
u32 chan0dll = 0, chan1dll = 0; u32 chan0dll = 0, chan1dll = 0;
int i; int i;
printk(BIOS_DEBUG, "Programming DLL Timings... \n"); printk(BIOS_DEBUG, "Programming DLL Timings...\n");
MCHBAR16(DQSMT) &= ~( (3 << 12) | (1 << 10) | ( 0xf << 0) ); MCHBAR16(DQSMT) &= ~( (3 << 12) | (1 << 10) | ( 0xf << 0) );
MCHBAR16(DQSMT) |= (1 << 13) | (0xc << 0); MCHBAR16(DQSMT) |= (1 << 13) | (0xc << 0);
@ -1287,7 +1287,7 @@ static void sdram_initialize_system_memory_io(struct sys_info *sysinfo)
u8 reg8; u8 reg8;
u32 reg32; u32 reg32;
printk(BIOS_DEBUG, "Initializing System Memory IO... \n"); printk(BIOS_DEBUG, "Initializing System Memory IO...\n");
/* Enable Data Half Clock Pushout */ /* Enable Data Half Clock Pushout */
reg8 = MCHBAR8(C0HCTC); reg8 = MCHBAR8(C0HCTC);
reg8 &= ~0x1f; reg8 &= ~0x1f;
@ -1329,7 +1329,7 @@ static void sdram_enable_system_memory_io(struct sys_info *sysinfo)
{ {
u32 reg32; u32 reg32;
printk(BIOS_DEBUG, "Enabling System Memory IO... \n"); printk(BIOS_DEBUG, "Enabling System Memory IO...\n");
reg32 = MCHBAR32(RCVENMT); reg32 = MCHBAR32(RCVENMT);
reg32 &= ~(0x3f << 6); reg32 &= ~(0x3f << 6);
@ -1561,7 +1561,7 @@ static int sdram_set_row_attributes(struct sys_info *sysinfo)
int i, value; int i, value;
u16 dra0=0, dra1=0, dra = 0; u16 dra0=0, dra1=0, dra = 0;
printk(BIOS_DEBUG, "Setting row attributes... \n"); printk(BIOS_DEBUG, "Setting row attributes...\n");
for(i=0; i < 2 * DIMM_SOCKETS; i++) { for(i=0; i < 2 * DIMM_SOCKETS; i++) {
u16 device; u16 device;
u8 columnsrows; u8 columnsrows;
@ -2763,7 +2763,7 @@ static void sdram_on_die_termination(struct sys_info *sysinfo)
if ( !(sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED && if ( !(sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED &&
sysinfo->dimm[1] != SYSINFO_DIMM_NOT_POPULATED) ) { sysinfo->dimm[1] != SYSINFO_DIMM_NOT_POPULATED) ) {
printk(BIOS_DEBUG, "one dimm per channel config.. \n"); printk(BIOS_DEBUG, "one dimm per channel config..\n");
reg32 = MCHBAR32(C0ODT); reg32 = MCHBAR32(C0ODT);
reg32 &= ~(7 << 28); reg32 &= ~(7 << 28);

4
src/northbridge/via/vx900/northbridge.c
View File

@ -82,8 +82,8 @@ static void killme_debug_4g_remap_reg(u32 reg32)
u64 remapend = (reg32 >> 14) & 0x3ff; u64 remapend = (reg32 >> 14) & 0x3ff;
remapstart <<= 26; remapstart <<= 26;
remapend <<= 26; remapend <<= 26;
printk(BIOS_DEBUG, "Remapstart %lld(MB) \n", remapstart >> 20); printk(BIOS_DEBUG, "Remapstart %lld(MB)\n", remapstart >> 20);
printk(BIOS_DEBUG, "Remapend %lld(MB) \n", remapend >> 20); printk(BIOS_DEBUG, "Remapend %lld(MB)\n", remapend >> 20);
} }
/** /**