soc/intel/xeon_sp/skx: Let iasl automatically resolve _PRT package size
BUILD_TIMELESS=1 with ocp/tiogapass results in identical binaries. Change-Id: Iff97f3cc0ce800036be32b2758c60e4b7ac39fe9 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41529 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This commit is contained in:
Arthur Heymans
Patrick Georgi
parent
ad2eb28c10
commit
3855a9806e
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@ -7,225 +7,225 @@
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*/
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#define GEN_PCIE_LEGACY_IRQ() \
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Package (0x04) { 0x0000FFFF, 0x00, LNKA, 0x00 }, \
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Package (0x04) { 0x0001FFFF, 0x00, LNKA, 0x00 }, \
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Package (0x04) { 0x0002FFFF, 0x00, LNKA, 0x00 }, \
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Package (0x04) { 0x0003FFFF, 0x00, LNKA, 0x00 }
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Package () { 0x0000FFFF, 0x00, LNKA, 0x00 }, \
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Package () { 0x0001FFFF, 0x00, LNKA, 0x00 }, \
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Package () { 0x0002FFFF, 0x00, LNKA, 0x00 }, \
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Package () { 0x0003FFFF, 0x00, LNKA, 0x00 }
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#define GEN_UNCORE_LEGACY_IRQ(dev) \
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Package (0x04) { ##dev, 0x00, LNKA, 0x00 }, \
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Package (0x04) { ##dev, 0x01, LNKB, 0x00 }, \
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Package (0x04) { ##dev, 0x02, LNKC, 0x00 }, \
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Package (0x04) { ##dev, 0x03, LNKD, 0x00 }
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Package () { ##dev, 0x00, LNKA, 0x00 }, \
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Package () { ##dev, 0x01, LNKB, 0x00 }, \
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Package () { ##dev, 0x02, LNKC, 0x00 }, \
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Package () { ##dev, 0x03, LNKD, 0x00 }
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#define GEN_PCIE_IOAPIC_IRQ(irq) \
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Package (0x04) { 0x0000FFFF, 0x00, 0x00, ##irq }, \
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Package (0x04) { 0x0001FFFF, 0x00, 0x00, ##irq }, \
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Package (0x04) { 0x0002FFFF, 0x00, 0x00, ##irq }, \
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Package (0x04) { 0x0003FFFF, 0x00, 0x00, ##irq }
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Package () { 0x0000FFFF, 0x00, 0x00, ##irq }, \
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Package () { 0x0001FFFF, 0x00, 0x00, ##irq }, \
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Package () { 0x0002FFFF, 0x00, 0x00, ##irq }, \
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Package () { 0x0003FFFF, 0x00, 0x00, ##irq }
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#define GEN_UNCORE_IOAPIC_IRQ(dev,irq1,irq2,irq3,irq4) \
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Package (0x04) { ##dev, 0x00, 0x00, ##irq1 }, \
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Package (0x04) { ##dev, 0x01, 0x00, ##irq2 }, \
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Package (0x04) { ##dev, 0x02, 0x00, ##irq3 }, \
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Package (0x04) { ##dev, 0x03, 0x00, ##irq4 }
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Package () { ##dev, 0x00, 0x00, ##irq1 }, \
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Package () { ##dev, 0x01, 0x00, ##irq2 }, \
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Package () { ##dev, 0x02, 0x00, ##irq3 }, \
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Package () { ##dev, 0x03, 0x00, ##irq4 }
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// Socket 0, IIOStack 0 device legacy interrupt routing
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Name (PR00, Package (0x28)
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{
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// [DMI0]: Legacy PCI Express Port 0
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Package (0x04) { 0x0000FFFF, 0x00, LNKA, 0x00 },
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Package () { 0x0000FFFF, 0x00, LNKA, 0x00 },
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// [CB0A]: CBDMA
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// [CB0E]: CBDMA
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Package (0x04) { 0x0004FFFF, 0x00, LNKA, 0x00 },
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Package () { 0x0004FFFF, 0x00, LNKA, 0x00 },
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// [CB0B]: CBDMA
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// [CB0F]: CBDMA
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Package (0x04) { 0x0004FFFF, 0x01, LNKB, 0x00 },
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Package () { 0x0004FFFF, 0x01, LNKB, 0x00 },
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// [CB0C]: CBDMA
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// [CB0G]: CBDMA
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Package (0x04) { 0x0004FFFF, 0x02, LNKC, 0x00 },
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Package () { 0x0004FFFF, 0x02, LNKC, 0x00 },
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// [CB0D]: CBDMA
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// [CB0H]: CBDMA
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Package (0x04) { 0x0004FFFF, 0x03, LNKD, 0x00 },
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Package () { 0x0004FFFF, 0x03, LNKD, 0x00 },
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// Uncore 0 UBOX Device
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Package (0x04) { 0x0008FFFF, 0x00, LNKA, 0x00 },
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Package (0x04) { 0x0008FFFF, 0x01, LNKB, 0x00 },
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Package (0x04) { 0x0008FFFF, 0x02, LNKC, 0x00 },
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Package (0x04) { 0x0008FFFF, 0x03, LNKD, 0x00 },
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Package () { 0x0008FFFF, 0x00, LNKA, 0x00 },
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Package () { 0x0008FFFF, 0x01, LNKB, 0x00 },
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Package () { 0x0008FFFF, 0x02, LNKC, 0x00 },
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Package () { 0x0008FFFF, 0x03, LNKD, 0x00 },
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// [DISP]: Display Controller
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Package (0x04) { 0x000FFFFF, 0x00, LNKA, 0x00 },
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Package () { 0x000FFFFF, 0x00, LNKA, 0x00 },
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// [IHC1]: HECI #1
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// [IHC3]: HECI #3
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Package (0x04) { 0x0010FFFF, 0x00, LNKA, 0x00 },
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Package () { 0x0010FFFF, 0x00, LNKA, 0x00 },
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// [IHC2]: HECI #2
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Package (0x04) { 0x0010FFFF, 0x01, LNKB, 0x00 },
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Package () { 0x0010FFFF, 0x01, LNKB, 0x00 },
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// [IIDR]: IDE-Redirection (IDE-R)
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Package (0x04) { 0x0010FFFF, 0x02, LNKC, 0x00 },
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Package () { 0x0010FFFF, 0x02, LNKC, 0x00 },
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// [IMKT]: Keyboard and Text (KT) Redirection
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Package (0x04) { 0x0010FFFF, 0x03, LNKD, 0x00 },
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Package () { 0x0010FFFF, 0x03, LNKD, 0x00 },
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// [SAT2]: sSATA Host controller 2 on PCH
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Package (0x04) { 0x0011FFFF, 0x00, LNKA, 0x00 },
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Package () { 0x0011FFFF, 0x00, LNKA, 0x00 },
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// // [XHCI]: xHCI controller 1 on PCH
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Package (0x04) { 0x0014FFFF, 0x00, LNKA, 0x00 },
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Package () { 0x0014FFFF, 0x00, LNKA, 0x00 },
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// [OTG0]: USB Device Controller (OTG) on PCH
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Package (0x04) { 0x0014FFFF, 0x01, LNKB, 0x00 },
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Package () { 0x0014FFFF, 0x01, LNKB, 0x00 },
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// [TERM]: Thermal Subsystem on PCH
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Package (0x04) { 0x0014FFFF, 0x02, LNKC, 0x00 },
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Package () { 0x0014FFFF, 0x02, LNKC, 0x00 },
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// [CAMR]: Camera IO Host Controller on PCH
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Package (0x04) { 0x0014FFFF, 0x03, LNKD, 0x00 },
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Package () { 0x0014FFFF, 0x03, LNKD, 0x00 },
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// [HEC1]: HECI #1 on PCH
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// [HEC3]: HECI #3 on PCH
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Package (0x04) { 0x0016FFFF, 0x00, LNKA, 0x00 },
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Package () { 0x0016FFFF, 0x00, LNKA, 0x00 },
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// [HEC2]: HECI #2 on PCH
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Package (0x04) { 0x0016FFFF, 0x01, LNKB, 0x00 },
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Package () { 0x0016FFFF, 0x01, LNKB, 0x00 },
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// [IDER]: ME IDE redirect on PCH
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Package (0x04) { 0x0016FFFF, 0x02, LNKC, 0x00 },
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Package () { 0x0016FFFF, 0x02, LNKC, 0x00 },
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// [MEKT]: MEKT on PCH
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Package (0x04) { 0x0016FFFF, 0x03, LNKD, 0x00 },
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Package () { 0x0016FFFF, 0x03, LNKD, 0x00 },
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// [SAT1]: SATA controller 1 on PCH
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Package (0x04) { 0x0017FFFF, 0x00, LNKA, 0x00 },
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Package () { 0x0017FFFF, 0x00, LNKA, 0x00 },
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// [NAN1]: NAND Cycle Router on PCH
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Package (0x04) { 0x0018FFFF, 0x00, LNKA, 0x00 },
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Package () { 0x0018FFFF, 0x00, LNKA, 0x00 },
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// [RP17]: PCIE PCH Root Port #17
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Package (0x04) { 0x001BFFFF, 0x00, LNKA, 0x00 },
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Package () { 0x001BFFFF, 0x00, LNKA, 0x00 },
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// [RP18]: PCIE PCH Root Port #18
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Package (0x04) { 0x001BFFFF, 0x01, LNKB, 0x00 },
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Package () { 0x001BFFFF, 0x01, LNKB, 0x00 },
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// [RP19]: PCIE PCH Root Port #19
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Package (0x04) { 0x001BFFFF, 0x02, LNKC, 0x00 },
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Package () { 0x001BFFFF, 0x02, LNKC, 0x00 },
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// [RP20]: PCIE PCH Root Port #20
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Package (0x04) { 0x001BFFFF, 0x03, LNKD, 0x00 },
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Package () { 0x001BFFFF, 0x03, LNKD, 0x00 },
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// [RP01]: PCIE PCH Root Port #1
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// [RP05]: PCIE PCH Root Port #5
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Package (0x04) { 0x001CFFFF, 0x00, LNKA, 0x00 },
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Package () { 0x001CFFFF, 0x00, LNKA, 0x00 },
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// [RP02]: PCIE PCH Root Port #2
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// [RP06]: PCIE PCH Root Port #6
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Package (0x04) { 0x001CFFFF, 0x01, LNKB, 0x00 },
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Package () { 0x001CFFFF, 0x01, LNKB, 0x00 },
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// [RP03]: PCIE PCH Root Port #3
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// [RP07]: PCIE PCH Root Port #7
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Package (0x04) { 0x001CFFFF, 0x02, LNKC, 0x00 },
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Package () { 0x001CFFFF, 0x02, LNKC, 0x00 },
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// [RP04]: PCIE PCH Root Port #4
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// [RP08]: PCIE PCH Root Port #8
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Package (0x04) { 0x001CFFFF, 0x03, LNKD, 0x00 },
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Package () { 0x001CFFFF, 0x03, LNKD, 0x00 },
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// [RP09]: PCIE PCH Root Port #9
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// [RP13]: PCIE PCH Root Port #13
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Package (0x04) { 0x001DFFFF, 0x00, LNKA, 0x00 },
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Package () { 0x001DFFFF, 0x00, LNKA, 0x00 },
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// [RP10]: PCIE PCH Root Port #10
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// [RP14]: PCIE PCH Root Port #14
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Package (0x04) { 0x001DFFFF, 0x01, LNKB, 0x00 },
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Package () { 0x001DFFFF, 0x01, LNKB, 0x00 },
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// [RP11]: PCIE PCH Root Port #11
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// [RP15]: PCIE PCH Root Port #15
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Package (0x04) { 0x001DFFFF, 0x02, LNKC, 0x00 },
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Package () { 0x001DFFFF, 0x02, LNKC, 0x00 },
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// [RP12]: PCIE PCH Root Port #12
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// [RP16]: PCIE PCH Root Port #16
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Package (0x04) { 0x001DFFFF, 0x03, LNKD, 0x00 },
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Package () { 0x001DFFFF, 0x03, LNKD, 0x00 },
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// [UAR0]: UART #0 on PCH
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Package (0x04) { 0x001EFFFF, 0x02, LNKC, 0x00 },
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Package () { 0x001EFFFF, 0x02, LNKC, 0x00 },
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// [UAR1]: UART #1 on PCH
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Package (0x04) { 0x001EFFFF, 0x03, LNKD, 0x00 },
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Package () { 0x001EFFFF, 0x03, LNKD, 0x00 },
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// [CAVS]: HD Audio Subsystem Controller on PCH
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// [SMBS]: SMBus controller on PCH
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// [GBE1]: GbE Controller on PCH
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// [NTPK]: Northpeak Controller on PCH
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Package (0x04) { 0x001FFFFF, 0x00, LNKA, 0x00 },
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Package () { 0x001FFFFF, 0x00, LNKA, 0x00 },
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})
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// Socket 0, IIOStack 0 device IOAPIC interrupt routing
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Name (AR00, Package (0x28)
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{
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// [DMI0]: Legacy PCI Express Port 0
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Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x1F },
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Package () { 0x0000FFFF, 0x00, 0x00, 0x1F },
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// [CB0A]: CB3DMA
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// [CB0E]: CB3DMA
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Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x1A },
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Package () { 0x0004FFFF, 0x00, 0x00, 0x1A },
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// [CB0B]: CB3DMA
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// [CB0F]: CB3DMA
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Package (0x04) { 0x0004FFFF, 0x01, 0x00, 0x1B },
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Package () { 0x0004FFFF, 0x01, 0x00, 0x1B },
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// [CB0C]: CB3DMA
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// [CB0G]: CB3DMA
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Package (0x04) { 0x0004FFFF, 0x02, 0x00, 0x1A },
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Package () { 0x0004FFFF, 0x02, 0x00, 0x1A },
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// [CB0D]: CB3DMA
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// [CB0H]: CB3DMA
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Package (0x04) { 0x0004FFFF, 0x03, 0x00, 0x1B },
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Package () { 0x0004FFFF, 0x03, 0x00, 0x1B },
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// [UBX0]: Uncore 0 UBOX Device
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Package (0x04) { 0x0008FFFF, 0x00, 0x00, 0x18 },
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Package (0x04) { 0x0008FFFF, 0x01, 0x00, 0x1C },
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Package (0x04) { 0x0008FFFF, 0x02, 0x00, 0x1D },
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Package (0x04) { 0x0008FFFF, 0x03, 0x00, 0x1E },
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Package () { 0x0008FFFF, 0x00, 0x00, 0x18 },
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Package () { 0x0008FFFF, 0x01, 0x00, 0x1C },
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Package () { 0x0008FFFF, 0x02, 0x00, 0x1D },
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Package () { 0x0008FFFF, 0x03, 0x00, 0x1E },
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// [DISP]: Display Controller
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Package (0x04) { 0x000FFFFF, 0x00, 0x00, 0x10 },
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Package () { 0x000FFFFF, 0x00, 0x00, 0x10 },
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// [IHC1]: HECI #1
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// [IHC3]: HECI #3
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Package (0x04) { 0x0010FFFF, 0x00, 0x00, 0x10 },
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Package () { 0x0010FFFF, 0x00, 0x00, 0x10 },
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// [IHC2]: HECI #2
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Package (0x04) { 0x0010FFFF, 0x01, 0x00, 0x11 },
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Package () { 0x0010FFFF, 0x01, 0x00, 0x11 },
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// [IIDR]: IDE-Redirection (IDE-R)
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Package (0x04) { 0x0010FFFF, 0x02, 0x00, 0x12 },
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Package () { 0x0010FFFF, 0x02, 0x00, 0x12 },
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// [IMKT]: Keyboard and Text (KT) Redirection
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Package (0x04) { 0x0010FFFF, 0x03, 0x00, 0x13 },
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Package () { 0x0010FFFF, 0x03, 0x00, 0x13 },
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// [SAT2]: sSATA Host controller 2 on PCH
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Package (0x04) { 0x0011FFFF, 0x00, 0x00, 0x10 },
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Package () { 0x0011FFFF, 0x00, 0x00, 0x10 },
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// [XHCI]: xHCI controller 1 on PCH
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Package (0x04) { 0x0014FFFF, 0x00, 0x00, 0x10 },
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Package () { 0x0014FFFF, 0x00, 0x00, 0x10 },
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// [OTG0]: USB Device Controller (OTG) on PCH
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Package (0x04) { 0x0014FFFF, 0x01, 0x00, 0x11 },
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Package () { 0x0014FFFF, 0x01, 0x00, 0x11 },
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// [TERM]: Thermal Subsystem on PCH
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Package (0x04) { 0x0014FFFF, 0x02, 0x00, 0x12 },
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Package () { 0x0014FFFF, 0x02, 0x00, 0x12 },
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// [CAMR]: Camera IO Host Controller on PCH
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Package (0x04) { 0x0014FFFF, 0x03, 0x00, 0x13 },
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Package () { 0x0014FFFF, 0x03, 0x00, 0x13 },
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// [HEC1]: HECI #1 on PCH
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// [HEC3]: HECI #3 on PCH
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Package (0x04) { 0x0016FFFF, 0x00, 0x00, 0x10 },
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Package () { 0x0016FFFF, 0x00, 0x00, 0x10 },
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// [HEC2]: HECI #2 on PCH
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Package (0x04) { 0x0016FFFF, 0x01, 0x00, 0x11 },
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Package () { 0x0016FFFF, 0x01, 0x00, 0x11 },
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// [IDER]: ME IDE redirect on PCH
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Package (0x04) { 0x0016FFFF, 0x02, 0x00, 0x12 },
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Package () { 0x0016FFFF, 0x02, 0x00, 0x12 },
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// [MEKT]: MEKT on PCH
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Package (0x04) { 0x0016FFFF, 0x03, 0x00, 0x13 },
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Package () { 0x0016FFFF, 0x03, 0x00, 0x13 },
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// [SAT1]: SATA controller 1 on PCH
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Package (0x04) { 0x0017FFFF, 0x00, 0x00, 0x10 },
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Package () { 0x0017FFFF, 0x00, 0x00, 0x10 },
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// [NAN1]: NAND Cycle Router on PCH
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Package (0x04) { 0x0018FFFF, 0x00, 0x00, 0x10 },
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Package () { 0x0018FFFF, 0x00, 0x00, 0x10 },
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// [RP17]: PCIE PCH Root Port #17
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Package (0x04) { 0x001BFFFF, 0x00, 0x00, 0x10 },
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Package () { 0x001BFFFF, 0x00, 0x00, 0x10 },
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// [RP18]: PCIE PCH Root Port #18
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Package (0x04) { 0x001BFFFF, 0x01, 0x00, 0x11 },
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Package () { 0x001BFFFF, 0x01, 0x00, 0x11 },
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// [RP19]: PCIE PCH Root Port #19
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Package (0x04) { 0x001BFFFF, 0x02, 0x00, 0x12 },
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Package () { 0x001BFFFF, 0x02, 0x00, 0x12 },
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// [RP20]: PCIE PCH Root Port #20
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Package (0x04) { 0x001BFFFF, 0x03, 0x00, 0x13 },
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Package () { 0x001BFFFF, 0x03, 0x00, 0x13 },
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// [RP01]: PCIE PCH Root Port #1
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// [RP05]: PCIE PCH Root Port #5
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Package (0x04) { 0x001CFFFF, 0x00, 0x00, 0x10 },
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Package () { 0x001CFFFF, 0x00, 0x00, 0x10 },
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// [RP02]: PCIE PCH Root Port #2
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// [RP06]: PCIE PCH Root Port #6
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Package (0x04) { 0x001CFFFF, 0x01, 0x00, 0x11 },
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Package () { 0x001CFFFF, 0x01, 0x00, 0x11 },
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// [RP03]: PCIE PCH Root Port #3
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// [RP07]: PCIE PCH Root Port #7
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Package (0x04) { 0x001CFFFF, 0x02, 0x00, 0x12 },
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Package () { 0x001CFFFF, 0x02, 0x00, 0x12 },
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// [RP04]: PCIE PCH Root Port #4
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// [RP08]: PCIE PCH Root Port #8
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Package (0x04) { 0x001CFFFF, 0x03, 0x00, 0x13 },
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Package () { 0x001CFFFF, 0x03, 0x00, 0x13 },
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// [RP09]: PCIE PCH Root Port #9
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// [RP13]: PCIE PCH Root Port #13
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Package (0x04) { 0x001DFFFF, 0x00, 0x00, 0x10 },
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Package () { 0x001DFFFF, 0x00, 0x00, 0x10 },
|
||||
// [RP10]: PCIE PCH Root Port #10
|
||||
// [RP14]: PCIE PCH Root Port #14
|
||||
Package (0x04) { 0x001DFFFF, 0x01, 0x00, 0x11 },
|
||||
Package () { 0x001DFFFF, 0x01, 0x00, 0x11 },
|
||||
// [RP11]: PCIE PCH Root Port #11
|
||||
// [RP15]: PCIE PCH Root Port #15
|
||||
Package (0x04) { 0x001DFFFF, 0x02, 0x00, 0x12 },
|
||||
Package () { 0x001DFFFF, 0x02, 0x00, 0x12 },
|
||||
// [RP12]: PCIE PCH Root Port #12
|
||||
// [RP16]: PCIE PCH Root Port #16
|
||||
Package (0x04) { 0x001DFFFF, 0x03, 0x00, 0x13 },
|
||||
Package () { 0x001DFFFF, 0x03, 0x00, 0x13 },
|
||||
// [UAR0]: UART #0 on PCH
|
||||
Package (0x04) { 0x001EFFFF, 0x02, 0x00, 0x16 },
|
||||
Package () { 0x001EFFFF, 0x02, 0x00, 0x16 },
|
||||
// [UAR1]: UART #1 on PCH
|
||||
Package (0x04) { 0x001EFFFF, 0x03, 0x00, 0x17 },
|
||||
Package () { 0x001EFFFF, 0x03, 0x00, 0x17 },
|
||||
// [CAVS]: HD Audio Subsystem Controller on PCH
|
||||
// [SMBS]: SMBus controller on PCH
|
||||
// [GBE1]: GbE Controller on PCH
|
||||
// [NTPK]: Northpeak Controller on PCH
|
||||
Package (0x04) { 0x001FFFFF, 0x00, 0x00, 0x10 },
|
||||
Package () { 0x001FFFFF, 0x00, 0x00, 0x10 },
|
||||
})
|
||||
|
||||
// Socket 0, IIOStack 1 device legacy interrupt routing
|
||||
|
|
@ -406,7 +406,7 @@ Name (AR28, Package (0x20)
|
|||
Name (PR40, Package (0x09)
|
||||
{
|
||||
// DMI
|
||||
Package (0x04) { 0x0000FFFF, 0x00, LNKA, 0x00 },
|
||||
Package () { 0x0000FFFF, 0x00, LNKA, 0x00 },
|
||||
|
||||
// CBDMA
|
||||
GEN_UNCORE_LEGACY_IRQ(0x0004FFFF),
|
||||
|
|
@ -419,7 +419,7 @@ Name (PR40, Package (0x09)
|
|||
Name (AR40, Package (0x09)
|
||||
{
|
||||
// DMI
|
||||
Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x4F },
|
||||
Package () { 0x0000FFFF, 0x00, 0x00, 0x4F },
|
||||
|
||||
// CBDMA
|
||||
GEN_UNCORE_IOAPIC_IRQ(0x0004FFFF, 0x4A, 0x4B, 0x4A, 0x4B),
|
||||
|
|
|
|||
Loading…
Reference in New Issue