device/pnp: Add header files for PNP ops

Change-Id: Ifda495420cfb121ad32920bb9f1cbdeef41f6d3a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31698
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/arch/x86/include/arch/io.h

@@ -202,12 +202,10 @@ static __always_inline void write64(volatile void *addr,
 }
 #endif
 
-typedef u32 pnp_devfn_t;
+#include <device/pnp_type.h>
 
 #ifdef __SIMPLE_DEVICE__
 
-#define PNP_DEV(PORT, FUNC) (((PORT) << 8) | (FUNC))
-
 /* Generic functions for pnp devices */
 static __always_inline void pnp_write_config(
 	pnp_devfn_t dev, uint8_t reg, uint8_t value)

src/ec/google/wilco/bootblock.c

@@ -15,6 +15,7 @@
 
 #include <arch/io.h>
 #include <endian.h>
+#include <device/pnp_ops.h>
 #include <device/pnp_def.h>
 
 #include "bootblock.h"

src/ec/hp/kbc1126/early_init.c

@@ -14,6 +14,7 @@
  */
 
 #include <arch/io.h>
+#include <device/pnp_ops.h>
 #include <device/pnp.h>
 #include "ec.h"
 

src/include/device/pnp_ops.h

@@ -0,0 +1,21 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __DEVICE_PNP_OPS_H__
+#define __DEVICE_PNP_OPS_H__
+
+/* FIXME: We only want the PNP ops. */
+#include <arch/io.h>
+
+#endif

src/include/device/pnp_type.h

@@ -0,0 +1,23 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __DEVICE_PNP_TYPE_H__
+#define __DEVICE_PNP_TYPE_H__
+
+#include <stdint.h>
+
+typedef u32 pnp_devfn_t;
+
+#define PNP_DEV(PORT, FUNC) (((PORT) << 8) | (FUNC))
+
+#endif /* __DEVICE_PNP_TYPE_H__ */

src/mainboard/asrock/b75pro3-m/romstage.c

@@ -15,6 +15,7 @@
  */
 
 #include <device/pci_ops.h>
+#include <device/pnp_ops.h>
 #include <northbridge/intel/sandybridge/raminit_native.h>
 #include <superio/nuvoton/nct6776/nct6776.h>
 #include <superio/nuvoton/common/nuvoton.h>

src/mainboard/asrock/g41c-gs/romstage.c

@@ -15,7 +15,7 @@
  * GNU General Public License for more details.
  */
 
-#include <arch/io.h>
+#include <device/pnp_ops.h>
 #include <device/pci_ops.h>
 #include <console/console.h>
 #include <cpu/intel/romstage.h>

src/mainboard/asrock/h81m-hds/romstage.c

@@ -18,6 +18,7 @@
 #include <stdint.h>
 #include <cpu/intel/romstage.h>
 #include <cpu/intel/haswell/haswell.h>
+#include <device/pnp_ops.h>
 #include <northbridge/intel/haswell/haswell.h>
 #include <northbridge/intel/haswell/pei_data.h>
 #include <southbridge/intel/common/gpio.h>

src/mainboard/asus/am1i-a/romstage.c

@@ -16,6 +16,7 @@
  */
 
 #include <arch/io.h>
+#include <device/pnp_ops.h>
 #include <device/pci_ops.h>
 #include <commonlib/loglevel.h>
 #include <northbridge/amd/agesa/state_machine.h>

src/mainboard/asus/f2a85-m/romstage.c

@@ -15,6 +15,7 @@
  */
 
 #include <arch/io.h>
+#include <device/pnp_type.h>
 #include <device/pci_ops.h>
 
 #include <northbridge/amd/agesa/state_machine.h>

src/mainboard/asus/h61m-cs/romstage.c

@@ -17,6 +17,7 @@
 
 #include <northbridge/intel/sandybridge/sandybridge.h>
 #include <device/pci_ops.h>
+#include <device/pnp_ops.h>
 #include <northbridge/intel/sandybridge/raminit_native.h>
 #include <southbridge/intel/bd82x6x/pch.h>
 #include <superio/nuvoton/common/nuvoton.h>

src/mainboard/asus/kfsn4-dre/bootblock.c

@@ -16,6 +16,7 @@
  */
 
 #include <arch/io.h>
+#include <device/pnp_ops.h>
 #include <pc80/mc146818rtc.h>
 
 #include <superio/winbond/common/winbond.h>

src/mainboard/asus/kfsn4-dre/romstage.c

@@ -22,6 +22,7 @@
 #include <device/pci_def.h>
 #include <device/pci_ids.h>
 #include <arch/io.h>
+#include <device/pnp_ops.h>
 #include <device/pci_ops.h>
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>

src/mainboard/asus/maximus_iv_gene-z/romstage.c

@@ -14,7 +14,7 @@
  * GNU General Public License for more details.
  */
 
-#include <arch/io.h>
+#include <device/pnp_ops.h>
 #include <device/pci_ops.h>
 #include <device/dram/ddr3.h>
 #include <northbridge/intel/sandybridge/raminit_native.h>

src/mainboard/asus/p5gc-mx/romstage.c

@@ -20,6 +20,7 @@
 #include <stdint.h>
 #include <string.h>
 #include <arch/io.h>
+#include <device/pnp_ops.h>
 #include <device/pci_ops.h>
 #include <device/pci_def.h>
 #include <cpu/x86/lapic.h>

src/mainboard/asus/p5qpl-am/romstage.c

@@ -16,6 +16,7 @@
  */
 
 #include <arch/io.h>
+#include <device/pnp_ops.h>
 #include <device/pci_ops.h>
 #include <console/console.h>
 #include <cpu/intel/romstage.h>

src/mainboard/asus/p8h61-m_pro/romstage.c

@@ -14,6 +14,7 @@
  */
 
 #include <device/pci_ops.h>
+#include <device/pnp_ops.h>
 #include <northbridge/intel/sandybridge/raminit_native.h>
 #include <northbridge/intel/sandybridge/sandybridge.h>
 #include <southbridge/intel/bd82x6x/pch.h>

src/mainboard/biostar/am1ml/romstage.c

@@ -15,6 +15,7 @@
  */
 
 #include <arch/io.h>
+#include <device/pnp_ops.h>
 #include <device/pci_ops.h>
 #include <console/console.h>
 #include <commonlib/loglevel.h>

src/mainboard/getac/p470/romstage.c

@@ -17,6 +17,7 @@
 #include <stdint.h>
 #include <string.h>
 #include <arch/io.h>
+#include <device/pnp_ops.h>
 #include <device/pci_ops.h>
 #include <device/pci_def.h>
 #include <cpu/x86/lapic.h>

src/mainboard/hp/dl165_g6_fam10/bootblock.c

@@ -12,6 +12,7 @@
  */
 
 #include <arch/io.h>
+#include <device/pnp_ops.h>
 #include <device/pnp_def.h>
 
 #define SCH4307_CONFIG_PORT     0x162e

src/mainboard/ibase/mb899/romstage.c

@@ -18,6 +18,7 @@
 #include <stdint.h>
 #include <halt.h>
 #include <arch/io.h>
+#include <device/pnp_ops.h>
 #include <device/pci_ops.h>
 #include <console/console.h>
 #include <cpu/intel/romstage.h>

src/mainboard/intel/dg41wv/romstage.c

@@ -15,7 +15,7 @@
  * GNU General Public License for more details.
  */
 
-#include <arch/io.h>
+#include <device/pnp_ops.h>
 #include <device/pci_ops.h>
 #include <console/console.h>
 #include <cpu/intel/romstage.h>

src/mainboard/kontron/986lcd-m/romstage.c

@@ -24,6 +24,7 @@
 #include <cpu/x86/lapic.h>
 #include <device/pci_def.h>
 #include <device/pci_ops.h>
+#include <device/pnp_ops.h>
 #include <device/pnp_def.h>
 #include <pc80/mc146818rtc.h>
 #include <northbridge/intel/i945/i945.h>

src/mainboard/kontron/ktqm77/romstage.c

@@ -17,7 +17,7 @@
 #include <stdint.h>
 #include <string.h>
 #include <arch/acpi.h>
-#include <arch/io.h>
+#include <device/pnp_ops.h>
 #include <device/pci_ops.h>
 #include <cpu/x86/lapic.h>
 #include <cpu/x86/msr.h>

src/mainboard/lenovo/t400/dock.c

@@ -18,6 +18,7 @@
 #define __SIMPLE_DEVICE__
 #include <console/console.h>
 #include <arch/io.h>
+#include <device/pnp_ops.h>
 #include <device/device.h>
 #include <device/pci.h>
 #include <device/pnp.h>

src/mainboard/lenovo/t60/romstage.c

@@ -20,6 +20,7 @@
 #include <stdint.h>
 #include <string.h>
 #include <arch/io.h>
+#include <device/pnp_ops.h>
 #include <device/pci_ops.h>
 #include <device/pci_def.h>
 #include <device/pnp_def.h>

src/mainboard/lenovo/x60/romstage.c

@@ -20,6 +20,7 @@
 #include <stdint.h>
 #include <string.h>
 #include <arch/io.h>
+#include <device/pnp_ops.h>
 #include <device/pci_ops.h>
 #include <device/pci_def.h>
 #include <device/pnp_def.h>

src/mainboard/lenovo/z61t/romstage.c

@@ -20,6 +20,7 @@
 #include <stdint.h>
 #include <string.h>
 #include <arch/io.h>
+#include <device/pnp_ops.h>
 #include <device/pci_ops.h>
 #include <device/pci_def.h>
 #include <device/pnp_def.h>

src/mainboard/msi/ms7721/romstage.c

@@ -16,6 +16,7 @@
  */
 
 #include <arch/io.h>
+#include <device/pnp_ops.h>
 #include <device/pci_ops.h>
 #include <device/pnp.h>
 #include <stdint.h>

src/mainboard/msi/ms9652_fam10/romstage.c

@@ -20,6 +20,7 @@
 #include <device/pci_def.h>
 #include <device/pci_ids.h>
 #include <arch/io.h>
+#include <device/pnp_ops.h>
 #include <device/pci_ops.h>
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>

src/mainboard/roda/rk886ex/romstage.c

@@ -19,6 +19,7 @@
 #include <stdint.h>
 #include <string.h>
 #include <arch/io.h>
+#include <device/pnp_ops.h>
 #include <device/pci_ops.h>
 #include <device/pci_def.h>
 #include <cpu/x86/lapic.h>

src/mainboard/roda/rk9/romstage.c

@@ -17,6 +17,7 @@
 /* __PRE_RAM__ means: use "unsigned" for device, not a struct. */
 
 #include <arch/io.h>
+#include <device/pnp_ops.h>
 #include <device/pci_ops.h>
 #include <southbridge/intel/common/gpio.h>
 #include <southbridge/intel/i82801ix/i82801ix.h>

src/mainboard/roda/rv11/variants/rw11/romstage.c

@@ -16,6 +16,7 @@
 #include <stdint.h>
 #include <device/pci.h>
 #include <device/pci_ops.h>
+#include <device/pnp_ops.h>
 #include <device/pnp.h>
 #include <northbridge/intel/sandybridge/raminit.h>
 #include <northbridge/intel/sandybridge/raminit_native.h>

src/mainboard/supermicro/h8qme_fam10/romstage.c

@@ -20,6 +20,7 @@
 #include <device/pci_def.h>
 #include <device/pci_ids.h>
 #include <arch/io.h>
+#include <device/pnp_ops.h>
 #include <device/pci_ops.h>
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>

src/mainboard/supermicro/x10slm-f/romstage.c

@@ -17,6 +17,7 @@
 
 #include <cpu/intel/haswell/haswell.h>
 #include <cpu/intel/romstage.h>
+#include <device/pnp_ops.h>
 #include <northbridge/intel/haswell/haswell.h>
 #include <northbridge/intel/haswell/pei_data.h>
 #include <southbridge/intel/common/gpio.h>

src/superio/fintek/common/early_serial.c

@@ -34,6 +34,7 @@
  */
 
 #include <arch/io.h>
+#include <device/pnp_ops.h>
 #include <device/pnp.h>
 #include <stdint.h>
 #include "fintek.h"

src/superio/fintek/common/fintek.h

@@ -17,7 +17,7 @@
 #ifndef SUPERIO_FINTEK_COMMON_PRE_RAM_H
 #define SUPERIO_FINTEK_COMMON_PRE_RAM_H
 
-#include <arch/io.h>
+#include <device/pnp_type.h>
 #include <stdint.h>
 
 void fintek_enable_serial(pnp_devfn_t dev, u16 iobase);

src/superio/fintek/f81216h/early_serial.c

@@ -15,6 +15,7 @@
  */
 
 #include <arch/io.h>
+#include <device/pnp_ops.h>
 #include <device/pnp.h>
 #include <stdint.h>
 #include "f81216h.h"

src/superio/fintek/f81216h/f81216h.h

@@ -17,6 +17,8 @@
 #ifndef SUPERIO_FINTEK_F81216H_H
 #define SUPERIO_FINTEK_F81216H_H
 
+#include <device/pnp_type.h>
+
 /* Logical Device Numbers (LDN). */
 #define F81216H_SP1    0x00	/* UART1 (+CIR mode) */
 #define F81216H_SP2    0x01	/* UART2 */

src/superio/intel/i8900/early_serial.c

@@ -15,6 +15,7 @@
  */
 
 #include <arch/io.h>
+#include <device/pnp_ops.h>
 #include <device/pnp.h>
 #include "i8900.h"
 

src/superio/intel/i8900/i8900.h

@@ -17,6 +17,8 @@
 #ifndef SUPERIO_INTEL_I8900_I8900_H
 #define SUPERIO_INTEL_I8900_I8900_H
 
+#include <device/pnp_type.h>
+
 /*
  * The SIW ("Serial I/O and Watchdog Timer") integrated into the i8900 is
  * very similar to a Super I/O, both in functionality and config mechanism.

src/superio/ite/common/early_serial.c

@@ -16,6 +16,7 @@
  */
 
 #include <arch/io.h>
+#include <device/pnp_ops.h>
 #include <device/pnp.h>
 #include <stdint.h>
 #include "ite.h"

src/superio/ite/common/ite.h

@@ -17,7 +17,7 @@
 #ifndef SUPERIO_ITE_COMMON_PRE_RAM_H
 #define SUPERIO_ITE_COMMON_PRE_RAM_H
 
-#include <arch/io.h>
+#include <device/pnp_type.h>
 #include <stdint.h>
 
 #define ITE_UART_CLK_PREDIVIDE_48 0x00 /* default */

src/superio/ite/it8671f/early_serial.c

@@ -15,6 +15,7 @@
  */
 
 #include <arch/io.h>
+#include <device/pnp_type.h>
 #include <device/pnp.h>
 #include <stdint.h>
 #include "it8671f.h"

src/superio/ite/it8671f/it8671f.h

@@ -17,7 +17,7 @@
 #ifndef SUPERIO_ITE_IT8671F_H
 #define SUPERIO_ITE_IT8671F_H
 
-#include <arch/io.h>
+#include <device/pnp_type.h>
 #include <stdint.h>
 
 /* Datasheet: Not available online, got it from ITE per request. */

src/superio/ite/it8718f/early_serial.c

@@ -14,7 +14,7 @@
  * GNU General Public License for more details.
  */
 
-#include <arch/io.h>
+#include <device/pnp_type.h>
 #include <superio/ite/common/ite.h>
 #include "it8718f.h"
 

src/superio/ite/it8718f/it8718f.h

@@ -17,7 +17,7 @@
 #ifndef SUPERIO_ITE_IT8718F_H
 #define SUPERIO_ITE_IT8718F_H
 
-#include <arch/io.h>
+#include <device/pnp_type.h>
 
 /* Datasheet: http://www.ite.com.tw/product_info/PC/Brief-IT8718_2.asp */
 

src/superio/ite/it8772f/early_init.c

@@ -15,6 +15,7 @@
  */
 
 #include <arch/io.h>
+#include <device/pnp_ops.h>
 
 #include "it8772f.h"
 

src/superio/ite/it8772f/it8772f.h

@@ -126,7 +126,7 @@ enum thermal_mode {
 /* GPIO Mode: 0: input mode, 1: output mode */
 #define GPIO_REG_OUTPUT(x)   (0xc8 + (x))
 
-#include <arch/io.h>
+#include <device/pnp_type.h>
 #include <stdint.h>
 
 u8 it8772f_sio_read(pnp_devfn_t dev, u8 reg);

src/superio/nsc/common/early_serial.c

@@ -17,7 +17,7 @@
  * GNU General Public License for more details.
  */
 
-#include <arch/io.h>
+#include <device/pnp_ops.h>
 #include <device/pnp_def.h>
 #include <stdint.h>
 #include "nsc.h"

src/superio/nsc/common/nsc.h

@@ -20,6 +20,7 @@
 
 #include <device/pnp_def.h>
 #include <stdint.h>
+#include <device/pnp_type.h>
 
 void nsc_enable_serial(pnp_devfn_t dev, u16 iobase);
 

src/superio/nsc/pc87417/early_init.c

@@ -17,6 +17,7 @@
  */
 
 #include <arch/io.h>
+#include <device/pnp_ops.h>
 #include <device/pnp.h>
 #include <stdint.h>
 #include "pc87417.h"

src/superio/nsc/pc87417/pc87417.h

@@ -110,7 +110,7 @@
 #define PC87417_XSCNF		0x15
 #define PC87417_XWBCNF		0x16
 
-#include <arch/io.h>
+#include <device/pnp_type.h>
 #include <stdint.h>
 
 void pc87417_disable_dev(pnp_devfn_t dev);

src/superio/nsc/pc97317/early_serial.c

@@ -15,6 +15,7 @@
  */
 
 #include <arch/io.h>
+#include <device/pnp_ops.h>
 #include <device/pnp.h>
 #include <stdint.h>
 #include "pc97317.h"

src/superio/nsc/pc97317/pc97317.h

@@ -27,7 +27,7 @@
 #define PC97317_GPIO 0x07
 #define PC97317_PM   0x08 /* Power Management */
 
-#include <arch/io.h>
+#include <device/pnp_type.h>
 #include <stdint.h>
 
 void pc97317_enable_serial(pnp_devfn_t dev, u16 iobase);

src/superio/nuvoton/common/early_serial.c

@@ -36,6 +36,7 @@
  */
 
 #include <arch/io.h>
+#include <device/pnp_ops.h>
 #include <device/pnp.h>
 #include <stdint.h>
 #include "nuvoton.h"

src/superio/nuvoton/common/nuvoton.h

@@ -18,7 +18,7 @@
 #ifndef SUPERIO_NUVOTON_COMMON_PRE_RAM_H
 #define SUPERIO_NUVOTON_COMMON_PRE_RAM_H
 
-#include <arch/io.h>
+#include <device/pnp_type.h>
 #include <stdint.h>
 
 void nuvoton_pnp_enter_conf_state(pnp_devfn_t dev);

src/superio/nuvoton/nct5104d/early_init.c

@@ -15,6 +15,7 @@
  */
 
 #include <arch/io.h>
+#include <device/pnp_type.h>
 #include <device/pnp.h>
 #include <stdint.h>
 #include "nct5104d.h"

src/superio/nuvoton/nct5104d/nct5104d.h

@@ -18,6 +18,8 @@
 #ifndef SUPERIO_NUVOTON_NCT5104D_H
 #define SUPERIO_NUVOTON_NCT5104D_H
 
+#include <device/pnp_type.h>
+
 /* SIO global configuration */
 #define IRQ_TYPE_SEL_CR10   0x10     /* UARTA,UARTB */
 #define IRQ_TYPE_SEL_CR11   0x11     /* SMI,UARTC,UARTD,WDTO */

src/superio/nuvoton/wpcm450/early_init.c

@@ -15,6 +15,7 @@
  */
 
 #include <arch/io.h>
+#include <device/pnp_ops.h>
 #include <device/pnp_def.h>
 #include "wpcm450.h"
 

src/superio/serverengines/pilot/early_init.c

@@ -19,7 +19,7 @@
 
 #define BLUBB_DEV PNP_DEV(port, 0x04)
 
-#include <arch/io.h>
+#include <device/pnp_ops.h>
 #include <console/console.h>
 #include <device/pnp.h>
 #include "pilot.h"

src/superio/serverengines/pilot/early_serial.c

@@ -18,6 +18,7 @@
 /* PILOT Super I/O is only based on LPC observation done on factory system. */
 
 #include <arch/io.h>
+#include <device/pnp_ops.h>
 #include <device/pnp.h>
 #include "pilot.h"
 

src/superio/serverengines/pilot/pilot.h

@@ -18,6 +18,8 @@
 #ifndef SUPERIO_SERVERENGINES_PILOT_PILOT_H
 #define SUPERIO_SERVERENGINES_PILOT_PILOT_H
 
+#include <device/pnp_type.h>
+
 /* PILOT Super I/O is only based on LPC observation done on factory system. */
 
 #define PILOT_LD1 0x01 /* Logical device 1 */

src/superio/smsc/dme1737/dme1737.h

@@ -26,7 +26,7 @@
 #define DME1737_KBC		7	/* Keyboard & Mouse */
 #define DME1737_RT		10	/* Runtime reg*/
 
-#include <arch/io.h>
+#include <device/pnp_type.h>
 #include <stdint.h>
 
 void dme1737_enable_serial(pnp_devfn_t dev, u16 iobase);

src/superio/smsc/dme1737/early_serial.c

@@ -17,6 +17,7 @@
  */
 
 #include <arch/io.h>
+#include <device/pnp_ops.h>
 #include <device/pnp.h>
 #include <stdint.h>
 #include "dme1737.h"

src/superio/smsc/kbc1100/early_init.c

@@ -17,6 +17,7 @@
 /* Pre-RAM driver for the SMSC KBC1100 Super I/O chip */
 
 #include <arch/io.h>
+#include <device/pnp_ops.h>
 #include <device/pnp.h>
 #include <stdint.h>
 

src/superio/smsc/kbc1100/kbc1100.h

@@ -17,7 +17,7 @@
 #ifndef SUPERIO_SMSC_KBC1100_H
 #define SUPERIO_SMSC_KBC1100_H
 
-#include <arch/io.h>
+#include <device/pnp_type.h>
 #include <stdint.h>
 
 #define KBC1100_PM1              1            /* PM1 */

src/superio/smsc/lpc47b272/early_serial.c

@@ -17,6 +17,7 @@
 /* Pre-RAM driver for SMSC LPC47B272 Super I/O chip. */
 
 #include <arch/io.h>
+#include <device/pnp_ops.h>
 #include <device/pnp.h>
 #include <stdint.h>
 #include "lpc47b272.h"

src/superio/smsc/lpc47b272/lpc47b272.h

@@ -26,7 +26,7 @@
 
 #define LPC47B272_MAX_CONFIG_REGISTER	0x5F
 
-#include <arch/io.h>
+#include <device/pnp_type.h>
 #include <stdint.h>
 
 void lpc47b272_enable_serial(pnp_devfn_t dev, u16 iobase);

src/superio/smsc/lpc47b397/early_serial.c

@@ -17,6 +17,7 @@
  */
 
 #include <arch/io.h>
+#include <device/pnp_ops.h>
 #include <device/pnp.h>
 #include <stdint.h>
 #include "lpc47b397.h"

src/superio/smsc/lpc47b397/lpc47b397.h

@@ -27,7 +27,7 @@
 #define LPC47B397_HWM		8	/* HW Monitor */
 #define LPC47B397_RT		10	/* Runtime reg*/
 
-#include <arch/io.h>
+#include <device/pnp_type.h>
 #include <stdint.h>
 
 void lpc47b397_enable_serial(pnp_devfn_t dev, u16 iobase);

src/superio/smsc/lpc47m10x/early_serial.c

@@ -15,6 +15,7 @@
  */
 
 #include <arch/io.h>
+#include <device/pnp_ops.h>
 #include <device/pnp.h>
 #include <stdint.h>
 #include "lpc47m10x.h"

src/superio/smsc/lpc47m10x/lpc47m10x.h

@@ -30,7 +30,7 @@
 
 #define LPC47M10X2_MAX_CONFIG_REGISTER	0x5F
 
-#include <arch/io.h>
+#include <device/pnp_type.h>
 #include <stdint.h>
 
 void lpc47m10x_enable_serial(pnp_devfn_t dev, u16 iobase);

src/superio/smsc/lpc47m15x/early_serial.c

@@ -16,6 +16,7 @@
 /* Pre-RAM driver for the SMSC LPC47M15X Super I/O chip */
 
 #include <arch/io.h>
+#include <device/pnp_ops.h>
 #include <device/pnp.h>
 #include <stdint.h>
 

src/superio/smsc/lpc47m15x/lpc47m15x.h

@@ -27,7 +27,7 @@
 
 #define LPC47M15X2_MAX_CONFIG_REGISTER	0x5F
 
-#include <arch/io.h>
+#include <device/pnp_type.h>
 #include <stdint.h>
 
 void lpc47m15x_enable_serial(pnp_devfn_t dev, u16 iobase);

src/superio/smsc/lpc47n217/early_serial.c

@@ -17,6 +17,7 @@
 /* Pre-RAM driver for SMSC LPC47N217 Super I/O chip. */
 
 #include <arch/io.h>
+#include <device/pnp_ops.h>
 #include <assert.h>
 #include "lpc47n217.h"
 

src/superio/smsc/lpc47n217/lpc47n217.h

@@ -17,7 +17,7 @@
 #ifndef SUPERIO_SMSC_LPC47N217_LPC47N217_H
 #define SUPERIO_SMSC_LPC47N217_LPC47N217_H
 
-#include <arch/io.h>
+#include <device/pnp_type.h>
 #include <stdint.h>
 
 /*

src/superio/smsc/lpc47n227/early_serial.c

@@ -17,6 +17,7 @@
 /* Pre-RAM driver for SMSC LPC47N227 Super I/O chip. */
 
 #include <arch/io.h>
+#include <device/pnp_ops.h>
 #include "lpc47n227.h"
 
 void pnp_enter_conf_state(pnp_devfn_t dev)

src/superio/smsc/lpc47n227/lpc47n227.h

@@ -16,6 +16,8 @@
 #ifndef SUPERIO_SMSC_LPC47N227_LPC47N227_H
 #define SUPERIO_SMSC_LPC47N227_LPC47N227_H
 
+#include <device/pnp_type.h>
+
 /*
  * Since the LPC47N227 does not have logical devices but a flat configuration
  * space, these are arbitrary, but must match declarations in the mainboard

src/superio/smsc/sch4037/sch4037_early_init.c

@@ -15,6 +15,7 @@
 
 
 #include <arch/io.h>
+#include <device/pnp_ops.h>
 #include <device/pnp.h>
 #include <stdint.h>
 

src/superio/smsc/sio1036/sio1036.h

@@ -22,7 +22,7 @@
 #define LPT_POWER_DOWN		(1 << 2)
 #define IR_OUTPUT_MUX		(1 << 6)
 
-#include <arch/io.h>
+#include <device/pnp_type.h>
 #include <stdint.h>
 
 void sio1036_enable_serial(pnp_devfn_t dev, u16 iobase);

src/superio/smsc/sio1036/sio1036_early_init.c

@@ -16,6 +16,7 @@
 /* Pre-RAM driver for the SMSC KBC1100 Super I/O chip */
 
 #include <arch/io.h>
+#include <device/pnp_ops.h>
 #include <stdint.h>
 
 #include "sio1036.h"

src/superio/smsc/smscsuperio/early_serial.c

@@ -16,6 +16,7 @@
  */
 
 #include <arch/io.h>
+#include <device/pnp_ops.h>
 #include <device/pnp_def.h>
 #include <stdint.h>
 

src/superio/smsc/smscsuperio/smscsuperio.h

@@ -17,7 +17,7 @@
 #ifndef SUPERIO_SMSC_SMSCSUPERIO_H
 #define SUPERIO_SMSC_SMSCSUPERIO_H
 
-#include <arch/io.h>
+#include <device/pnp_type.h>
 #include <stdint.h>
 
 /* All known/supported SMSC Super I/Os have the same logical device IDs

src/superio/winbond/common/early_init.c

@@ -34,6 +34,7 @@
  */
 
 #include <arch/io.h>
+#include <device/pnp_ops.h>
 #include <device/pnp.h>
 #include <stdint.h>
 #include "winbond.h"

src/superio/winbond/common/winbond.h

@@ -17,7 +17,7 @@
 #ifndef SUPERIO_WINBOND_COMMON_PRE_RAM_H
 #define SUPERIO_WINBOND_COMMON_PRE_RAM_H
 
-#include <arch/io.h>
+#include <device/pnp_type.h>
 #include <stdint.h>
 
 void winbond_enable_serial(pnp_devfn_t dev, uint16_t iobase);

src/superio/winbond/w83627dhg/early_serial.c

@@ -16,6 +16,7 @@
  */
 
 #include <arch/io.h>
+#include <device/pnp_ops.h>
 #include <stdint.h>
 #include "w83627dhg.h"
 

src/superio/winbond/w83627dhg/w83627dhg.h

@@ -18,7 +18,7 @@
 #ifndef SUPERIO_WINBOND_W83627DHG_H
 #define SUPERIO_WINBOND_W83627DHG_H
 
-#include <arch/io.h>
+#include <device/pnp_type.h>
 
 #define W83627DHG_FDC              0   /* Floppy */
 #define W83627DHG_PP               1   /* Parallel port */

src/superio/winbond/w83627thg/w83627thg.h

@@ -19,7 +19,7 @@
 #ifndef SUPERIO_WINBOND_W83627THG_W83627THG_H
 #define SUPERIO_WINBOND_W83627THG_W83627THG_H
 
-#include <arch/io.h>
+#include <device/pnp_type.h>
 
 #define W83627THG_FDC              0   /* Floppy */
 #define W83627THG_PP               1   /* Parallel port */

src/superio/winbond/wpcd376i/early_serial.c

@@ -17,7 +17,7 @@
 /* Pre-RAM driver for the Winbond WPCD376I Super I/O chip. */
 
 
-#include <arch/io.h>
+#include <device/pnp_ops.h>
 #include <device/pnp_def.h>
 #include "wpcd376i.h"
 

src/superio/winbond/wpcd376i/wpcd376i.h

@@ -18,7 +18,7 @@
 #ifndef SUPERIO_WINBOND_WPCD376I_WPCD376I_H
 #define SUPERIO_WINBOND_WPCD376I_WPCD376I_H
 
-#include <arch/io.h>
+#include <device/pnp_type.h>
 
 /* Logical Device Numbers (LDN). */
 #define WPCD376I_FDC	0x00  /* Floppy */