cpu/amd/model_10xxx: Clean up debugging statements
Change-Id: I6dff74b3857e1fb384aefc87b44e7679bd4aab07 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/11948 Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com> Tested-by: build bot (Jenkins)
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@ -460,7 +460,7 @@ static void config_clk_power_ctrl_reg0(int node, u32 cpuRev, u8 procPkg) {
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static void config_power_ctrl_misc_reg(device_t dev,u32 cpuRev, u8 procPkg) {
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static void config_power_ctrl_misc_reg(device_t dev,u32 cpuRev, u8 procPkg) {
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/* check PVI/SVI */
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/* check PVI/SVI */
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u32 dword = pci_read_config32(dev, 0xA0);
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u32 dword = pci_read_config32(dev, 0xa0);
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/* BKDG r31116 2010-04-22 2.4.1.7 step b F3xA0[VSSlamVidMod] */
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/* BKDG r31116 2010-04-22 2.4.1.7 step b F3xA0[VSSlamVidMod] */
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/* PllLockTime and PsiVidEn set in ruleset in defaults.h */
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/* PllLockTime and PsiVidEn set in ruleset in defaults.h */
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@ -488,7 +488,7 @@ static void config_power_ctrl_misc_reg(device_t dev,u32 cpuRev, u8 procPkg) {
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dword |= SVI_HIGH_FREQ_ON;
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dword |= SVI_HIGH_FREQ_ON;
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}
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}
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#endif
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#endif
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pci_write_config32(dev, 0xA0, dword);
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pci_write_config32(dev, 0xa0, dword);
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}
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}
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static void config_nb_syn_ptr_adj(device_t dev, u32 cpuRev) {
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static void config_nb_syn_ptr_adj(device_t dev, u32 cpuRev) {
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@ -608,8 +608,6 @@ static void prep_fid_change(void)
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printk(BIOS_DEBUG, " F3xD8: %08x\n", dword);
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printk(BIOS_DEBUG, " F3xD8: %08x\n", dword);
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dword = pci_read_config32(dev, 0xDC);
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dword = pci_read_config32(dev, 0xDC);
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printk(BIOS_DEBUG, " F3xDC: %08x\n", dword);
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printk(BIOS_DEBUG, " F3xDC: %08x\n", dword);
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}
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}
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}
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}
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