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intel/lynxpoint: remove explicit pcie config accesses 

Now that MMCONF_SUPPORT_DEFAULT is enabled by default remove
the pcie explicit accesses. The default config accesses use
MMIO.

Change-Id: I71923790aa03e51db01ae3a4745e1c44556d281f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3812
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
This commit is contained in:
Kyösti Mälkki 2013-07-26 08:52:49 +03:00
parent ef84401149
commit 386b3e631f
2 changed files with 18 additions and 18 deletions
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18
src/southbridge/intel/lynxpoint/azalia.c
View File

@ -252,28 +252,28 @@ static void azalia_init(struct device *dev)
printk(BIOS_DEBUG, "Azalia: base = %08x\n", (u32)base); printk(BIOS_DEBUG, "Azalia: base = %08x\n", (u32)base);
if (RCBA32(0x2030) & (1 << 31)) { if (RCBA32(0x2030) & (1 << 31)) {
reg32 = pci_mmio_read_config32(dev, 0x120); reg32 = pci_read_config32(dev, 0x120);
reg32 &= 0xf8ffff01; reg32 &= 0xf8ffff01;
reg32 |= (1 << 24); // 25 for server reg32 |= (1 << 24); // 25 for server
reg32 |= RCBA32(0x2030) & 0xfe; reg32 |= RCBA32(0x2030) & 0xfe;
pci_mmio_write_config32(dev, 0x120, reg32); pci_write_config32(dev, 0x120, reg32);
reg16 = pci_mmio_read_config16(dev, 0x78); reg16 = pci_read_config16(dev, 0x78);
reg16 &= ~(1 << 11); reg16 &= ~(1 << 11);
pci_mmio_write_config16(dev, 0x78, reg16); pci_write_config16(dev, 0x78, reg16);
} else } else
printk(BIOS_DEBUG, "Azalia: V1CTL disabled.\n"); printk(BIOS_DEBUG, "Azalia: V1CTL disabled.\n");
reg32 = pci_mmio_read_config32(dev, 0x114); reg32 = pci_read_config32(dev, 0x114);
reg32 &= ~0xfe; reg32 &= ~0xfe;
pci_mmio_write_config32(dev, 0x114, reg32); pci_write_config32(dev, 0x114, reg32);
// Set VCi enable bit // Set VCi enable bit
if (pci_mmio_read_config32(dev, 0x120) & ((1 << 24) | if (pci_read_config32(dev, 0x120) & ((1 << 24) |
(1 << 25) | (1 << 26))) { (1 << 25) | (1 << 26))) {
reg32 = pci_mmio_read_config32(dev, 0x120); reg32 = pci_read_config32(dev, 0x120);
reg32 |= (1 << 31); reg32 |= (1 << 31);
pci_mmio_write_config32(dev, 0x120, reg32); pci_write_config32(dev, 0x120, reg32);
} }
// Enable HDMI codec: // Enable HDMI codec:

18
src/southbridge/intel/lynxpoint/pcie.c
View File

@ -141,30 +141,30 @@ static void pch_pcie_pm_late(struct device *dev)
u32 reg32; u32 reg32;
/* Set 0x314 = 0x743a361b */ /* Set 0x314 = 0x743a361b */
pci_mmio_write_config32(dev, 0x314, 0x743a361b); pci_write_config32(dev, 0x314, 0x743a361b);
/* Set 0x318[31:16] = 0x1414 */ /* Set 0x318[31:16] = 0x1414 */
reg32 = pci_mmio_read_config32(dev, 0x318); reg32 = pci_read_config32(dev, 0x318);
reg32 &= 0x0000ffff; reg32 &= 0x0000ffff;
reg32 |= 0x14140000; reg32 |= 0x14140000;
pci_mmio_write_config32(dev, 0x318, reg32); pci_write_config32(dev, 0x318, reg32);
/* Set 0x324[5] = 1 */ /* Set 0x324[5] = 1 */
reg32 = pci_mmio_read_config32(dev, 0x324); reg32 = pci_read_config32(dev, 0x324);
reg32 |= (1 << 5); reg32 |= (1 << 5);
pci_mmio_write_config32(dev, 0x324, reg32); pci_write_config32(dev, 0x324, reg32);
/* Set 0x330[7:0] = 0x40 */ /* Set 0x330[7:0] = 0x40 */
reg32 = pci_mmio_read_config32(dev, 0x330); reg32 = pci_read_config32(dev, 0x330);
reg32 &= ~(0xff); reg32 &= ~(0xff);
reg32 |= 0x40; reg32 |= 0x40;
pci_mmio_write_config32(dev, 0x330, reg32); pci_write_config32(dev, 0x330, reg32);
/* Set 0x33C[24:0] = 0x854c74 */ /* Set 0x33C[24:0] = 0x854c74 */
reg32 = pci_mmio_read_config32(dev, 0x33c); reg32 = pci_read_config32(dev, 0x33c);
reg32 &= 0xff000000; reg32 &= 0xff000000;
reg32 |= 0x00854c74; reg32 |= 0x00854c74;
pci_mmio_write_config32(dev, 0x33c, reg32); pci_write_config32(dev, 0x33c, reg32);
/* No IO-APIC, Disable EOI forwarding */ /* No IO-APIC, Disable EOI forwarding */
reg32 = pci_read_config32(dev, 0xd4); reg32 = pci_read_config32(dev, 0xd4);