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riscv: add support to check ISA extension

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Add support to check ISA extension for RISC-V.

Change-Id: I5982fb32ed1dd435059edc6aa0373bffa899e160
Signed-off-by: Xiang Wang <wxjstz@126.com>
Reviewed-on: https://review.coreboot.org/27410
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Philipp Hug <philipp@hug.cx>
This commit is contained in:
Xiang Wang 2018-07-09 11:54:09 +08:00 committed by Patrick Georgi
parent 654a45d2ad
commit 387417be03
1 changed files with 7 additions and 0 deletions
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7
src/arch/riscv/include/arch/cpu.h
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@ -16,6 +16,8 @@
#ifndef __ARCH_CPU_H__ #ifndef __ARCH_CPU_H__
#define __ARCH_CPU_H__ #define __ARCH_CPU_H__
#include <arch/encoding.h>
#define asmlinkage #define asmlinkage
#if !defined(__PRE_RAM__) #if !defined(__PRE_RAM__)
@ -44,5 +46,10 @@ struct cpuinfo_riscv {
#endif #endif
static inline int supports_extension(char ext)
{
return read_csr(misa) & (1 << (ext - 'A'));
}
struct cpu_info *cpu_info(void); struct cpu_info *cpu_info(void);
#endif /* __ARCH_CPU_H__ */ #endif /* __ARCH_CPU_H__ */