mb/google/rex: Enable asynchronous End-Of-Post
Set the `SOC_INTEL_CSE_SEND_EOP_ASYNC' flag to request End-Of-Post right after PCI enumeration and handle the command response at `BS_PAYLOAD_BOOT'. With these settings we have observed a boot time reduction of about 100ms on google/rex. TEST=Tests on google/rex with `SOC_INTEL_CSE_SEND_EOP_ASYNC' show End-Of-Post after PCI initialization and EOP message received at `BS_PAYLOAD_BOOT'. Change-Id: I27b540eeddcada521eba91fcc51504831d6dc855 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74562 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
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@ -27,6 +27,7 @@ config BOARD_GOOGLE_REX_COMMON
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select PMC_IPC_ACPI_INTERFACE
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select PMC_IPC_ACPI_INTERFACE
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select SOC_INTEL_CSE_LITE_SKU
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select SOC_INTEL_CSE_LITE_SKU
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select SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY_V2
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select SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY_V2
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select SOC_INTEL_CSE_SEND_EOP_ASYNC
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config BOARD_GOOGLE_BASEBOARD_REX
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config BOARD_GOOGLE_BASEBOARD_REX
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def_bool n
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def_bool n
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@ -89,7 +89,7 @@ config CPU_SPECIFIC_OPTIONS
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select SOC_INTEL_COMMON_PCH_CLIENT
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select SOC_INTEL_COMMON_PCH_CLIENT
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select SOC_INTEL_COMMON_RESET
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select SOC_INTEL_COMMON_RESET
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select SOC_INTEL_COMMON_BLOCK_IOC
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select SOC_INTEL_COMMON_BLOCK_IOC
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select SOC_INTEL_CSE_SEND_EOP_LATE
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select SOC_INTEL_CSE_SEND_EOP_LATE if !MAINBOARD_HAS_CHROMEOS
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select SOC_INTEL_CSE_SET_EOP
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select SOC_INTEL_CSE_SET_EOP
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select SOC_INTEL_GFX_NON_PREFETCHABLE_MMIO
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select SOC_INTEL_GFX_NON_PREFETCHABLE_MMIO
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select SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION
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select SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION
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