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mb/google/rex: Use FW_CONFIG for generating ACPI code for WIFI 

This patch avoids creating runtime ACPI for unused WIFI solutions.
For example: if the Rex SKU is with WIFI_CNVI then you don't need
to populate ACPI code for WIFI_PCIE.

FW_CONIG can be used for making those decisions.

TEST=No ASL entries being created for WIFI_PCIE if the FW_CONIG is
set to WIFI_CNVI.

Also, helped to save the boot time on google/rex (FSP-S API) by 9ms.

Change-Id: I60e4332d8d8c360fdf425b30513ff79209979e85
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74147
Reviewed-by: YH Lin <yueherngl@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This commit is contained in:
Subrata Banik 2023-03-31 23:20:13 +05:30 committed by Felix Held
parent 2014cad94c
commit 389e73a97b
1 changed files with 10 additions and 3 deletions
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13
src/mainboard/google/rex/variants/rex0/overridetree.cb
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@ -248,7 +248,9 @@ chip soc/intel/meteorlake
register "wake" = "GPE0_PME_B0" register "wake" = "GPE0_PME_B0"
register "add_acpi_dma_property" = "true" register "add_acpi_dma_property" = "true"
register "enable_cnvi_ddr_rfim" = "true" register "enable_cnvi_ddr_rfim" = "true"
device generic 0 on end device generic 0 on
probe WIFI WIFI_CNVI
end
end end
end end
device ref ipu on device ref ipu on
@ -500,6 +502,7 @@ chip soc/intel/meteorlake
end end
end #I2C5 end #I2C5
device ref pcie_rp5 on device ref pcie_rp5 on
probe WIFI WIFI_PCIE
# Enable WLAN Card PCIE 5 using clk 5 # Enable WLAN Card PCIE 5 using clk 5
register "pcie_rp[PCH_RP(5)]" = "{ register "pcie_rp[PCH_RP(5)]" = "{
.clk_src = 5, .clk_src = 5,
@ -509,13 +512,17 @@ chip soc/intel/meteorlake
chip drivers/wifi/generic chip drivers/wifi/generic
register "wake" = "GPE0_DW2_09" register "wake" = "GPE0_DW2_09"
register "add_acpi_dma_property" = "true" register "add_acpi_dma_property" = "true"
device pci 00.0 on end device pci 00.0 on
probe WIFI WIFI_PCIE
end
end end
chip soc/intel/common/block/pcie/rtd3 chip soc/intel/common/block/pcie/rtd3
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E22)" register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E22)"
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F08)" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F08)"
register "srcclk_pin" = "5" register "srcclk_pin" = "5"
device generic 0 on end device generic 0 on
probe WIFI WIFI_PCIE
end
end end
end #PCIE5 WLAN card end #PCIE5 WLAN card
device ref pcie_rp6 on device ref pcie_rp6 on