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AGESA f15tn f16kb: Fix ACPI S3 resume for FCH 

This recovers FCH configuration on S3 resume path.
Appearst to work, but other defects of HAVE_ACPI_RESUME
must be fixed also before S3 support is re-enabled.

Change-Id: I8d07d2e9dc161b67d854fcc8ec1da1f36900f989
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21376
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Kyösti Mälkki 2017-07-26 00:57:30 +03:00
parent 8f39f1f097
commit 38aff1ad41
4 changed files with 48 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

17
src/northbridge/amd/agesa/state_machine.c
View File

@ -330,6 +330,7 @@ static void amd_bs_ramstage_init(void *arg)
if (IS_ENABLED(CONFIG_LATE_CBMEM_INIT))
cbmem_initialize();
agesa_execute_state(cb, AMD_S3LATE_RESTORE);
fchs3earlyrestore(&cb->StdHeader);
}
}
@ -351,8 +352,10 @@ static void amd_bs_post_device(void *arg)
{
struct sysinfo *cb = arg;
if (acpi_is_wakeup_s3())
if (acpi_is_wakeup_s3()) {
fchs3laterestore(&cb->StdHeader);
return;
}
agesa_execute_state(cb, AMD_INIT_LATE);
@ -386,3 +389,15 @@ void __attribute__((weak))
board_BeforeInitEnv(struct sysinfo *cb, AMD_ENV_PARAMS *Env) { }
void __attribute__((weak))
board_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *Mid) { }
AGESA_STATUS __attribute__((weak))
fchs3earlyrestore(AMD_CONFIG_PARAMS *StdHeader)
{
return AGESA_SUCCESS;
}
AGESA_STATUS __attribute__((weak))
fchs3laterestore(AMD_CONFIG_PARAMS *StdHeader)
{
return AGESA_SUCCESS;
}

4
src/northbridge/amd/agesa/state_machine.h
View File

@ -38,6 +38,10 @@ AGESA_STATUS OemS3LateRestore(AMD_S3_PARAMS *dataBlock);
AGESA_STATUS OemS3Save(AMD_S3_PARAMS *dataBlock);
#endif
/* For FCH */
AGESA_STATUS fchs3earlyrestore(AMD_CONFIG_PARAMS *StdHeader);
AGESA_STATUS fchs3laterestore(AMD_CONFIG_PARAMS *StdHeader);
struct sysinfo
{
AMD_CONFIG_PARAMS StdHeader;

1
src/southbridge/amd/agesa/hudson/hudson.h
View File

@ -80,7 +80,6 @@ int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos);
#else
void hudson_enable(device_t dev);
void s3_resume_init_data(void *FchParams);
#endif /* __PRE_RAM__ */
#endif /* __SMM__ */

33
src/southbridge/amd/agesa/hudson/resume.c
View File

@ -20,6 +20,8 @@
#include "hudson.h"
#include "AGESA.h"
#include <northbridge/amd/agesa/state_machine.h>
extern FCH_DATA_BLOCK InitEnvCfgDefault;
extern FCH_INTERFACE FchInterfaceDefault;
extern FCH_RESET_DATA_BLOCK InitResetCfgDefault;
@ -27,13 +29,9 @@ extern FCH_RESET_INTERFACE FchResetInterfaceDefault;
#define DUMP_FCH_SETTING 0
void s3_resume_init_data(void *data)
static void s3_resume_init_data(FCH_DATA_BLOCK *FchParams)
{
FCH_DATA_BLOCK *FchParams = (FCH_DATA_BLOCK *)data;
AMD_CONFIG_PARAMS *StdHeader = FchParams->StdHeader;
*FchParams = InitEnvCfgDefault;
FchParams->StdHeader = StdHeader;
FchParams->Usb.Xhci0Enable = InitResetCfgDefault.FchReset.Xhci0Enable;
FchParams->Usb.Xhci1Enable = InitResetCfgDefault.FchReset.Xhci1Enable;
@ -120,3 +118,28 @@ void s3_resume_init_data(void *data)
}
#endif
}
AGESA_STATUS fchs3earlyrestore(AMD_CONFIG_PARAMS *StdHeader)
{
FCH_DATA_BLOCK FchParams;
/* FIXME: Recover FCH_DATA_BLOCK from CBMEM. */
s3_resume_init_data(&FchParams);
FchParams.StdHeader = StdHeader;
FchInitS3EarlyRestore(&FchParams);
return AGESA_SUCCESS;
}
AGESA_STATUS fchs3laterestore(AMD_CONFIG_PARAMS *StdHeader)
{
FCH_DATA_BLOCK FchParams;
/* FIXME: Recover FCH_DATA_BLOCK from CBMEM. */
s3_resume_init_data(&FchParams);
FchParams.StdHeader = StdHeader;
FchInitS3LateRestore(&FchParams);
return AGESA_SUCCESS;
}