amd/stoneyridge: Remove multi-node support
The Stoney Ridge APU can never be used in a multi-node system. Reduce the feature set to a single node. Remove the static variables for each D18Fn device and replace the routines with coreboot config read and write functions. Strip down domain_set_resources() to consider only a single node. A follow-on patch will further simplify this. Change-Id: I1982b3fbf8dbb44ca75112c57afa59a2b4e4cf5a Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21495 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This commit is contained in:
Marshall Dawson
Martin Roth
parent
e2697de821
commit
38bded0eb0
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@ -31,6 +31,7 @@
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#include <agesawrapper.h>
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#include <agesawrapper_call.h>
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#include <soc/northbridge.h>
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#include <soc/pci_devs.h>
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#include <stdint.h>
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#include <stdlib.h>
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#include <string.h>
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@ -46,8 +47,6 @@
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#include <Porting.h>
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#include <Topology.h>
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#define MAX_NODE_NUMS (MAX_NODES * MAX_DIES)
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#if IS_ENABLED(CONFIG_EXT_CONF_SUPPORT)
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#error CONFIG_EXT_CONF_SUPPORT == 1 not support anymore!
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#endif
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@ -57,33 +56,26 @@ typedef struct dram_base_mask {
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u32 mask; /* [47:27] at [28:8] and enable at bit 0 */
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} dram_base_mask_t;
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static unsigned int node_nums;
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static device_t __f0_dev;
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static device_t __f1_dev;
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static device_t __f2_dev;
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static device_t __f4_dev;
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static unsigned int fx_dev = 0;
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static dram_base_mask_t get_dram_base_mask(u32 nodeid)
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static dram_base_mask_t get_dram_base_mask(void)
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{
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device_t dev = __f1_dev;
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device_t dev = dev_find_slot(0, ADDR_DEVFN);
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dram_base_mask_t d;
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u32 temp;
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/* [39:24] at [31:16] */
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temp = pci_read_config32(dev, 0x44 + (nodeid << 3));
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temp = pci_read_config32(dev, 0x44);
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/* mask out DramMask [26:24] too */
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d.mask = ((temp & 0xfff80000) >> (8 + 3));
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/* [47:40] at [7:0] */
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temp = pci_read_config32(dev, 0x144 + (nodeid << 3)) & 0xff;
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temp = pci_read_config32(dev, 0x144) & 0xff;
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d.mask |= temp << 21;
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temp = pci_read_config32(dev, 0x40 + (nodeid << 3));
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temp = pci_read_config32(dev, 0x40);
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d.mask |= (temp & 1); /* enable bit */
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d.base = ((temp & 0xfff80000) >> (8 + 3));
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temp = pci_read_config32(dev, 0x140 + (nodeid << 3)) & 0xff;
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temp = pci_read_config32(dev, 0x140) & 0xff;
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d.base |= temp << 21;
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return d;
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}
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@ -92,54 +84,27 @@ static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg,
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u32 io_min, u32 io_max)
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{
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u32 tempreg;
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device_t addr_map = dev_find_slot(0, ADDR_DEVFN);
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/* io range allocation. Limit */
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tempreg = (nodeid & 0xf) | ((nodeid & 0x30) << (8 - 4)) | (linkn << 4)
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| ((io_max & 0xf0) << (12 - 4));
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pci_write_config32(__f1_dev, reg + 4, tempreg);
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pci_write_config32(addr_map, reg + 4, tempreg);
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tempreg = 3 | ((io_min & 0xf0) << (12 - 4)); /* base: ISA and VGA ? */
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pci_write_config32(__f1_dev, reg, tempreg);
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pci_write_config32(addr_map, reg, tempreg);
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}
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static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index,
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u32 mmio_min, u32 mmio_max)
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{
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u32 tempreg;
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device_t addr_map = dev_find_slot(0, ADDR_DEVFN);
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/* io range allocation. Limit */
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tempreg = (nodeid & 0xf) | (linkn << 4) | (mmio_max & 0xffffff00);
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pci_write_config32(__f1_dev, reg + 4, tempreg);
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pci_write_config32(addr_map, reg + 4, tempreg);
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tempreg = 3 | (nodeid & 0x30) | (mmio_min & 0xffffff00);
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pci_write_config32(__f1_dev, reg, tempreg);
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}
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static device_t get_node_pci(u32 fn)
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{
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return dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB, fn));
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}
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static void get_fx_dev(void)
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{
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__f0_dev = get_node_pci(0);
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__f1_dev = get_node_pci(1);
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__f2_dev = get_node_pci(2);
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__f4_dev = get_node_pci(4);
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fx_dev = 1;
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if (__f1_dev == NULL || __f0_dev == NULL || fx_dev == 0)
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die("Cannot find 0:0x18.[0|1]\n");
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}
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static u32 f1_read_config32(unsigned int reg)
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{
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if (fx_dev == 0)
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get_fx_dev();
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return pci_read_config32(__f1_dev, reg);
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}
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static void f1_write_config32(unsigned int reg, u32 value)
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{
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if (fx_dev == 0)
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get_fx_dev();
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pci_write_config32(__f1_dev, reg, value);
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pci_write_config32(addr_map, reg, tempreg);
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}
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static void read_resources(device_t dev)
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@ -216,7 +181,8 @@ static void create_vga_resource(device_t dev)
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return;
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printk(BIOS_DEBUG, "VGA: %s has VGA device\n", dev_path(dev));
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f1_write_config32(0xf4, 1); /* Route A0000-BFFFF, IO 3B0-3BB 3C0-3DF */
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/* Route A0000-BFFFF, IO 3B0-3BB 3C0-3DF */
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pci_write_config32(dev_find_slot(0, ADDR_DEVFN), 0xf4, 1);
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}
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static void set_resources(device_t dev)
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@ -403,24 +369,23 @@ void fam15_finalize(void *chip_info)
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void domain_read_resources(device_t dev)
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{
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unsigned int reg;
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device_t addr_map = dev_find_slot(0, ADDR_DEVFN);
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/* Find the already assigned resource pairs */
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get_fx_dev();
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for (reg = 0x80 ; reg <= 0xd8 ; reg += 0x08) {
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u32 base, limit;
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base = f1_read_config32(reg);
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limit = f1_read_config32(reg + 0x04);
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base = pci_read_config32(addr_map, reg);
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limit = pci_read_config32(addr_map, reg + 4);
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/* Is this register allocated? */
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if ((base & 3) != 0) {
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unsigned int nodeid, reg_link;
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device_t reg_dev;
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device_t reg_dev = dev_find_slot(0, HT_DEVFN);
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if (reg < 0xc0) /* mmio */
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nodeid = (limit & 0xf) + (base & 0x30);
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else /* io */
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nodeid = (limit & 0xf) + ((base >> 4) & 0x30);
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reg_link = (limit >> 4) & 7;
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reg_dev = __f0_dev;
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if (reg_dev) {
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/* Reserve the resource */
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struct resource *res;
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@ -463,8 +428,8 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void)
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mem_hole.node_id = -1;
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dram_base_mask_t d;
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u32 hole;
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d = get_dram_base_mask(0);
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hole = pci_read_config32(__f1_dev, 0xf0);
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d = get_dram_base_mask();
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hole = pci_read_config32(dev_find_slot(0, ADDR_DEVFN), 0xf0);
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if (hole & 2) {
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/* We found the hole */
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mem_hole.hole_startk = (hole & (0xff << 24)) >> 10;
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@ -479,7 +444,7 @@ void domain_set_resources(device_t dev)
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{
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unsigned long mmio_basek;
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u32 pci_tolm;
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int i, idx;
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int idx;
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struct bus *link;
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#if CONFIG_HW_MEM_HOLE_SIZEK != 0
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struct hw_mem_hole_info mem_hole;
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@ -517,14 +482,12 @@ void domain_set_resources(device_t dev)
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#endif
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idx = 0x10;
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for (i = 0 ; i < node_nums ; i++) {
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dram_base_mask_t d;
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resource_t basek, limitk, sizek; /* 4 1T */
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d = get_dram_base_mask(i);
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d = get_dram_base_mask();
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if (!(d.mask & 1))
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continue;
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if ((d.mask & 1)) { /* if enabled... */
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/* could overflow, we may lose 6 bit here */
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basek = ((resource_t)(d.base & 0x1fffff00)) << 9;
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limitk = ((resource_t)(((d.mask & ~1) + 0x000ff)
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@ -535,7 +498,7 @@ void domain_set_resources(device_t dev)
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/* see if we need a hole from 0xa0000 to 0xbffff */
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if ((basek < ((8 * 64) + (8 * 16))) && (sizek > ((8 * 64) +
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(16 * 16)))) {
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ram_resource(dev, (idx | i), basek,
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ram_resource(dev, idx, basek,
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((8 * 64) + (8 * 16)) - basek);
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idx += 0x10;
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basek = (8 * 64) + (16 * 16);
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@ -549,7 +512,7 @@ void domain_set_resources(device_t dev)
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unsigned int pre_sizek;
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pre_sizek = mmio_basek - basek;
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if (pre_sizek > 0) {
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ram_resource(dev, (idx | i), basek,
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ram_resource(dev, idx, basek,
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pre_sizek);
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idx += 0x10;
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sizek -= pre_sizek;
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@ -565,11 +528,9 @@ void domain_set_resources(device_t dev)
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}
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}
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ram_resource(dev, (idx | i), basek, sizek);
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idx += 0x10;
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printk(BIOS_DEBUG, "node %d: mmio_basek=%08lx, basek=%08llx,"
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" limitk=%08llx\n", i, mmio_basek, basek,
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limitk);
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ram_resource(dev, idx, basek, sizek);
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printk(BIOS_DEBUG, "node 0: mmio_basek=%08lx, basek=%08llx,"
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" limitk=%08llx\n", mmio_basek, basek, limitk);
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}
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add_uma_resource_below_tolm(dev, 7);
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@ -588,13 +549,6 @@ void domain_set_resources(device_t dev)
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reserved_ram_resource(dev, 0xc0000, 0xc0000 / KiB, 0x40000 / KiB);
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}
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/* first node */
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static void sysconf_init(device_t dev)
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{
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/* NodeCnt[2:0] */
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node_nums = ((pci_read_config32(dev, 0x60) >> 4) & 7) + 1;
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}
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void cpu_bus_scan(device_t dev)
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{
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struct bus *cpu_bus;
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@ -618,11 +572,6 @@ void cpu_bus_scan(device_t dev)
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CONFIG_CDB);
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die("");
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}
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sysconf_init(dev_mc); /* sets global node_nums */
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if (node_nums != 1)
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die("node_nums != 1. This is an SOC."
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" Something is terribly wrong.");
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/* Get max and actual number of cores */
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pccount = cpuid_ecx(AMD_CPUID_ASIZE_PCCOUNT);
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@ -665,13 +614,12 @@ void cpu_bus_scan(device_t dev)
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for (j = 0 ; j <= siblings ; j++) {
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apic_id = lapicid_start + j;
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printk(BIOS_SPEW, "lapicid_start 0x%x, node 0x%x, core 0x%x,"
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" apicid=0x%x\n", lapicid_start, node_nums,
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j, apic_id);
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printk(BIOS_SPEW, "lapicid_start 0x%x, core 0x%x,"
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" apicid=0x%x\n", lapicid_start, j, apic_id);
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cpu = add_cpu_device(cpu_bus, apic_id, enable_node);
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if (cpu)
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amd_cpu_topology(cpu, node_nums, j);
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amd_cpu_topology(cpu, 1, j);
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}
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}
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