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soc/intel/{cnl,jsl,tgl,ehl,adl}: rename PMC device init/enable callbacks 

The current names of the PMC init/enable callbacks are very confusing.
Rename them.

Change-Id: I69f54f3b4e1ea9a9b4fa5c8dd9c0d454d7cd1283
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57995
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Michael Niewöhner 2021-09-27 23:55:05 +02:00 committed by Felix Held
parent f67f2b0d4c
commit 38bf496366
5 changed files with 20 additions and 20 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
src/soc/intel/alderlake/pmc.c
View File

@ -66,7 +66,7 @@ static void config_deep_sx(uint32_t deepsx_config)
write32(pmcbase + DSX_CFG, reg);
}
static void pmc_init(struct device *dev)
static void soc_pmc_enable(struct device *dev)
{
const config_t *config = config_of_soc();
@ -140,7 +140,7 @@ static void soc_pmc_fill_ssdt(const struct device *dev)
dev_path(dev));
}
static void soc_acpi_mode_init(struct device *dev)
static void soc_pmc_init(struct device *dev)
{
/*
* pmc_set_acpi_mode() should be delayed until BS_DEV_INIT in order
@ -165,8 +165,8 @@ BOOT_STATE_INIT_ENTRY(BS_DEV_INIT_CHIPS, BS_ON_EXIT, pm1_enable_pwrbtn_smi, NULL
struct device_operations pmc_ops = {
.read_resources = soc_pmc_read_resources,
.set_resources = noop_set_resources,
.init = soc_acpi_mode_init,
.enable = pmc_init,
.init = soc_pmc_init,
.enable = soc_pmc_enable,
#if CONFIG(HAVE_ACPI_TABLES)
.acpi_fill_ssdt = soc_pmc_fill_ssdt,
#endif

8
src/soc/intel/cannonlake/pmc.c
View File

@ -84,7 +84,7 @@ static void soc_pmc_read_resources(struct device *dev)
res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
}
static void pmc_init(struct device *dev)
static void soc_pmc_enable(struct device *dev)
{
const config_t *config = config_of_soc();
@ -98,7 +98,7 @@ static void pmc_init(struct device *dev)
config_deep_sx(config->deep_sx_config);
}
static void soc_acpi_mode_init(struct device *dev)
static void soc_pmc_init(struct device *dev)
{
/*
* PMC initialization happens earlier for this SoC because FSP-Silicon
@ -129,8 +129,8 @@ static void pmc_fill_ssdt(const struct device *dev)
struct device_operations pmc_ops = {
.read_resources = soc_pmc_read_resources,
.set_resources = noop_set_resources,
.init = soc_acpi_mode_init,
.enable = pmc_init,
.init = soc_pmc_init,
.enable = soc_pmc_enable,
#if CONFIG(HAVE_ACPI_TABLES)
.acpi_fill_ssdt = pmc_fill_ssdt,
#endif

8
src/soc/intel/elkhartlake/pmc.c
View File

@ -53,7 +53,7 @@ static void config_deep_sx(uint32_t deepsx_config)
write32(pmcbase + DSX_CFG, reg);
}
static void pmc_init(struct device *dev)
static void soc_pmc_enable(struct device *dev)
{
const config_t *config = config_of_soc();
@ -80,7 +80,7 @@ static void soc_pmc_read_resources(struct device *dev)
res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
}
static void soc_acpi_mode_init(struct device *dev)
static void soc_pmc_init(struct device *dev)
{
/*
* pmc_set_acpi_mode() should be delayed until BS_DEV_INIT in order
@ -103,8 +103,8 @@ static void pmc_fill_ssdt(const struct device *dev)
struct device_operations pmc_ops = {
.read_resources = soc_pmc_read_resources,
.set_resources = noop_set_resources,
.init = soc_acpi_mode_init,
.enable = pmc_init,
.init = soc_pmc_init,
.enable = soc_pmc_enable,
#if CONFIG(HAVE_ACPI_TABLES)
.acpi_fill_ssdt = pmc_fill_ssdt,
#endif

8
src/soc/intel/jasperlake/pmc.c
View File

@ -53,7 +53,7 @@ static void config_deep_sx(uint32_t deepsx_config)
write32(pmcbase + DSX_CFG, reg);
}
static void pmc_init(struct device *dev)
static void soc_pmc_enable(struct device *dev)
{
const config_t *config = config_of_soc();
@ -80,7 +80,7 @@ static void soc_pmc_read_resources(struct device *dev)
res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
}
static void soc_acpi_mode_init(struct device *dev)
static void soc_pmc_init(struct device *dev)
{
/*
* pmc_set_acpi_mode() should be delayed until BS_DEV_INIT in order
@ -111,8 +111,8 @@ static void pmc_fill_ssdt(const struct device *dev)
struct device_operations pmc_ops = {
.read_resources = soc_pmc_read_resources,
.set_resources = noop_set_resources,
.init = soc_acpi_mode_init,
.enable = pmc_init,
.init = soc_pmc_init,
.enable = soc_pmc_enable,
#if CONFIG(HAVE_ACPI_TABLES)
.acpi_fill_ssdt = pmc_fill_ssdt,
#endif

8
src/soc/intel/tigerlake/pmc.c
View File

@ -65,7 +65,7 @@ static void config_deep_sx(uint32_t deepsx_config)
write32(pmcbase + DSX_CFG, reg);
}
static void pmc_init(struct device *dev)
static void soc_pmc_enable(struct device *dev)
{
const config_t *config = config_of_soc();
@ -139,7 +139,7 @@ static void soc_pmc_fill_ssdt(const struct device *dev)
dev_path(dev));
}
static void soc_acpi_mode_init(struct device *dev)
static void soc_pmc_init(struct device *dev)
{
/*
* pmc_set_acpi_mode() should be delayed until BS_DEV_INIT in order
@ -164,8 +164,8 @@ BOOT_STATE_INIT_ENTRY(BS_DEV_INIT_CHIPS, BS_ON_EXIT, pm1_enable_pwrbtn_smi, NULL
struct device_operations pmc_ops = {
.read_resources = soc_pmc_read_resources,
.set_resources = noop_set_resources,
.init = soc_acpi_mode_init,
.enable = pmc_init,
.init = soc_pmc_init,
.enable = soc_pmc_enable,
#if CONFIG(HAVE_ACPI_TABLES)
.acpi_fill_ssdt = soc_pmc_fill_ssdt,
#endif