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intel sandy/ivy: Skip SPD loading on S3 resume path 

For S3 resume path SPD is only used for DIMM replacement detection.
As this detection already fails in the case of removal/insertion of
same DIMM, we can rely on cbmem_recovery() failure alone to force
system reset in case someone accidentally does DIMM replacements while
system is suspend-to-ram stage.

Skipping DIMM replacement detection allows skipping slow SPD loading,
thus reducing S3 resume path time by 80ms for every installed DIMM.

Change-Id: I4f2838c05f172d3cb351b027c9b8dd6543ab5944
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17490
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Kyösti Mälkki 2016-11-18 19:25:52 +02:00
parent 4cb44e5645
commit 38cb82222c
1 changed files with 9 additions and 10 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

19
src/northbridge/intel/sandybridge/raminit.c
View File

@ -4235,22 +4235,21 @@ static void init_dram_ddr3(int mobile, int min_tck, int s3resume)
ctrl_cached = (ramctr_timing *)mrc_cache->mrc_data;
}
memset(spds, 0, sizeof(spds));
mainboard_get_spd(spds);
if (!s3resume) {
memset(spds, 0, sizeof(spds));
mainboard_get_spd(spds);
}
/* verify MRC cache for fast boot */
if (ctrl_cached) {
if (!s3resume && ctrl_cached) {
/* check SPD CRC16 to make sure the DIMMs haven't been replaced */
fast_boot = verify_crc16_spds_ddr3(spds, ctrl_cached);
if (!fast_boot)
printk(BIOS_DEBUG, "Stored timings CRC16 mismatch.\n");
if (!fast_boot && s3resume) {
/* Failed S3 resume, reset to come up cleanly */
outb(0x6, 0xcf9);
halt();
}
} else
fast_boot = 0;
} else {
fast_boot = s3resume;
}
if (fast_boot) {
printk(BIOS_DEBUG, "Trying stored timings.\n");