nb/intel/sandybridge: Drop unused parameters
We now use a static variable to handle the sequence length. Tested on Asus P8Z77-V LX2, still boots. Change-Id: Id3115c14336ea128264bd3945a99c52b9796d115 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40984 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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38d901e88d
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@ -243,7 +243,7 @@
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.lfsr_xors = xors, \
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}, \
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}; \
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iosav_write_ssq(ch, n, &ssq); \
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iosav_write_ssq(ch, &ssq); \
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} while (0)
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/* Indexed register helper macros */
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@ -20,7 +20,7 @@
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/* Number of programmed IOSAV subsequences. */
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static unsigned int ssq_count = 0;
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static void iosav_write_ssq(const int ch, const int n, const struct iosav_ssq *ssq)
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static void iosav_write_ssq(const int ch, const struct iosav_ssq *ssq)
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{
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MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(ch, ssq_count)) = ssq->sp_cmd_ctrl.raw;
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MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(ch, ssq_count)) = ssq->subseq_ctrl.raw;
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@ -30,17 +30,16 @@ static void iosav_write_ssq(const int ch, const int n, const struct iosav_ssq *s
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ssq_count++;
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}
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/* length: [1..4] */
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static void iosav_run_queue(const int ch, const u8 loops, const u8 length, const u8 as_timer)
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static void iosav_run_queue(const int ch, const u8 loops, const u8 as_timer)
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{
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MCHBAR32(IOSAV_SEQ_CTL_ch(ch)) = loops | ((ssq_count - 1) << 18) | (as_timer << 22);
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ssq_count = 0;
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}
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static void iosav_run_once(const int ch, const u8 length)
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static void iosav_run_once(const int ch)
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{
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iosav_run_queue(ch, 1, length, 0);
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iosav_run_queue(ch, 1, 0);
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}
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static void sfence(void)
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@ -606,7 +605,7 @@ static void write_reset(ramctr_timing *ctrl)
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*
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* This is actually using the IOSAV state machine as a timer, so refresh is allowed.
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*/
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iosav_run_queue(channel, 1, 1, true);
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iosav_run_queue(channel, 1, 1);
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wait_for_iosav(channel);
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}
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@ -709,7 +708,7 @@ static void write_mrreg(ramctr_timing *ctrl, int channel, int slotrank, int reg,
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0, 0, 0, 0, 0, 0, 0, 0);
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/* Execute command queue */
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iosav_run_once(channel, 3);
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iosav_run_once(channel);
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}
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static u32 make_mr0(ramctr_timing *ctrl, u8 rank)
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@ -846,7 +845,7 @@ void dram_mrscommands(ramctr_timing *ctrl)
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0, 0, 0, 1, 20, 0, 0, 0);
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/* Execute command queue on all channels. Do it four times. */
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iosav_run_queue(BROADCAST_CH, 4, 2, false);
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iosav_run_queue(BROADCAST_CH, 4, 0);
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FOR_ALL_CHANNELS {
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/* Wait for ref drained */
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@ -874,7 +873,7 @@ void dram_mrscommands(ramctr_timing *ctrl)
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0, 0, 0, 0, 31, 0, 0, 0);
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/* Execute command queue */
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iosav_run_once(channel, 1);
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iosav_run_once(channel);
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/* Drain */
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wait_for_iosav(channel);
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@ -1064,7 +1063,7 @@ static void test_timA(ramctr_timing *ctrl, int channel, int slotrank)
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0, 0, 0, 0, 0, 0, 0, 0);
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/* Execute command queue */
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iosav_run_once(channel, 4);
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iosav_run_once(channel);
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wait_for_iosav(channel);
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}
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@ -1330,7 +1329,7 @@ int read_training(ramctr_timing *ctrl)
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0, 0, 0, 0, 0, 0, 0, 0);
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/* Execute command queue */
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iosav_run_once(channel, 1);
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iosav_run_once(channel);
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MCHBAR32(GDCRTRAININGMOD) = (slotrank << 2) | 0x8001;
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@ -1452,7 +1451,7 @@ static void test_timC(ramctr_timing *ctrl, int channel, int slotrank)
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0, 0, 0, 0, 31, 0, 0, 0);
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/* Execute command queue */
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iosav_run_once(channel, 4);
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iosav_run_once(channel);
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wait_for_iosav(channel);
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@ -1485,7 +1484,7 @@ static void test_timC(ramctr_timing *ctrl, int channel, int slotrank)
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0, 0, 0, 0, 18, 0, 0, 0);
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/* Execute command queue */
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iosav_run_once(channel, 4);
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iosav_run_once(channel);
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wait_for_iosav(channel);
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}
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@ -1525,7 +1524,7 @@ static int discover_timC(ramctr_timing *ctrl, int channel, int slotrank)
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0, 0, 0, 0, 18, 0, 0, 0);
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/* Execute command queue */
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iosav_run_once(channel, 1);
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iosav_run_once(channel);
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for (timC = 0; timC <= MAX_TIMC; timC++) {
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FOR_ALL_LANES ctrl->timings[channel][slotrank].lanes[lane].timC = timC;
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@ -1654,7 +1653,7 @@ static void precharge(ramctr_timing *ctrl)
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0, 0, 0, 0, 0, 0, 0, 0);
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/* Execute command queue */
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iosav_run_once(channel, 4);
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iosav_run_once(channel);
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wait_for_iosav(channel);
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}
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@ -1701,7 +1700,7 @@ static void precharge(ramctr_timing *ctrl)
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0, 0, 0, 0, 0, 0, 0, 0);
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/* Execute command queue */
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iosav_run_once(channel, 4);
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iosav_run_once(channel);
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wait_for_iosav(channel);
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}
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@ -1729,7 +1728,7 @@ static void test_timB(ramctr_timing *ctrl, int channel, int slotrank)
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0, 0, 0, 0, 0, 0, 0, 0);
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/* Execute command queue */
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iosav_run_once(channel, 2);
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iosav_run_once(channel);
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wait_for_iosav(channel);
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@ -1853,7 +1852,7 @@ static void adjust_high_timB(ramctr_timing *ctrl)
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0, 0, 0, 0, 31, 0, 0, 0);
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/* Execute command queue */
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iosav_run_once(channel, 4);
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iosav_run_once(channel);
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wait_for_iosav(channel);
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@ -1881,7 +1880,7 @@ static void adjust_high_timB(ramctr_timing *ctrl)
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0, 0, 0, 0, 0, 0, 0, 0);
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/* Execute command queue */
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iosav_run_once(channel, 3);
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iosav_run_once(channel);
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wait_for_iosav(channel);
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FOR_ALL_LANES {
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@ -1917,7 +1916,7 @@ static void write_op(ramctr_timing *ctrl, int channel)
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0, 0, 0, 0, 31, 0, 0, 0);
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/* Execute command queue */
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iosav_run_once(channel, 1);
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iosav_run_once(channel);
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wait_for_iosav(channel);
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}
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@ -1996,7 +1995,7 @@ int write_training(ramctr_timing *ctrl)
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0, 0, 0, 0, 31, 0, 0, 0);
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/* Execute command queue */
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iosav_run_once(channel, 1);
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iosav_run_once(channel);
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wait_for_iosav(channel);
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}
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@ -2091,7 +2090,7 @@ static int test_320c(ramctr_timing *ctrl, int channel, int slotrank)
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0, 0, 0, 0, 18, 0, 0, 0);
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/* Execute command queue */
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iosav_run_once(channel, 4);
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iosav_run_once(channel);
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wait_for_iosav(channel);
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FOR_ALL_LANES {
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@ -2158,7 +2157,7 @@ static void reprogram_320c(ramctr_timing *ctrl)
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0, 0, 0, 0, 31, 0, 0, 0);
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/* Execute command queue */
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iosav_run_once(channel, 1);
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iosav_run_once(channel);
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wait_for_iosav(channel);
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MCHBAR32_OR(SCHED_CBIT_ch(channel), 0x200000);
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@ -2180,7 +2179,7 @@ static void reprogram_320c(ramctr_timing *ctrl)
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0, 0, 0, 0, 31, 0, 0, 0);
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/* Execute command queue */
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iosav_run_once(channel, 1);
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iosav_run_once(channel);
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wait_for_iosav(channel);
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}
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@ -2367,7 +2366,7 @@ static int discover_edges_real(ramctr_timing *ctrl, int channel, int slotrank, i
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0, 0, 0, 0, 0, 0, 0, 0);
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/* Execute command queue */
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iosav_run_once(channel, 4);
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iosav_run_once(channel);
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wait_for_iosav(channel);
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@ -2456,7 +2455,7 @@ int discover_edges(ramctr_timing *ctrl)
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0, 0, 0, 0, 0, 0, 0, 0);
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/* Execute command queue */
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iosav_run_once(channel, 4);
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iosav_run_once(channel);
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wait_for_iosav(channel);
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}
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@ -2507,7 +2506,7 @@ int discover_edges(ramctr_timing *ctrl)
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0, 0, 0, 0, 0, 0, 0, 0);
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/* Execute command queue */
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iosav_run_once(channel, 4);
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iosav_run_once(channel);
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wait_for_iosav(channel);
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}
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@ -2635,7 +2634,7 @@ static int discover_edges_write_real(ramctr_timing *ctrl, int channel, int slotr
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0, 0, 0, 0, 0, 0, 0, 0);
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/* Execute command queue */
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iosav_run_once(channel, 4);
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iosav_run_once(channel);
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wait_for_iosav(channel);
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FOR_ALL_LANES {
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@ -2759,7 +2758,7 @@ static void test_timC_write(ramctr_timing *ctrl, int channel, int slotrank)
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0, 0, 0, 0, 0, 0, 0, 0);
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/* Execute command queue */
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iosav_run_once(channel, 4);
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iosav_run_once(channel);
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wait_for_iosav(channel);
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}
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@ -2976,7 +2975,7 @@ int channel_test(ramctr_timing *ctrl)
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0, 0, 0, 0, 18, 0, 0, 0);
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/* Execute command queue */
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iosav_run_once(channel, 4);
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iosav_run_once(channel);
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wait_for_iosav(channel);
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FOR_ALL_LANES
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@ -3021,7 +3020,7 @@ void channel_scrub(ramctr_timing *ctrl)
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0, 0, 0, 0, 18, 0, 0, 0);
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/* execute command queue */
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iosav_run_once(channel, 3);
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iosav_run_once(channel);
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wait_for_iosav(channel);
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}
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