mb/google/dedede: Fix crossystem wpsw_cur error

Add GPIO_PCH_WP (GPP_C11) to associate GPP_PCH_WP with community
zero.

TEST=Build coreboot, flash, boot to
and log into kernel, execute "wp enable" in console,
execute "crossystem" at kernel prompt and verify that "wpsw_cur"
shows as being "1", Execute "wp disable" in console, execute
"crossystem" at kernel prompt and verify "wpsw_cur" is 0.

Change-Id: Ie4ae1365a7611b8be3e795798c171e3f7ea9e417
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40744
Reviewed-by: Usha P <usha.p@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/mainboard/google/dedede/chromeos.c

@@ -23,8 +23,7 @@ void fill_lb_gpios(struct lb_gpios *gpios)
 
 int get_write_protect_state(void)
 {
-	/* No write protect */
+	return gpio_get(GPIO_PCH_WP);
-	return 0;
 }
 
 void mainboard_chromeos_acpi_generate(void)

src/mainboard/google/dedede/variants/baseboard/gpio.c

@@ -119,7 +119,7 @@ static const struct pad_config gpio_table[] = {
 	/* C10 : GPP_C10/UART0_RTSB */
 	PAD_NC(GPP_C10, NONE),
 	/* C11 : AP_WP_OD */
-	PAD_NC(GPP_C11, NONE),
+	PAD_CFG_GPI(GPP_C11, NONE, DEEP),
 	/* C12 : AP_PEN_DET_ODL */
 	PAD_NC(GPP_C12, NONE),
 	/* C13 : GPP_C13/UART1_TXD */
@@ -444,6 +444,8 @@ const struct pad_config *__weak variant_sleep_gpio_table(size_t *num)
 }
 
 static const struct cros_gpio cros_gpios[] = {
+	CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_COMM0_NAME),
+	CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_COMM0_NAME),
 };
 
 const struct cros_gpio *__weak variant_cros_gpios(size_t *num)

src/mainboard/google/dedede/variants/baseboard/include/baseboard/gpio.h

@@ -14,6 +14,8 @@
 /* eSPI virtual wire reporting */
 #define EC_SCI_GPI	GPE0_ESPI
 
+#define GPIO_PCH_WP	GPP_C11
+
 /* EC wake is LAN_WAKE# which is a special DeepSX wake pin */
 #define GPE_EC_WAKE	GPE0_LAN_WAK