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soc/intel/quark: Add header files for FSP 2.0 

Add the FSP 2.0 header files for Quark.  These files were run through
the drivers/intel/fsp2_0/header_util to convert the data types so that
they are compatible with the coreboot build system.

TEST=Build and run on Galileo Gen2.

Change-Id: I15548888215cc811fa753d30b65e3a19e3f8ff8d
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15863
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Lee Leahy 2016-07-25 07:00:50 -07:00
parent 01728bb2ed
commit 38e0cc0aa4
5 changed files with 450 additions and 0 deletions
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42
src/soc/intel/quark/include/soc/fsp/FspEas.h Normal file
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/** @file
Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
* Neither the name of Intel Corporation nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
THE POSSIBILITY OF SUCH DAMAGE.
This file is automatically generated. Please do NOT modify !!!
**/
#ifndef __FSPEAS_H__
#define __FSPEAS_H__
#include <fsp/upd.h>
#include <soc/fsp/FspmUpd.h>
#include <soc/fsp/FspsUpd.h>
#include <soc/fsp/FsptUpd.h>
#include <fsp/api.h>
#endif /* _FSPEAS_H_ */

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src/soc/intel/quark/include/soc/fsp/FspUpd.h Normal file
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/** @file
Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
* Neither the name of Intel Corporation nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
THE POSSIBILITY OF SUCH DAMAGE.
This file is automatically generated. Please do NOT modify !!!
**/
#ifndef __FSPUPD_H__
#define __FSPUPD_H__
#include <FspEas.h>
#define FSPT_UPD_SIGNATURE 0x545F4450554B5251 /* 'QRKUPD_T' */
#define FSPM_UPD_SIGNATURE 0x4D5F4450554B5251 /* 'QRKUPD_M' */
#define FSPS_UPD_SIGNATURE 0x535F4450554B5251 /* 'QRKUPD_S' */
#endif

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src/soc/intel/quark/include/soc/fsp/FspmUpd.h Normal file
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/** @file
Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
* Neither the name of Intel Corporation nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
THE POSSIBILITY OF SUCH DAMAGE.
This file is automatically generated. Please do NOT modify !!!
**/
#ifndef __FSPMUPD_H__
#define __FSPMUPD_H__
#include <FspUpd.h>
/** Fsp M Configuration
**/
struct FSP_M_CONFIG {
/** Offset 0x0040 - RmuBaseAddress
RMU microcode binary base address in SPI flash'
**/
uint32_t RmuBaseAddress;
/** Offset 0x0044 - RmuLength
RMU microcode binary length in bytes
**/
uint32_t RmuLength;
/** Offset 0x0048 - SerialPortBaseAddress
Debug serial port base address set by BIOS. Zero disables debug serial output.
**/
uint32_t SerialPortBaseAddress;
/** Offset 0x004C - tRAS
ACT to PRE command period in picoseconds.
**/
uint32_t tRAS;
/** Offset 0x0050 - tWTR
Delay from start of internal write transaction to internal read command in picoseconds.
**/
uint32_t tWTR;
/** Offset 0x0054 - tRRD
ACT to ACT command period (JESD79 specific to page size 1K/2K) in picoseconds.
**/
uint32_t tRRD;
/** Offset 0x0058 - tFAW
Four activate window (JESD79 specific to page size 1K/2K) in picoseconds.
**/
uint32_t tFAW;
/** Offset 0x005C - Flags
Bitmap of MRC_FLAG_XXX: ECC_EN BIT0, SCRAMBLE_EN BIT1, MEMTEST_EN
BIT2, TOP_TREE_EN BIT3 0b DDR "fly-by" topology else 1b DDR "tree"
topology, WR_ODT_EN BIT4 If set ODR signal is asserted to DRAM devices
on writes.
**/
uint32_t Flags;
/** Offset 0x0060 - DramWidth
0=x8, 1=x16, others=RESERVED.
**/
uint8_t DramWidth;
/** Offset 0x0061 - DramSpeed
0=DDRFREQ_800, 1=DDRFREQ_1066, others=RESERVED. Only 533MHz SKU support 1066 memory.
**/
uint8_t DramSpeed;
/** Offset 0x0062 - DramType
0=DDR3, 1=DDR3L, others=RESERVED.
**/
uint8_t DramType;
/** Offset 0x0063 - RankMask
bit[0] RANK0_EN, bit[1] RANK1_EN, others=RESERVED.
**/
uint8_t RankMask;
/** Offset 0x0064 - ChanMask
bit[0] CHAN0_EN, others=RESERVED.
**/
uint8_t ChanMask;
/** Offset 0x0065 - ChanWidth
1=x16, others=RESERVED.
**/
uint8_t ChanWidth;
/** Offset 0x0066 - AddrMode
0, 1, 2 (mode 2 forced if ecc enabled), others=RESERVED.
**/
uint8_t AddrMode;
/** Offset 0x0067 - SrInt
1=1.95us, 2=3.9us, 3=7.8us, others=RESERVED. REFRESH_RATE.
**/
uint8_t SrInt;
/** Offset 0x0068 - SrTemp
0=normal, 1=extended, others=RESERVED.
**/
uint8_t SrTemp;
/** Offset 0x0069 - DramRonVal
0=34ohm, 1=40ohm, others=RESERVED. RON_VALUE Select MRS1.DIC driver impedance control.
**/
uint8_t DramRonVal;
/** Offset 0x006A - DramRttNomVal
0=40ohm, 1=60ohm, 2=120ohm, others=RESERVED.
**/
uint8_t DramRttNomVal;
/** Offset 0x006B - DramRttWrVal
0=off others=RESERVED.
**/
uint8_t DramRttWrVal;
/** Offset 0x006C - SocRdOdtVal
0=off, 1=60ohm, 2=120ohm, 3=180ohm, others=RESERVED.
**/
uint8_t SocRdOdtVal;
/** Offset 0x006D - SocWrRonVal
0=27ohm, 1=32ohm, 2=40ohm, others=RESERVED.
**/
uint8_t SocWrRonVal;
/** Offset 0x006E - SocWrSlewRate
0=2.5V/ns, 1=4V/ns, others=RESERVED.
**/
uint8_t SocWrSlewRate;
/** Offset 0x006F - DramDensity
0=512Mb, 1=1Gb, 2=2Gb, 3=4Gb, others=RESERVED.
**/
uint8_t DramDensity;
/** Offset 0x0070 - tCL
DRAM CAS Latency in clocks
**/
uint8_t tCL;
/** Offset 0x0071 - EccScrubInterval
ECC scrub interval in miliseconds 1..255 (0 works as feature disable
**/
uint8_t EccScrubInterval;
/** Offset 0x0072 - EccScrubBlkSize
Number of 32B blocks read for ECC scrub 2..16
**/
uint8_t EccScrubBlkSize;
/** Offset 0x0073 - SmmTsegSize
Size of the SMM region in 1 MiB chunks
**/
uint8_t SmmTsegSize;
/** Offset 0x0074 - FspReservedMemoryLength
FSP reserved memory length in bytes
**/
uint32_t FspReservedMemoryLength;
/** Offset 0x0078 - MrcDataPtr
Pointer to saved MRC data
**/
uint32_t MrcDataPtr;
/** Offset 0x007C - MrcDataLength
Length of saved MRC data
**/
uint32_t MrcDataLength;
/** Offset 0x0080
**/
uint16_t UpdTerminator;
} __attribute__((packed));
/** Fsp M UPD Configuration
**/
struct FSPM_UPD {
/** Offset 0x0000
**/
struct FSP_UPD_HEADER FspUpdHeader;
/** Offset 0x0020
**/
struct FSPM_ARCH_UPD FspmArchUpd;
/** Offset 0x0040
**/
struct FSP_M_CONFIG FspmConfig;
} __attribute__((packed));
#endif

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src/soc/intel/quark/include/soc/fsp/FspsUpd.h Normal file
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/** @file
Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
* Neither the name of Intel Corporation nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
THE POSSIBILITY OF SUCH DAMAGE.
This file is automatically generated. Please do NOT modify !!!
**/
#ifndef __FSPSUPD_H__
#define __FSPSUPD_H__
#include <FspUpd.h>
/** Fsp S UPD Configuration
**/
struct FSPS_UPD {
/** Offset 0x0000
**/
struct FSP_UPD_HEADER FspUpdHeader;
/** Offset 0x0020
**/
uint16_t UpdTerminator;
} __attribute__((packed));
#endif

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src/soc/intel/quark/include/soc/fsp/FsptUpd.h Normal file
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/** @file
Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
* Neither the name of Intel Corporation nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
THE POSSIBILITY OF SUCH DAMAGE.
This file is automatically generated. Please do NOT modify !!!
**/
#ifndef __FSPTUPD_H__
#define __FSPTUPD_H__
#include <FspUpd.h>
/** Fsp T Common UPD
**/
struct FSPT_COMMON_UPD {
/** Offset 0x0020
**/
uint8_t Revision;
/** Offset 0x0021
**/
uint8_t Reserved[3];
/** Offset 0x0024
**/
uint32_t MicrocodeRegionBase;
/** Offset 0x0028
**/
uint32_t MicrocodeRegionLength;
/** Offset 0x002C
**/
uint32_t CodeRegionBase;
/** Offset 0x0030
**/
uint32_t CodeRegionLength;
/** Offset 0x0034
**/
uint8_t Reserved1[12];
} __attribute__((packed));
/** Fsp T UPD Configuration
**/
struct FSPT_UPD {
/** Offset 0x0000
**/
struct FSP_UPD_HEADER FspUpdHeader;
/** Offset 0x0020
**/
struct FSPT_COMMON_UPD FsptCommonUpd;
/** Offset 0x0040
**/
uint16_t UpdTerminator;
} __attribute__((packed));
#endif