mb/google/sarien: Increse BIOS region size to 28MB
Increase BIOS region(SI_BIOS) from 16MB to 28MB to make more spaces for upcoming payloads. BUG=b:121169122 TEST=Build and boot up fine into OS on sarien and arcada platform. Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Change-Id: I4b03e20a485cb819b468c00e68f1539e92731237 Reviewed-on: https://review.coreboot.org/c/31054 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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@ -1,27 +1,27 @@
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FLASH@0xfe000000 0x2000000 {
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SI_ALL@0x0 0x1000000 {
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SI_ALL@0x0 0x400000 {
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SI_DESC@0x0 0x1000
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SI_EC@0x1000 0x100000
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SI_GBE@0x101000 0x2000
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SI_ME@0x103000 0xef9000
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SI_PDR@0xffc000 0x4000
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SI_ME@0x103000 0x2f9000
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SI_PDR@0x3fc000 0x4000
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}
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SI_BIOS@0x1000000 0x1000000 {
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RW_DIAG@0x0 0x6d0000 {
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SI_BIOS@0x400000 0x1c00000 {
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RW_DIAG@0x0 0x12d0000 {
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DIAG_NVRAM@0x0 0x10000
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RW_LEGACY(CBFS)@0x10000 0x6c0000
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RW_LEGACY(CBFS)@0x10000 0x12c0000
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}
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RW_SECTION_A@0x6d0000 0x280000 {
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RW_SECTION_A@0x12d0000 0x280000 {
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VBLOCK_A@0x0 0x10000
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FW_MAIN_A(CBFS)@0x10000 0x26ffc0
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RW_FWID_A@0x27ffc0 0x40
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}
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RW_SECTION_B@0x950000 0x280000 {
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RW_SECTION_B@0x1550000 0x280000 {
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VBLOCK_B@0x0 0x10000
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FW_MAIN_B(CBFS)@0x10000 0x26ffc0
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RW_FWID_B@0x27ffc0 0x40
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}
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RW_MISC@0xbd0000 0x30000 {
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RW_MISC@0x17d0000 0x30000 {
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UNIFIED_MRC_CACHE@0x0 0x20000 {
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RECOVERY_MRC_CACHE@0x0 0x10000
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RW_MRC_CACHE@0x10000 0x10000
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@ -34,7 +34,7 @@ FLASH@0xfe000000 0x2000000 {
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RW_VPD@0x28000 0x2000
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RW_NVRAM@0x2a000 0x6000
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}
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WP_RO@0xc00000 0x400000 {
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WP_RO@0x1800000 0x400000 {
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RO_VPD@0x0 0x4000
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RO_UNUSED@0x4000 0xc000
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RO_SECTION@0x10000 0x3f0000 {
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