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soc/amd/common: move FCH IOAPIC and HPET init from SMBUs to LPC device 

Despite the SMBus device being function 0 of the FCH PCI device, the
MMIO resource of the FCH IOAPIC is on the LPC device which is function 3
of the same PCI device, so move the FCH IOAPIC initialization code to
the LPC device. Since the HPET was enabled in the same function, also
move it to the LPC device initialization.

TEST=On Mandolin both IOAPICs are still correctly detected by Linux.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I585afd463c1c00cd87ced0617e7802503c5deba5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58334
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Felix Held 2021-10-21 03:13:42 +02:00 committed by Felix Held
parent a6425f170c
commit 390a28057c
2 changed files with 11 additions and 10 deletions
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11
src/soc/amd/common/block/lpc/lpc.c
View File

@ -1,5 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <arch/ioapic.h>
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
@ -15,6 +16,7 @@
#include <amdblocks/acpi.h>
#include <amdblocks/acpimmio.h>
#include <amdblocks/espi.h>
#include <amdblocks/ioapic.h>
#include <amdblocks/lpc.h>
#include <soc/iomap.h>
#include <soc/lpc.h>
@ -34,6 +36,12 @@ static void setup_serirq(void)
pm_write8(PM_SERIRQ_CONF, byte);
}
static void fch_ioapic_init(void)
{
fch_enable_ioapic_decode();
setup_ioapic(VIO_APIC_VADDR, FCH_IOAPIC_ID);
}
static void lpc_init(struct device *dev)
{
u8 byte;
@ -83,6 +91,9 @@ static void lpc_init(struct device *dev)
setup_i8254();
setup_serirq();
fch_ioapic_init();
fch_configure_hpet();
}
static void lpc_read_resources(struct device *dev)

10
src/soc/amd/common/block/smbus/sm.c
View File

@ -1,20 +1,11 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <amdblocks/acpimmio.h>
#include <amdblocks/ioapic.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/smbus.h>
#include <device/smbus_host.h>
#include <arch/ioapic.h>
static void sm_init(struct device *dev)
{
fch_enable_ioapic_decode();
setup_ioapic(VIO_APIC_VADDR, FCH_IOAPIC_ID);
fch_configure_hpet();
}
static u32 get_sm_mmio(struct device *dev)
{
@ -77,7 +68,6 @@ static struct device_operations smbus_ops = {
.read_resources = noop_read_resources,
.set_resources = noop_set_resources,
.enable_resources = pci_dev_enable_resources,
.init = sm_init,
.scan_bus = scan_smbus,
.ops_pci = &pci_dev_ops_pci,
.ops_smbus_bus = &lops_smbus_bus,