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mb/google/brya/var/nereid: Enable AUX DC biasing on C0 and C1 

C0 has no redriver, so enable SBU muxing in the SoC.

C1 has a redriver which does SBU muxing, so disable SBU muxing in the
SoC. However, this also disables AUX biasing when the pins are
configured as NF6. So instead configure the C1 AUX bias pins as GPO.

BUG=b:227259673
TEST=Voltages are correct on the C0 and C1 AUX bias pins

Change-Id: Ic0af662ecc1c6cee15b4ae98cb02deeefc93a71e
Signed-off-by: Reka Norman <rekanorman@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63199
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sam McNally <sammc@google.com>
This commit is contained in:
Reka Norman 2022-03-30 12:44:24 +11:00 committed by Paul Fagerburg
parent 56ed0bee86
commit 390c3f2b47
2 changed files with 9 additions and 1 deletions
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4
src/mainboard/google/brya/variants/nereid/gpio.c
View File

@ -9,6 +9,10 @@
static const struct pad_config override_gpio_table[] = {
/* A8 : WWAN_RF_DISABLE_ODL */
PAD_NC(GPP_A8, NONE),
/* A21 : GPP_A21 ==> USB_C1_AUX_DC_P */
PAD_CFG_GPO(GPP_A21, 0, DEEP),
/* A22 : GPP_A22 ==> USB_C1_AUX_DC_N */
PAD_CFG_GPO(GPP_A22, 1, DEEP),
/* B5 : SOC_I2C_SUB_SDA */
PAD_NC(GPP_B5, NONE),

6
src/mainboard/google/brya/variants/nereid/overridetree.cb
View File

@ -9,8 +9,12 @@ end
chip soc/intel/alderlake
register "sagv" = "SaGv_Enabled"
# Bit 0 - C0 has no redriver, so enable SBU muxing in the SoC.
# Bit 2 - C1 has a redriver which does SBU muxing.
# Bit 1,3 - AUX lines are not swapped on the motherboard for either C0 or C1.
register "tcss_aux_ori" = "1"
register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}"
register "typec_aux_bias_pads[1]" = "{.pad_auxp_dc = GPP_A21, .pad_auxn_dc = GPP_A22}"
register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # WFC
register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth port for PCIe WLAN