mb/google/dedede: Skip the CPU replacement check for dedede
This patches enables the SkipCpuReplacementCheck config for the dedede baseboard to avoid the forced MRC training for all its variants with the soldered down SOC. BUG=b:160201335 TEST=Build and verify CSE Lite SKU on Waddledoo. Cq-Depend: chrome-internal:3142530 Change-Id: I611e66f74a3b9b090ab5e0d836231643d3f919dc Signed-off-by: V Sowmya <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42930 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
This commit is contained in:
parent
e8156ad981
commit
3915627615
|
@ -163,6 +163,9 @@ chip soc/intel/jasperlake
|
||||||
# register "common_soc_config.<variable_name>" = "value"
|
# register "common_soc_config.<variable_name>" = "value"
|
||||||
register "common_soc_config.chipset_lockdown" = CHIPSET_LOCKDOWN_COREBOOT
|
register "common_soc_config.chipset_lockdown" = CHIPSET_LOCKDOWN_COREBOOT
|
||||||
|
|
||||||
|
# Skip the CPU repalcement check
|
||||||
|
register "SkipCpuReplacementCheck" = "1"
|
||||||
|
|
||||||
device domain 0 on
|
device domain 0 on
|
||||||
device pci 00.0 on end # Host Bridge
|
device pci 00.0 on end # Host Bridge
|
||||||
device pci 02.0 on end # Integrated Graphics Device
|
device pci 02.0 on end # Integrated Graphics Device
|
||||||
|
|
Loading…
Reference in New Issue