S3 code in vendorcode folder.
Change the ExecuteFinalHltInstruction to assembly code. so we can make sure the code can run stackless. Change-Id: I783ced6cf7c5bc29c12a37aef29077e610d8957d Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: zbao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/622 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
zbao
Stefan Reinauer
parent
9bcdbf8eaa
commit
3925622638
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@ -113,6 +113,7 @@ agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Gfx/GfxInitAtMidPost.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/cpuF14CacheDefaults.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Ps/ON/mpuon3.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cahalt.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cahaltasm.S
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agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/mt.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/ON/F14OnMicrocodePatchTables.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/ON/F14OnPciTables.c
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@ -305,7 +305,9 @@ static __inline__ __attribute__((always_inline)) unsigned long __readcr0(void)
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unsigned long value;
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__asm__ __volatile__ (
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"mov %%cr0, %[value]"
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: [value] "=a" (value));
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: [value] "=a" (value)
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:
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: "memory");
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return value;
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}
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@ -379,6 +381,7 @@ static __inline__ __attribute__((always_inline)) void __writecr0(unsigned long D
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"mov %%eax, %%cr0"
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:
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: "a" (Data)
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: "memory"
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);
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}
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@ -508,13 +511,16 @@ static __inline__ __attribute__((always_inline)) void __debugbreak(void)
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__asm__ __volatile__ ("int3");
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}
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static __inline__ __attribute__((always_inline)) void __invd(void)
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{
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__asm__ __volatile__ ("invd");
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}
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static __inline__ __attribute__((always_inline)) void __wbinvd(void)
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{
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__asm__ __volatile__ ("wbinvd");
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}
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static __inline__ __attribute__((always_inline)) void __lidt(void *Source)
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{
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__asm__ __volatile__("lidt %0" : : "m"(*(short*)Source));
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@ -106,149 +106,16 @@ ExecuteWbinvdInstruction (
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*/
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//----------------------------------------------------------------------------
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STATIC
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VOID
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PrimaryCoreFunctions (AP_MTRR_SETTINGS *ApMtrrSettingsList)
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{
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UINT64 data;
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UINT32 msrno;
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// Configure the MTRRs on the AP so
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// when it runs remote code it will execute
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// out of RAM instead of ROM.
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// Disable MTRRs and turn on modification enable bit
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data = __readmsr (0xC0010010); // MTRR_SYS_CFG
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data &= ~(1 << 18); // MtrrFixDramEn
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data &= ~(1 << 20); // MtrrVarDramEn
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data |= (1 << 19); // MtrrFixDramModEn
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data |= (1 << 17); // SysUcLockEn
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__writemsr (0xC0010010, data);
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// Set 7FFFh-00000h and 9FFFFh-80000h as WB DRAM
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__writemsr (0x250, 0x1E1E1E1E1E1E1E1E); // AMD_MTRR_FIX64k_00000
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__writemsr (0x258, 0x1E1E1E1E1E1E1E1E); // AMD_MTRR_FIX16k_80000
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// Set BFFFFh-A0000h, DFFFFh-C0000h as Uncacheable Memory-mapped IO
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__writemsr (0x259, 0); // AMD_AP_MTRR_FIX16k_A0000
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__writemsr (0x268, 0); // AMD_MTRR_FIX4k_C0000
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__writemsr (0x269, 0); // AMD_MTRR_FIX4k_C8000
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__writemsr (0x26A, 0); // AMD_MTRR_FIX4k_D0000
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__writemsr (0x26B, 0); // AMD_MTRR_FIX4k_D8000
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// Set FFFFFh-E0000h as Uncacheable Memory
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for (msrno = 0x26C; msrno <= 0x26F; msrno++)
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__writemsr (msrno, 0x1818181818181818);
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// If IBV provided settings for Fixed-Sized MTRRs,
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// overwrite the default settings.
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if ((uintptr_t) ApMtrrSettingsList != 0 && (uintptr_t) ApMtrrSettingsList != 0xFFFFFFFF)
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{
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int index;
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for (index = 0; ApMtrrSettingsList [index].MsrAddr != CPU_LIST_TERMINAL; index++)
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__writemsr (ApMtrrSettingsList [index].MsrAddr, ApMtrrSettingsList [index].MsrData);
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}
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// restore variable MTTR6 and MTTR7 to default states
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for (msrno = 0x20F; msrno <= 0x20C; msrno--) // decrement so that the pair is disable before the base is cleared
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__writemsr (msrno, 0);
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// Enable fixed-range and variable-range MTRRs
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// Set Fixed-Range Enable (FE) and MTRR Enable (E) bits
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__writemsr (0x2FF, __readmsr (0x2FF) | 0xC00);
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// Enable Top-of-Memory setting
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// Enable use of RdMem/WrMem bits attributes
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data = __readmsr (0xC0010010); // MTRR_SYS_CFG
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data |= (1 << 18); // MtrrFixDramEn
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data |= (1 << 20); // MtrrVarDramEn
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data &= ~(1 << 19); // MtrrFixDramModEn
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__writemsr (0xC0010010, data);
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}
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//----------------------------------------------------------------------------
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/* see cahaltasm.S
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VOID
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ExecuteFinalHltInstruction (
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IN UINT32 SharedCore,
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IN UINT32 HaltFlags,
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IN AP_MTRR_SETTINGS *ApMtrrSettingsList,
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IN AMD_CONFIG_PARAMS *StdHeader
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)
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{
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int abcdRegs [4];
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UINT32 cr0val;
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UINT64 data;
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cr0val = __readcr0 ();
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if (SharedCore & 2)
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{
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// set CombineCr0Cd and enable cache in CR0
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__writemsr (MSR_CU_CFG3, __readmsr (MSR_CU_CFG3) | 1ULL << 49);
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__writecr0 (cr0val & ~0x60000000);
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}
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else
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__writecr0 (cr0val | 0x60000000);
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if (SharedCore & 1) PrimaryCoreFunctions (ApMtrrSettingsList);
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// Make sure not to touch any Shared MSR from this point on
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// Restore settings that were temporarily overridden for the cache as ram phase
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data = __readmsr (0xC0011022); // MSR_DC_CFG
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data &= ~(1 << 4); // DC_DIS_SPEC_TLB_RLD
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data &= ~(1 << 8); // DIS_CLR_WBTOL2_SMC_HIT
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data &= ~(1 << 13); // DIS_HW_PF
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__writemsr (0xC0011022, data);
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data = __readmsr (0xC0011021); // MSR_IC_CFG - C001_1021
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data &= ~(1 << 9); // IC_DIS_SPEC_TLB_RLD
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__writemsr (0xC0011021, data);
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// AMD_DISABLE_STACK_FAMILY_HOOK
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__cpuid (abcdRegs, 1);
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if ((abcdRegs [0] >> 20) == 1) //-----family 10h (Hydra) only-----
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{
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data = __readmsr (0xC0011022);
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data &= ~(1 << 4);
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data &= ~(1 << 8);
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data &= ~(1 << 13);
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__writemsr (0xC0011022, data);
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data = __readmsr (0xC0011021);
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data &= ~(1 << 14);
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data &= ~(1 << 9);
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__writemsr (0xC0011021, data);
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data = __readmsr (0xC001102A);
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data &= ~(1 << 15);
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data &= ~(1ull << 35);
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__writemsr (0xC001102A, data);
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}
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else if ((abcdRegs [0] >> 20) == 6) //-----family 15h (Orochi) only-----
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{
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data = __readmsr (0xC0011020);
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data &= ~(1 << 28);
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__writemsr (0xC0011020, data);
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data = __readmsr (0xC0011021);
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data &= ~(1 << 9);
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__writemsr (0xC0011021, data);
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data = __readmsr (0xC0011022);
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data &= ~(1 << 4);
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data &= ~(1l << 13);
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__writemsr (0xC0011022, data);
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}
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for (;;)
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{
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_disable ();
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__halt ();
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}
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}
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}
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*/
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//----------------------------------------------------------------------------
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@ -0,0 +1,203 @@
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/*
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* Copyright (c) 2011, Advanced Micro Devices, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of Advanced Micro Devices, Inc. nor the names of
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* its contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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*/
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.include "src/vendorcode/amd/agesa/f14/gcccar.inc"
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.code32
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.align 4
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.globl ExecuteFinalHltInstruction
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.type ExecuteFinalHltInstruction, @function
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/* ExecuteFinalHltInstruction (
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IN UINT32 HaltFlags,
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IN AP_MTRR_SETTINGS *ApMtrrSettingsList,
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IN AMD_CONFIG_PARAMS *StdHeader
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)
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*/
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/* This function disables CAR. We don't care about the stack on this CPU */
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ExecuteFinalHltInstruction:
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movl 4(%esp), %esi /* HaltFlags*/
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movl 8(%esp), %edi /* ApMtrrSettingList */
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/* Do these special steps in case if the core is part of a compute unit
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* Note: The following bits are family specific flags, that gets set during build time,
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* and indicates things like "family cache control methodology", etc.
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* esi bit0 = 0 -> not a Primary core
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* esi bit0 = 1 -> Primary core
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* esi bit1 = 0 -> Cache disable
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* esi bit1 = 1 -> Cache enable
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*/
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bt $1, %esi /* .if (esi & 2h) */
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jz 0f
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/* Set CombineCr0Cd bit */
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movl $CU_CFG3, %ecx
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rdmsr
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bts $(COMBINE_CR0_CD - 32), %edx
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wrmsr
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/* Clear the CR0.CD bit */
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movl %cr0, %eax /* Make sure cache is enabled for all APs */
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btr $CR0_CD, %eax
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btr $CR0_NW, %eax
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mov %eax, %cr0 /* Write back to CR0 */
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jmp 1f /* .else */
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0:
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movl %cr0, %eax /* Make sure cache is disabled for all APs */
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bts $CR0_CD, %eax /* Disable cache */
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bts $CR0_NW, %eax
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movl %eax, %cr0 /* Write back to CR0 */
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1: /* .endif */
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bt $0, %esi /* .if (esi & 1h) */
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jz 2f
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/* This core is a primary core and needs to do all the MTRRs, including shared MTRRs. */
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movl %edi, %esi /* Get ApMtrrSettingList */
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/* Configure the MTRRs on the AP so
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* when it runs remote code it will execute
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* out of RAM instead of ROM.
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*/
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/* Disable MTRRs and turn on modification enable bit */
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movl $MTRR_SYS_CFG, %ecx
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rdmsr
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btr $MTRR_VAR_DRAM_EN, %eax /* Disable */
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bts $MTRR_FIX_DRAM_MOD_EN, %eax /* Enable */
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btr $MTRR_FIX_DRAM_EN, %eax /* Disable */
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bts $SYS_UC_LOCK_EN, %eax
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wrmsr
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/* Setup default values for Fixed-Sized MTRRs */
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/* Set 7FFFh-00000h as WB */
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movl $AMD_AP_MTRR_FIX64k_00000, %ecx
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movl $0x1E1E1E1E, %eax
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movl %eax, %edx
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wrmsr
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/* Set 9FFFFh-80000h also as WB */
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movl $AMD_AP_MTRR_FIX16k_80000, %ecx
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wrmsr
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/* Set BFFFFh-A0000h as Uncacheable Memory-mapped IO */
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movl $AMD_AP_MTRR_FIX16k_A0000, %ecx
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xorl %eax, %eax
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xorl %edx, %edx
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wrmsr
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/* Set DFFFFh-C0000h as Uncacheable Memory-mapped IO */
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xorl %eax, %eax
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xorl %edx, %edx
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movl $AMD_AP_MTRR_FIX4k_C0000, %ecx
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CDLoop:
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wrmsr
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inc %ecx
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cmp $AMD_AP_MTRR_FIX4k_D8000, %ecx
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jbe CDLoop
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/* Set FFFFFh-E0000h as Uncacheable Memory */
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movl $0x18181818, %eax
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movl %eax, %edx
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mov $AMD_AP_MTRR_FIX4k_E0000, %ecx
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EFLoop:
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wrmsr
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inc %ecx
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cmp $AMD_AP_MTRR_FIX4k_F8000, %ecx
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jbe EFLoop
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/* If IBV provided settings for Fixed-Sized MTRRs,
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* overwrite the default settings. */
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cmp $0, %esi /*.if ((esi != 0) && (esi != 0FFFFFFFFh)) */
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jz 4f
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cmp $0xFFFFFFFF, %esi
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jz 4f
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5:
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mov (%esi), %ecx /* (AP_MTRR_SETTINGS ptr [esi]).MsrAddr */
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/* While we are not at the end of the list */
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cmp $CPU_LIST_TERMINAL, %ecx /* .while (ecx != CPU_LIST_TERMINAL)*/
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je 4f
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/* TODO - coreboot isn't checking for valid data.
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* Ensure that the MSR address is valid for Fixed-Sized MTRRs */
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/*.if ( ((ecx >= AMD_AP_MTRR_FIX4k_C0000) && (ecx <= AMD_AP_MTRR_FIX4k_F8000)) || \
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(ecx == AMD_AP_MTRR_FIX64k_00000) || (ecx == AMD_AP_MTRR_FIX16k_80000 ) || \
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(ecx == AMD_AP_MTRR_FIX16k_A0000))
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*/
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mov 4(%esi), %eax /* MsrData */
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mov 8(%esi), %edx /* MsrData */
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wrmsr
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/* .endif */
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add $12, %esi /* sizeof (AP_MTRR_SETTINGS) */
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jmp 5b /* .endw */
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4: /* .endif */
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/* restore variable MTTR6 and MTTR7 to default states */
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movl $AMD_MTRR_VARIABLE_BASE6, %ecx /* clear MTRRPhysBase6 MTRRPhysMask6 */
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xor %eax, %eax /* and MTRRPhysBase7 MTRRPhysMask7 */
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xor %edx, %edx
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cmp $10, %ecx /* .while (cl < 010h) */
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jge 6f
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wrmsr
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inc %ecx
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6: /* .endw */
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/* Enable fixed-range and variable-range MTRRs */
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mov $AMD_MTRR_DEFTYPE, %ecx
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rdmsr
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bts $MTRR_DEF_TYPE_EN, %eax /* MtrrDefTypeEn */
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bts $MTRR_DEF_TYPE_FIX_EN, %eax /* MtrrDefTypeFixEn */
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wrmsr
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/* Enable Top-of-Memory setting */
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/* Enable use of RdMem/WrMem bits attributes */
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mov $MTRR_SYS_CFG, %ecx
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rdmsr
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bts $MTRR_VAR_DRAM_EN, %eax /* Enable */
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btr $MTRR_FIX_DRAM_MOD_EN, %eax /* Disable */
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bts $MTRR_FIX_DRAM_EN, %eax /* Enable */
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wrmsr
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bts $FLAG_IS_PRIMARY, %esi
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jmp 3f /* .else ; end if primary core */
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2:
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xor %esi, %esi
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3: /* .endif*/
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/* Make sure not to touch any Shared MSR from this point on */
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AMD_DISABLE_STACK_FAMILY_HOOK
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xor %eax, %eax
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7:
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cli
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hlt
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jmp 7b /* ExecuteHltInstruction */
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.size ExecuteFinalHltInstruction, .-ExecuteFinalHltInstruction
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@ -245,7 +245,7 @@ AmdS3Save (
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HeapStatus = AmdS3SaveParams->StdHeader.HeapStatus;
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AmdS3SaveParams->StdHeader.HeapStatus = HEAP_S3_RESUME;
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AmdS3SaveParams->StdHeader.HeapBasePtr = (UINT64) HeapPtr;
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AmdS3SaveParams->StdHeader.HeapBasePtr = (VOID *) HeapPtr;
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for (i = 0; i < S3LATE_TABLE_SIZE; i++) {
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if (HeapPtrs[i] != NULL) {
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|
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@ -259,30 +259,30 @@ MemFS3GetDeviceList (
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|||
(*DeviceBlockHdrPtr)->RelativeOrMaskOffset = (UINT16) AllocHeapParams.RequestedBufferSize;
|
||||
|
||||
// Copy device list on the stack to the heap.
|
||||
BufferOffset = sizeof (DEVICE_BLOCK_HEADER) + (UINT64) AllocHeapParams.BufferPtr;
|
||||
BufferOffset = sizeof (DEVICE_BLOCK_HEADER) + (UINT64) (UINT32) AllocHeapParams.BufferPtr;
|
||||
for (Die = 0; Die < DieCount; Die ++) {
|
||||
for (i = PRESELFREF; i <= POSTSELFREF; i ++) {
|
||||
// Copy PCI device descriptor to the heap if it exists.
|
||||
if (DeviceDescript[Die].PCIDevice[i].RegisterListID != 0xFFFFFFFF) {
|
||||
LibAmdMemCopy ((VOID *) BufferOffset, &(DeviceDescript[Die].PCIDevice[i]), sizeof (PCI_DEVICE_DESCRIPTOR), StdHeader);
|
||||
LibAmdMemCopy ((VOID *)(UINT32) BufferOffset, &(DeviceDescript[Die].PCIDevice[i]), sizeof (PCI_DEVICE_DESCRIPTOR), StdHeader);
|
||||
(*DeviceBlockHdrPtr)->NumDevices ++;
|
||||
BufferOffset += sizeof (PCI_DEVICE_DESCRIPTOR);
|
||||
}
|
||||
// Copy conditional PCI device descriptor to the heap if it exists.
|
||||
if (DeviceDescript[Die].CPCIDevice[i].RegisterListID != 0xFFFFFFFF) {
|
||||
LibAmdMemCopy ((VOID *) BufferOffset, &(DeviceDescript[Die].CPCIDevice[i]), sizeof (CONDITIONAL_PCI_DEVICE_DESCRIPTOR), StdHeader);
|
||||
LibAmdMemCopy ((VOID *)(UINT32) BufferOffset, &(DeviceDescript[Die].CPCIDevice[i]), sizeof (CONDITIONAL_PCI_DEVICE_DESCRIPTOR), StdHeader);
|
||||
(*DeviceBlockHdrPtr)->NumDevices ++;
|
||||
BufferOffset += sizeof (CONDITIONAL_PCI_DEVICE_DESCRIPTOR);
|
||||
}
|
||||
// Copy MSR device descriptor to the heap if it exists.
|
||||
if (DeviceDescript[Die].MSRDevice[i].RegisterListID != 0xFFFFFFFF) {
|
||||
LibAmdMemCopy ((VOID *) BufferOffset, &(DeviceDescript[Die].MSRDevice[i]), sizeof (MSR_DEVICE_DESCRIPTOR), StdHeader);
|
||||
LibAmdMemCopy ((VOID *)(UINT32) BufferOffset, &(DeviceDescript[Die].MSRDevice[i]), sizeof (MSR_DEVICE_DESCRIPTOR), StdHeader);
|
||||
(*DeviceBlockHdrPtr)->NumDevices ++;
|
||||
BufferOffset += sizeof (MSR_DEVICE_DESCRIPTOR);
|
||||
}
|
||||
// Copy conditional MSR device descriptor to the heap if it exists.
|
||||
if (DeviceDescript[Die].CMSRDevice[i].RegisterListID != 0xFFFFFFFF) {
|
||||
LibAmdMemCopy ((VOID *) BufferOffset, &(DeviceDescript[Die].PCIDevice[i]), sizeof (CONDITIONAL_MSR_DEVICE_DESCRIPTOR), StdHeader);
|
||||
LibAmdMemCopy ((VOID *)(UINT32) BufferOffset, &(DeviceDescript[Die].PCIDevice[i]), sizeof (CONDITIONAL_MSR_DEVICE_DESCRIPTOR), StdHeader);
|
||||
(*DeviceBlockHdrPtr)->NumDevices ++;
|
||||
BufferOffset += sizeof (CONDITIONAL_MSR_DEVICE_DESCRIPTOR);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -37,99 +37,113 @@
|
|||
|
||||
.altmacro
|
||||
|
||||
BSP_STACK_BASE_ADDR = 0x30000 /* Base address for primary cores stack */
|
||||
BSP_STACK_SIZE = 0x10000 /* 64KB for BSP core */
|
||||
CORE0_STACK_BASE_ADDR = 0x80000 /* Base address for primary cores stack */
|
||||
CORE0_STACK_SIZE = 0x4000 /* 16KB for primary cores */
|
||||
CORE1_STACK_BASE_ADDR = 0x40000 /* Base address for AP cores */
|
||||
CORE1_STACK_SIZE = 0x1000 /* 4KB for each AP cores */
|
||||
|
||||
APIC_BASE_ADDRESS = 0x0000001B
|
||||
APIC_BSC = 8 /* Boot Strap Core */
|
||||
|
||||
AMD_MTRR_VARIABLE_BASE0 = 0x0200
|
||||
AMD_MTRR_VARIABLE_BASE6 = 0x020C
|
||||
AMD_MTRR_FIX64k_00000 = 0x0250
|
||||
AMD_MTRR_FIX16k_80000 = 0x0258
|
||||
AMD_MTRR_FIX16k_A0000 = 0x0259
|
||||
AMD_MTRR_FIX4k_C0000 = 0x0268
|
||||
AMD_MTRR_FIX4k_C8000 = 0x0269
|
||||
AMD_MTRR_FIX4k_D0000 = 0x026A
|
||||
AMD_MTRR_FIX4k_D8000 = 0x026B
|
||||
AMD_MTRR_FIX4k_E0000 = 0x026C
|
||||
AMD_MTRR_FIX4k_E8000 = 0x026D
|
||||
AMD_MTRR_FIX4k_F0000 = 0x026E
|
||||
AMD_MTRR_FIX4k_F8000 = 0x026F
|
||||
|
||||
AMD_MTRR_DEFTYPE = 0x02FF
|
||||
WB_DRAM_TYPE = 0x1E /* MemType - memory type */
|
||||
MTRR_DEF_TYPE_EN = 11 /* MtrrDefTypeEn - variable and fixed MTRRs default enabled */
|
||||
MTRR_DEF_TYPE_FIX_EN = 10 /* MtrrDefTypeEn - fixed MTRRs default enabled */
|
||||
|
||||
HWCR = 0x0C0010015 /* Hardware Configuration */
|
||||
INVD_WBINVD = 0x04 /* INVD to WBINVD conversion */
|
||||
|
||||
IORR_BASE = 0x0C0010016 /* IO Range Regusters Base/Mask, 2 pairs */
|
||||
/* uses 16h - 19h */
|
||||
TOP_MEM = 0x0C001001A /* Top of Memory */
|
||||
TOP_MEM2 = 0x0C001001D /* Top of Memory2 */
|
||||
|
||||
LS_CFG = 0x0C0011020 /* Load-Store Configuration */
|
||||
DIS_SS = 28 /* Family 10h,12h,15h:Disable Streng Store functionality */
|
||||
DIS_STREAM_ST = 28 /* Family 14h:DisStreamSt - Disable Streaming Store functionality */
|
||||
|
||||
IC_CFG = 0x0C0011021 /* Instruction Cache Config Register */
|
||||
IC_DIS_SPEC_TLB_RLD = 9 /* Disable speculative TLB reloads */
|
||||
DIS_IND = 14 /* Family 10-14h:Disable Indirect Branch Predictor */
|
||||
DIS_I_CACHE = 14 /* Family 15h:DisICache - Disable Indirect Branch Predictor */
|
||||
|
||||
DC_CFG = 0x0C0011022 /* Data Cache Configuration */
|
||||
DC_DIS_SPEC_TLB_RLD = 4 /* Disable speculative TLB reloads */
|
||||
DIS_CLR_WBTOL2_SMC_HIT = 8 /* self modifying code check buffer bit */
|
||||
DIS_HW_PF = 13 /* Hardware prefetches bit */
|
||||
|
||||
DE_CFG = 0x0C0011029 /* Decode Configuration */
|
||||
CL_FLUSH_SERIALIZE = 23 /* Family 12h,15h: CL Flush Serialization */
|
||||
|
||||
BU_CFG2 = 0x0C001102A /* Family 10h: Bus Unit Configuration 2 */
|
||||
CU_CFG2 = 0x0C001102A /* Family 15h: Combined Unit Configuration 2 */
|
||||
F10_CL_LINES_TO_NB_DIS = 15 /* ClLinesToNbDis - allows WP code to be cached in L2 */
|
||||
IC_DIS_SPEC_TLB_WR = 35 /* IcDisSpecTlbWr - ITLB speculative writes */
|
||||
|
||||
CU_CFG3 = 0x0C001102B /* Combined Unit Configuration 3 */
|
||||
COMBINE_CR0_CD = 49 /* Combine CR0.CD for both cores of a compute unit */
|
||||
|
||||
|
||||
BSP_STACK_BASE_ADDR = 0x30000 /* Base address for primary cores stack */
|
||||
BSP_STACK_SIZE = 0x10000 /* 64KB for BSP core */
|
||||
CORE0_STACK_BASE_ADDR = 0x80000 /* Base address for primary cores stack */
|
||||
CORE0_STACK_SIZE = 0x4000 /* 16KB for primary cores */
|
||||
CORE1_STACK_BASE_ADDR = 0x40000 /* Base address for AP cores */
|
||||
CORE1_STACK_SIZE = 0x1000 /* 4KB for each AP cores */
|
||||
|
||||
APIC_BASE_ADDRESS = 0x0000001B
|
||||
APIC_BSC = 8 /* Boot Strap Core */
|
||||
|
||||
AMD_MTRR_VARIABLE_BASE0 = 0x0200
|
||||
AMD_MTRR_VARIABLE_BASE6 = 0x020C
|
||||
AMD_MTRR_FIX64k_00000 = 0x0250
|
||||
AMD_MTRR_FIX16k_80000 = 0x0258
|
||||
AMD_MTRR_FIX16k_A0000 = 0x0259
|
||||
AMD_MTRR_FIX4k_C0000 = 0x0268
|
||||
AMD_MTRR_FIX4k_C8000 = 0x0269
|
||||
AMD_MTRR_FIX4k_D0000 = 0x026A
|
||||
AMD_MTRR_FIX4k_D8000 = 0x026B
|
||||
AMD_MTRR_FIX4k_E0000 = 0x026C
|
||||
AMD_MTRR_FIX4k_E8000 = 0x026D
|
||||
AMD_MTRR_FIX4k_F0000 = 0x026E
|
||||
AMD_MTRR_FIX4k_F8000 = 0x026F
|
||||
|
||||
/* Reproduced from AGESA.h */
|
||||
AMD_AP_MTRR_FIX64k_00000 = 0x00000250
|
||||
AMD_AP_MTRR_FIX16k_80000 = 0x00000258
|
||||
AMD_AP_MTRR_FIX16k_A0000 = 0x00000259
|
||||
AMD_AP_MTRR_FIX4k_C0000 = 0x00000268
|
||||
AMD_AP_MTRR_FIX4k_C8000 = 0x00000269
|
||||
AMD_AP_MTRR_FIX4k_D0000 = 0x0000026A
|
||||
AMD_AP_MTRR_FIX4k_D8000 = 0x0000026B
|
||||
AMD_AP_MTRR_FIX4k_E0000 = 0x0000026C
|
||||
AMD_AP_MTRR_FIX4k_E8000 = 0x0000026D
|
||||
AMD_AP_MTRR_FIX4k_F0000 = 0x0000026E
|
||||
AMD_AP_MTRR_FIX4k_F8000 = 0x0000026F
|
||||
CPU_LIST_TERMINAL = 0xFFFFFFFF
|
||||
|
||||
AMD_MTRR_DEFTYPE = 0x02FF
|
||||
WB_DRAM_TYPE = 0x1E /* MemType - memory type */
|
||||
MTRR_DEF_TYPE_EN = 11 /* MtrrDefTypeEn - variable and fixed MTRRs default enabled */
|
||||
MTRR_DEF_TYPE_FIX_EN = 10 /* MtrrDefTypeEn - fixed MTRRs default enabled */
|
||||
|
||||
HWCR = 0x0C0010015 /* Hardware Configuration */
|
||||
INVD_WBINVD = 0x04 /* INVD to WBINVD conversion */
|
||||
|
||||
IORR_BASE = 0x0C0010016 /* IO Range Regusters Base/Mask, 2 pairs */
|
||||
/* uses 16h - 19h */
|
||||
TOP_MEM = 0x0C001001A /* Top of Memory */
|
||||
TOP_MEM2 = 0x0C001001D /* Top of Memory2 */
|
||||
|
||||
LS_CFG = 0x0C0011020 /* Load-Store Configuration */
|
||||
DIS_SS = 28 /* Family 10h,12h,15h:Disable Streng Store functionality */
|
||||
DIS_STREAM_ST = 28 /* Family 14h:DisStreamSt - Disable Streaming Store functionality */
|
||||
|
||||
IC_CFG = 0x0C0011021 /* Instruction Cache Config Register */
|
||||
IC_DIS_SPEC_TLB_RLD = 9 /* Disable speculative TLB reloads */
|
||||
DIS_IND = 14 /* Family 10-14h:Disable Indirect Branch Predictor */
|
||||
DIS_I_CACHE = 14 /* Family 15h:DisICache - Disable Indirect Branch Predictor */
|
||||
|
||||
DC_CFG = 0x0C0011022 /* Data Cache Configuration */
|
||||
DC_DIS_SPEC_TLB_RLD = 4 /* Disable speculative TLB reloads */
|
||||
DIS_CLR_WBTOL2_SMC_HIT = 8 /* self modifying code check buffer bit */
|
||||
DIS_HW_PF = 13 /* Hardware prefetches bit */
|
||||
|
||||
DE_CFG = 0x0C0011029 /* Decode Configuration */
|
||||
CL_FLUSH_SERIALIZE = 23 /* Family 12h,15h: CL Flush Serialization */
|
||||
|
||||
BU_CFG2 = 0x0C001102A /* Family 10h: Bus Unit Configuration 2 */
|
||||
CU_CFG2 = 0x0C001102A /* Family 15h: Combined Unit Configuration 2 */
|
||||
F10_CL_LINES_TO_NB_DIS = 15 /* ClLinesToNbDis - allows WP code to be cached in L2 */
|
||||
IC_DIS_SPEC_TLB_WR = 35 /* IcDisSpecTlbWr - ITLB speculative writes */
|
||||
|
||||
CU_CFG3 = 0x0C001102B /* Combined Unit Configuration 3 */
|
||||
COMBINE_CR0_CD = 49 /* Combine CR0.CD for both cores of a compute unit */
|
||||
|
||||
|
||||
CR0_PE = 1 # Protection Enable
|
||||
CR0_NW = 29 # Not Write-through
|
||||
CR0_CD = 30 # Cache Disable
|
||||
CR0_PG = 31 # Paging Enable
|
||||
|
||||
/* CPUID Functions */
|
||||
|
||||
CPUID_MODEL = 1
|
||||
AMD_CPUID_FMF = 0x80000001 /* Family Model Features information */
|
||||
AMD_CPUID_APIC = 0x80000008 /* Long Mode and APIC info., core count */
|
||||
|
||||
NB_CFG = 0x0C001001F /* Northbridge Configuration Register */
|
||||
INIT_APIC_ID_CPU_ID_LO = 54 /* InitApicIdCpuIdLo - is core# in high or low half of APIC ID? */
|
||||
|
||||
MTRR_SYS_CFG = 0x0C0010010 /* System Configuration Register */
|
||||
CHX_TO_DIRTY_DIS = 16 /* ChxToDirtyDis Change to dirty disable */
|
||||
SYS_UC_LOCK_EN = 17 /* SysUcLockEn System lock command enable */
|
||||
MTRR_FIX_DRAM_EN = 18 /* MtrrFixDramEn MTRR fixed RdDram and WrDram attributes enable */
|
||||
MTRR_FIX_DRAM_MOD_EN = 19 /* MtrrFixDramModEn MTRR fixed RdDram and WrDram modification enable */
|
||||
MTRR_VAR_DRAM_EN = 20 /* MtrrVarDramEn MTRR variable DRAM enable */
|
||||
MTRR_TOM2_EN = 21 /* MtrrTom2En MTRR top of memory 2 enable */
|
||||
|
||||
PERF_CONTROL3 = 0x0C0010003 /* Performance event control three */
|
||||
PERF_CONTROL3_RESERVE_L = 0x00200000 /* Preserve the reserved bits */
|
||||
PERF_CONTROL3_RESERVE_H = 0x0FCF0 /* Preserve the reserved bits */
|
||||
CONFIG_EVENT_L = 0x0F0E2 /* All cores with level detection */
|
||||
CONFIG_EVENT_H = 4 /* Increment count by number of event */
|
||||
/* occured in clock cycle */
|
||||
EVENT_ENABLE = 22 /* Enable the event */
|
||||
PERF_COUNTER3 = 0x0C0010007 /* Performance event counter three */
|
||||
|
||||
/* CPUID Functions */
|
||||
|
||||
CPUID_MODEL = 1
|
||||
AMD_CPUID_FMF = 0x80000001 /* Family Model Features information */
|
||||
AMD_CPUID_APIC = 0x80000008 /* Long Mode and APIC info., core count */
|
||||
|
||||
NB_CFG = 0x0C001001F /* Northbridge Configuration Register */
|
||||
INIT_APIC_ID_CPU_ID_LO = 54 /* InitApicIdCpuIdLo - is core# in high or low half of APIC ID? */
|
||||
|
||||
MTRR_SYS_CFG = 0x0C0010010 /* System Configuration Register */
|
||||
CHX_TO_DIRTY_DIS = 16 /* ChxToDirtyDis Change to dirty disable */
|
||||
SYS_UC_LOCK_EN = 17 /* SysUcLockEn System lock command enable */
|
||||
MTRR_FIX_DRAM_EN = 18 /* MtrrFixDramEn MTRR fixed RdDram and WrDram attributes enable */
|
||||
MTRR_FIX_DRAM_MOD_EN = 19 /* MtrrFixDramModEn MTRR fixed RdDram and WrDram modification enable */
|
||||
MTRR_VAR_DRAM_EN = 20 /* MtrrVarDramEn MTRR variable DRAM enable */
|
||||
MTRR_TOM2_EN = 21 /* MtrrTom2En MTRR top of memory 2 enable */
|
||||
|
||||
PERF_CONTROL3 = 0x0C0010003 /* Performance event control three */
|
||||
PERF_CONTROL3_RESERVE_L = 0x00200000 /* Preserve the reserved bits */
|
||||
PERF_CONTROL3_RESERVE_H = 0x0FCF0 /* Preserve the reserved bits */
|
||||
CONFIG_EVENT_L = 0x0F0E2 /* All cores with level detection */
|
||||
CONFIG_EVENT_H = 4 /* Increment count by number of event */
|
||||
/* occured in clock cycle */
|
||||
EVENT_ENABLE = 22 /* Enable the event */
|
||||
PERF_COUNTER3 = 0x0C0010007 /* Performance event counter three */
|
||||
|
||||
# Local use flags, in upper most byte if ESI
|
||||
FLAG_UNKNOWN_FAMILY = 24 # Signals that the family# of the installed processor is not recognized
|
||||
|
|
|
|||
Loading…
Reference in New Issue