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vc/mediatek/mt8195: Remove unused code and comments 

Remove unused code and comment to align with the latest MTK memory
reference code which is from MTK internal dram driver code without
upstream.
version: Ib59134533ced8de09d23dd9f347c934d315166e2

TEST=boot to kernel

Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.corp-partner.google.com>
Change-Id: I95ab3cf8809ad22a341ceb7fd53a68e13fb0420d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58635
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Ryan Chuang 2021-10-26 20:01:01 +08:00 committed by Patrick Georgi
parent 19b3102910
commit 39277554a4
24 changed files with 5046 additions and 15466 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

289
src/vendorcode/mediatek/mt8195/dramc/ANA_init_config.c
View File

@ -3,19 +3,19 @@
#include "dramc_dv_init.h"
#include "dramc_common.h"
#include "dramc_top.h"
//==========================
//PLL config
//==========================
static void ANA_PLL_shuffle_Config(DRAMC_CTX_T *p,U32 PLL_FREQ,U16 data_rate)
{
U32 XTAL_FREQ = 26;
U8 PREDIV = 1; //0/1/2
U8 POSDIV = 0; //0/1/2
U8 FBKSEL = 0; //over 3800 1 otherwise 0
U8 PREDIV = 1;
U8 POSDIV = 0;
U8 FBKSEL = 0;
U32 PCW;
U8 DIV16_CK_SEL = 0;
#if EMI_LPBK_USE_DDR_800 // For Pe_trus DDR1600, sedalpbk DDR800 thru io
#if EMI_LPBK_USE_DDR_800
if(p->frequency==800)
{
POSDIV = 1;
@ -25,7 +25,7 @@ static void ANA_PLL_shuffle_Config(DRAMC_CTX_T *p,U32 PLL_FREQ,U16 data_rate)
#if (fcFOR_CHIP_ID == fc8195)
if(A_D->DQ_CA_OPEN == 1)
{
DIV16_CK_SEL = 0; // For open loop mode DDR400 = 1600/div4, confirm with WL Lee
DIV16_CK_SEL = 0;
}
else
#endif
@ -39,7 +39,7 @@ static void ANA_PLL_shuffle_Config(DRAMC_CTX_T *p,U32 PLL_FREQ,U16 data_rate)
mcSHOW_DBG_MSG6(("=================================== \n"));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_PHYPLL1), P_Fld(0, PHYPLL1_RG_RPHYPLL_TST_EN) | P_Fld(0, PHYPLL1_RG_RPHYPLL_TSTOP_EN));
// @Darren, Mp settings sync @WL
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_PHYPLL0) , P_Fld(0 , SHU_PHYPLL0_RG_RPHYPLL_RESERVED ) \
| P_Fld(0 , SHU_PHYPLL0_RG_RPHYPLL_ICHP ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CLRPLL0) , P_Fld(0 , SHU_CLRPLL0_RG_RCLRPLL_RESERVED ) \
@ -52,25 +52,25 @@ static void ANA_PLL_shuffle_Config(DRAMC_CTX_T *p,U32 PLL_FREQ,U16 data_rate)
| P_Fld(POSDIV , SHU_CLRPLL2_RG_RCLRPLL_POSDIV ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_PHYPLL1) , P_Fld(PCW , SHU_PHYPLL1_RG_RPHYPLL_SDM_PCW ) \
| P_Fld(1 , SHU_PHYPLL1_RG_RPHYPLL_SDM_PCW_CHG ) \
| P_Fld(0 , SHU_PHYPLL1_RG_RPHYPLL_SDM_FRA_EN )); //for DV could set 1 to solve clock jitter issue.
| P_Fld(0 , SHU_PHYPLL1_RG_RPHYPLL_SDM_FRA_EN ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CLRPLL1) , P_Fld(PCW , SHU_CLRPLL1_RG_RCLRPLL_SDM_PCW ) \
| P_Fld(1 , SHU_CLRPLL1_RG_RCLRPLL_SDM_PCW_CHG ) \
| P_Fld(0 , SHU_CLRPLL1_RG_RCLRPLL_SDM_FRA_EN )); //for DV could set 1 to solve clock jitter issue.
| P_Fld(0 , SHU_CLRPLL1_RG_RCLRPLL_SDM_FRA_EN ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_PLL1) , P_Fld(1 , SHU_PLL1_RG_RPHYPLLGP_CK_SEL ) \
| P_Fld(1 , SHU_PLL1_R_SHU_AUTO_PLL_MUX )); //notice here. TODO. should create another function to manage the SPM related
| P_Fld(1 , SHU_PLL1_R_SHU_AUTO_PLL_MUX ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_PHYPLL3) , P_Fld(0 , SHU_PHYPLL3_RG_RPHYPLL_LVROD_EN ) \
| P_Fld(1 , SHU_PHYPLL3_RG_RPHYPLL_RST_DLY ) \
| P_Fld(FBKSEL , SHU_PHYPLL3_RG_RPHYPLL_FBKSEL ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CLRPLL3) , P_Fld(0 , SHU_CLRPLL3_RG_RCLRPLL_LVROD_EN ) \
| P_Fld(1 , SHU_CLRPLL3_RG_RCLRPLL_RST_DLY ) \
| P_Fld(FBKSEL , SHU_CLRPLL3_RG_RCLRPLL_FBKSEL ));
//if(A_D->DQ_CA_OPEN == 1)
{
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_MISC_CLK_CTRL0), P_Fld( A_D->DQ_CA_OPEN , SHU_MISC_CLK_CTRL0_M_CK_OPENLOOP_MODE_SEL ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_PHYPLL3) , P_Fld( A_D->DQ_CA_OPEN , SHU_PHYPLL3_RG_RPHYPLL_MONCK_EN ) \
| P_Fld( DIV16_CK_SEL , SHU_PHYPLL3_RG_RPHYPLL_DIV_CK_SEL )); //@Darren, DDR250 = 4G/div16, confirm with WL Lee
| P_Fld( DIV16_CK_SEL , SHU_PHYPLL3_RG_RPHYPLL_DIV_CK_SEL ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CLRPLL3) , P_Fld( A_D->DQ_CA_OPEN , SHU_CLRPLL3_RG_RCLRPLL_MONCK_EN ) \
| P_Fld( DIV16_CK_SEL , SHU_CLRPLL3_RG_RCLRPLL_DIV_CK_SEL )); //@Darren, DDR250 = 4G/div16, confirm with WL Lee
| P_Fld( DIV16_CK_SEL , SHU_CLRPLL3_RG_RCLRPLL_DIV_CK_SEL ));
}
// vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_PLL2) , P_Fld(1 , SHU_PLL2_RG_RPHYPLL_ADA_MCK8X_EN_SHU ));
mcSHOW_DBG_MSG6(("<<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL\n"));
@ -79,8 +79,8 @@ static void ANA_PLL_shuffle_Config(DRAMC_CTX_T *p,U32 PLL_FREQ,U16 data_rate)
static void ANA_CLK_DIV_config_setting(DRAMC_CTX_T *p,ANA_DVFS_CORE_T *tr,ANA_top_config_T *a_cfg)
{
U8 TX_ARDQ_SERMODE=0; //DQ_P2S_RATIO
U8 TX_ARCA_SERMODE=0; //CA_P2S_RATIO
U8 TX_ARDQ_SERMODE=0;
U8 TX_ARCA_SERMODE=0;
U8 ARDLL_SERMODE_B=0;
U8 ARDLL_SERMODE_C=0;
BOOL isLP4_DSC = (p->DRAMPinmux == PINMUX_DSC)?1:0;
@ -99,7 +99,7 @@ static void ANA_CLK_DIV_config_setting(DRAMC_CTX_T *p,ANA_DVFS_CORE_T *tr,ANA_to
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ6) , P_Fld( TX_ARDQ_SERMODE , SHU_B0_DQ6_RG_RX_ARDQ_RANK_SEL_SER_MODE_B0));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ6) , P_Fld( TX_ARDQ_SERMODE , SHU_B1_DQ6_RG_RX_ARDQ_RANK_SEL_SER_MODE_B1));
//Justin confirm that DES_MODE -> Deserializer mode, while DQ_P2S_RATIO=16 setting 3 others 2. in fact ANA could support some other mode, Here is an propsal option
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD11), P_Fld( (tr->DQ_P2S_RATIO == 16 ) ? 3 : 2 , SHU_CA_CMD11_RG_RX_ARCA_DES_MODE_CA));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ11) , P_Fld( (tr->DQ_P2S_RATIO == 16 ) ? 3 : 2 , SHU_B0_DQ11_RG_RX_ARDQ_DES_MODE_B0));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ11) , P_Fld( (tr->DQ_P2S_RATIO == 16 ) ? 3 : 2 , SHU_B1_DQ11_RG_RX_ARDQ_DES_MODE_B1));
@ -116,14 +116,14 @@ static void ANA_CLK_DIV_config_setting(DRAMC_CTX_T *p,ANA_DVFS_CORE_T *tr,ANA_to
switch (tr->DQ_AAMCK_DIV)
{
case 0 : { ARDLL_SERMODE_B = (isLP4_DSC)?2:0; break; } //for DSC semi-open B1 has to set 2 and B0 don't care
case 0 : { ARDLL_SERMODE_B = (isLP4_DSC)?2:0; break; }
case 2 : { ARDLL_SERMODE_B = 1; break; }
case 4 : { ARDLL_SERMODE_B = 2; break; }
case 8: { ARDLL_SERMODE_B = 3; break; }
default: mcSHOW_ERR_MSG(("WARN: tr->DQ_AAMCK_DIV= %2d, Because of DQ_SEMI_OPEN, It's don't care.",tr->DQ_AAMCK_DIV));
}
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DLL1), P_Fld(ARDLL_SERMODE_B , SHU_B0_DLL1_RG_ARDLL_SER_MODE_B0));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DLL1), P_Fld(ARDLL_SERMODE_B , SHU_B1_DLL1_RG_ARDLL_SER_MODE_B1));//TODO:check
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DLL1), P_Fld(ARDLL_SERMODE_B , SHU_B1_DLL1_RG_ARDLL_SER_MODE_B1));
switch (tr->CA_ADMCK_DIV)
{
@ -136,13 +136,13 @@ static void ANA_CLK_DIV_config_setting(DRAMC_CTX_T *p,ANA_DVFS_CORE_T *tr,ANA_to
vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_DLL1), P_Fld(ARDLL_SERMODE_C , SHU_CA_DLL1_RG_ARDLL_SER_MODE_CA));
DramcBroadcastOnOff(DRAMC_BROADCAST_ON);
//DQ SEMI-OPEN register control
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ6) , P_Fld( tr->DQ_SEMI_OPEN , SHU_B0_DQ6_RG_ARPI_SOPEN_EN_B0 ) \
| P_Fld( tr->DQ_CA_OPEN , SHU_B0_DQ6_RG_ARPI_OPEN_EN_B0 ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ6) , P_Fld( tr->DQ_SEMI_OPEN , SHU_B1_DQ6_RG_ARPI_SOPEN_EN_B1 ) \
| P_Fld( tr->DQ_CA_OPEN , SHU_B1_DQ6_RG_ARPI_OPEN_EN_B1 ));
//CA SEMI-OPEN register control
if(tr->CA_SEMI_OPEN == 0)
{
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD6) , P_Fld( 0 , SHU_CA_CMD6_RG_ARPI_SOPEN_EN_CA ) \
@ -154,7 +154,7 @@ static void ANA_CLK_DIV_config_setting(DRAMC_CTX_T *p,ANA_DVFS_CORE_T *tr,ANA_to
}
else
{
// @Darren, for DDR800semi
DramcBroadcastOnOff(DRAMC_BROADCAST_OFF);
vIO32WriteFldMulti_All(DDRPHY_REG_SHU_CA_CMD6 , P_Fld( 1 , SHU_CA_CMD6_RG_ARPI_SOPEN_EN_CA ) \
| P_Fld( 1 , SHU_CA_CMD6_RG_ARPI_SOPEN_CKGEN_EN_CA ) \
@ -163,17 +163,17 @@ static void ANA_CLK_DIV_config_setting(DRAMC_CTX_T *p,ANA_DVFS_CORE_T *tr,ANA_to
| P_Fld( 1 , SHU_CA_DLL_ARPI3_RG_ARPI_CLK_EN ));
if(!isLP4_DSC)
{
//CHA CA as master
vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_DLL_ARPI3), 1, SHU_CA_DLL_ARPI3_RG_ARPI_MCTL_EN_CA );
//CHB CA as slave
vSetPHY2ChannelMapping(p, CHANNEL_B);
vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_DLL_ARPI3), 0, SHU_CA_DLL_ARPI3_RG_ARPI_MCTL_EN_CA );
#if (CHANNEL_NUM>2)
if (channel_num_auxadc > 2) {
vSetPHY2ChannelMapping(p, CHANNEL_C);
//CHC CA as master
vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_DLL_ARPI3), 1, SHU_CA_DLL_ARPI3_RG_ARPI_MCTL_EN_CA );
//CHD CA as slave
vSetPHY2ChannelMapping(p, CHANNEL_D);
vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_DLL_ARPI3), 0, SHU_CA_DLL_ARPI3_RG_ARPI_MCTL_EN_CA );
}
@ -181,17 +181,17 @@ static void ANA_CLK_DIV_config_setting(DRAMC_CTX_T *p,ANA_DVFS_CORE_T *tr,ANA_to
}
else
{
//CHA CA as master
vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DLL_ARPI3), 1, SHU_B1_DLL_ARPI3_RG_ARPI_MCTL_EN_B1 );
//CHB CA as slave
vSetPHY2ChannelMapping(p, CHANNEL_B);
vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DLL_ARPI3), 0, SHU_B1_DLL_ARPI3_RG_ARPI_MCTL_EN_B1 );
#if (CHANNEL_NUM>2)
if (channel_num_auxadc > 2) {
vSetPHY2ChannelMapping(p, CHANNEL_C);
//CHC CA as master
vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DLL_ARPI3), 1, SHU_B1_DLL_ARPI3_RG_ARPI_MCTL_EN_B1 );
//CHD CA as slave
vSetPHY2ChannelMapping(p, CHANNEL_D);
vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DLL_ARPI3), 0, SHU_B1_DLL_ARPI3_RG_ARPI_MCTL_EN_B1 );
}
@ -201,21 +201,6 @@ static void ANA_CLK_DIV_config_setting(DRAMC_CTX_T *p,ANA_DVFS_CORE_T *tr,ANA_to
vSetPHY2ChannelMapping(p, CHANNEL_A);
DramcBroadcastOnOff(DRAMC_BROADCAST_ON);
//--------TODO ---20190721 WAITING DPHY KaiHsin & Alucary confirm this RG setting.
// if(a_cfg->DLL_ASYNC_EN == 1)
// {
// //CA as all master
// vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_DLL_ARPI3) , P_Fld(1, SHU_CA_DLL_ARPI3_RG_ARPI_MCTL_EN_CA ));
// } else {
// DramcBroadcastOnOff(DRAMC_BROADCAST_OFF);
// //CHA CA as master
// vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_DLL_ARPI3) , P_Fld(1, SHU_CA_DLL_ARPI3_RG_ARPI_MCTL_EN_CA ));
// //CHB CA as slave
// vSetPHY2ChannelMapping(p, CHANNEL_B);
// vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_DLL_ARPI3) , P_Fld(0, SHU_CA_DLL_ARPI3_RG_ARPI_MCTL_EN_CA ));
// vSetPHY2ChannelMapping(p, CHANNEL_A);
// DramcBroadcastOnOff(DRAMC_BROADCAST_ON);
// }
}
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD6) , P_Fld( tr->DQ_CA_OPEN , SHU_CA_CMD6_RG_ARPI_OPEN_EN_CA ));
@ -236,9 +221,9 @@ static void ANA_CLK_DIV_config_setting(DRAMC_CTX_T *p,ANA_DVFS_CORE_T *tr,ANA_to
mcSHOW_DBG_MSG6(("<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration\n"));
}
//==========================
//DLL config
//==========================
static void ANA_DLL_non_shuffle_config(DRAMC_CTX_T *p,ANA_top_config_T *a_cfg)
{
U8 u1PDZone = (p->frequency >= 2133) ? 0x2 : 0x3;
@ -349,14 +334,14 @@ static void ANA_DLL_shuffle_Config(DRAMC_CTX_T *p, ANA_top_config_T *a_cfg)
BOOL isLP4_DSC = (p->DRAMPinmux == PINMUX_DSC)?1:0;
if(p->frequency<=1600)
{
u1Gain = 1;//checked by WL
u1Gain = 1;
mcSHOW_DBG_MSG6((">>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = %d\n",u1Gain));
}
mcSHOW_DBG_MSG6((">>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL\n"));
//B0
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DLL0) , P_Fld( 7+u1Gain , SHU_B0_DLL0_RG_ARDLL_GAIN_B0 ) \
| P_Fld( 7 , SHU_B0_DLL0_RG_ARDLL_IDLECNT_B0 ) \
| P_Fld( 0 , SHU_B0_DLL0_RG_ARDLL_FAST_PSJP_B0 ) \
@ -372,7 +357,7 @@ static void ANA_DLL_shuffle_Config(DRAMC_CTX_T *p, ANA_top_config_T *a_cfg)
| P_Fld( 0 , SHU_B0_DLL1_RG_ARDLL_PD_CK_SEL_B0 ));
if (isLP4_DSC)
{
//B1
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_DLL0) , P_Fld( 7+u1Gain , SHU_CA_DLL0_RG_ARDLL_GAIN_CA ) \
| P_Fld( 7 , SHU_CA_DLL0_RG_ARDLL_IDLECNT_CA ) \
| P_Fld( 0 , SHU_CA_DLL0_RG_ARDLL_FAST_PSJP_CA ) \
@ -481,7 +466,7 @@ if (isLP4_DSC)
}
else
{
//B1
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DLL0) , P_Fld( 7+u1Gain , SHU_B1_DLL0_RG_ARDLL_GAIN_B1 ) \
| P_Fld( 7 , SHU_B1_DLL0_RG_ARDLL_IDLECNT_B1 ) \
| P_Fld( 0 , SHU_B1_DLL0_RG_ARDLL_FAST_PSJP_B1 ) \
@ -595,7 +580,7 @@ else
static void ANA_ARPI_shuffle_config(DRAMC_CTX_T *p,ANA_top_config_T *a_cfg,ANA_DVFS_CORE_T *tr)
{
BOOL isLP4_DSC = (p->DRAMPinmux == PINMUX_DSC)?1:0;
//B0
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DLL_ARPI3) , P_Fld( !((tr->DQ_SEMI_OPEN)||(tr->DQ_CA_OPEN)), SHU_B0_DLL_ARPI3_RG_ARPI_DQSIEN_EN_B0 ) \
| P_Fld( !((tr->DQ_SEMI_OPEN)||(tr->DQ_CA_OPEN)), SHU_B0_DLL_ARPI3_RG_ARPI_DQ_EN_B0 ) \
| P_Fld( !((tr->DQ_SEMI_OPEN)||(tr->DQ_CA_OPEN)), SHU_B0_DLL_ARPI3_RG_ARPI_DQM_EN_B0 ) \
@ -612,7 +597,7 @@ static void ANA_ARPI_shuffle_config(DRAMC_CTX_T *p,ANA_top_config_T *a_cfg,ANA_D
| P_Fld( 0 , SHU_B0_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B0 ) \
| P_Fld( 0 , SHU_B0_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B0 ));
//B1
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DLL_ARPI3) , P_Fld( !((tr->DQ_SEMI_OPEN)||(tr->DQ_CA_OPEN)), SHU_B1_DLL_ARPI3_RG_ARPI_DQSIEN_EN_B1 ) \
| P_Fld( !((tr->DQ_SEMI_OPEN)||(tr->DQ_CA_OPEN)), SHU_B1_DLL_ARPI3_RG_ARPI_DQ_EN_B1 ) \
| P_Fld( !((tr->DQ_SEMI_OPEN)||(tr->DQ_CA_OPEN)), SHU_B1_DLL_ARPI3_RG_ARPI_DQM_EN_B1 ) \
@ -630,7 +615,7 @@ static void ANA_ARPI_shuffle_config(DRAMC_CTX_T *p,ANA_top_config_T *a_cfg,ANA_D
| P_Fld( 0 , SHU_B1_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B1 ));
//CA
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_DLL_ARPI3) , P_Fld( isLP4_DSC&&(!((tr->DQ_SEMI_OPEN)||(tr->DQ_CA_OPEN))), SHU_CA_DLL_ARPI3_RG_ARPI_CLKIEN_EN ) \
| P_Fld( (!((tr->DQ_SEMI_OPEN)||(tr->DQ_CA_OPEN))), SHU_CA_DLL_ARPI3_RG_ARPI_CMD_EN ) \
| P_Fld( (!((tr->DQ_SEMI_OPEN)||(tr->DQ_CA_OPEN))), SHU_CA_DLL_ARPI3_RG_ARPI_CS_EN ));
@ -644,9 +629,9 @@ static void ANA_ARPI_shuffle_config(DRAMC_CTX_T *p,ANA_top_config_T *a_cfg,ANA_D
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD7) , P_Fld( 0 , SHU_CA_CMD7_R_DMTX_ARPI_CG_CS_NEW ) \
| P_Fld( 0 , SHU_CA_CMD7_R_DMTX_ARPI_CG_CMD_NEW ));
}
//==========================
//ANA_TX_CONFIG
//==========================
static void ANA_TX_nonshuffle_config(DRAMC_CTX_T *p,ANA_top_config_T *a_cfg)
{
BOOL isLP4_DSC = (p->DRAMPinmux == PINMUX_DSC)?1:0;
@ -660,7 +645,7 @@ static void ANA_TX_nonshuffle_config(DRAMC_CTX_T *p,ANA_top_config_T *a_cfg)
| P_Fld(!(a_cfg->LP45_APHY_COMB_EN) , B1_DQ6_RG_TX_ARDQ_DDR4_SEL_B1 ) \
| P_Fld(a_cfg->LP45_APHY_COMB_EN , B1_DQ6_RG_TX_ARDQ_LP4_SEL_B1 ));
mcSHOW_DBG_MSG6(("<<<<<< [CONFIGURE PHASE]: ANA_TX\n"));
//enable TX OE
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ2) , P_Fld(0 , B0_DQ2_RG_TX_ARDQ_OE_DIS_B0 ) \
| P_Fld(0 , B0_DQ2_RG_TX_ARDQ_ODTEN_DIS_B0 ) \
| P_Fld(0 , B0_DQ2_RG_TX_ARDQM0_OE_DIS_B0 ) \
@ -714,13 +699,13 @@ static void ANA_TX_nonshuffle_config(DRAMC_CTX_T *p,ANA_top_config_T *a_cfg)
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_TX_ARCS_CTRL),P_Fld(1, CA_TX_ARCS_CTRL_RG_TX_ARCS_OE_TIE_SEL_C0)) ;
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_TX_ARDQ_CTRL), P_Fld(1, CA_TX_ARDQ_CTRL_RG_TX_ARDQ6_OE_TIE_EN_C0) \
| P_Fld(1, CA_TX_ARDQ_CTRL_RG_TX_ARDQ7_OE_TIE_EN_C0)) ; //Sync MP setting WL C0 DQ6 and DQ7 is no use
| P_Fld(1, CA_TX_ARDQ_CTRL_RG_TX_ARDQ7_OE_TIE_EN_C0)) ;
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_TX_CKE_CTRL), P_Fld(1, B1_TX_CKE_CTRL_RG_TX_ARCKE_OE_TIE_EN_B1) \
| P_Fld(1, B1_TX_CKE_CTRL_RG_TX_ARCS1_OE_TIE_EN_B1)) ; //Sync MP setting WL EMCP: B1 CS1 and CKE is no use
| P_Fld(1, B1_TX_CKE_CTRL_RG_TX_ARCS1_OE_TIE_EN_B1)) ;
}
//enable TX & reset
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD3) , P_Fld(1 , CA_CMD3_RG_TX_ARCMD_EN ) \
| P_Fld(1 , CA_CMD3_RG_ARCMD_RESETB ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ3) , P_Fld(1 , B0_DQ3_RG_ARDQ_RESETB_B0 ) \
@ -733,7 +718,7 @@ static void ANA_TX_shuffle_config(DRAMC_CTX_T *p,ANA_top_config_T *a_cfg,U8 grou
{
BOOL isLP4_DSC = (p->DRAMPinmux == PINMUX_DSC)?1:0;
//ODTEN & DQS control
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD13) , P_Fld(isLP4_DSC , SHU_CA_CMD13_RG_TX_ARCLK_OE_ODTEN_CG_EN_CA ) \
| P_Fld(isLP4_DSC , SHU_CA_CMD13_RG_TX_ARCS_OE_ODTEN_CG_EN_CA )
| P_Fld(0 , SHU_CA_CMD13_RG_TX_ARCLK_READ_BASE_EN_CA )
@ -767,28 +752,28 @@ static void ANA_TX_shuffle_config(DRAMC_CTX_T *p,ANA_top_config_T *a_cfg,U8 grou
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ14) , P_Fld( 0 , SHU_B1_DQ14_RG_TX_ARDQ_MCKIO_SEL_B1 ) \
| P_Fld( 0 , SHU_B1_DQ14_RG_TX_ARWCK_MCKIO_SEL_B1 ));
//B0
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ13), P_Fld(a_cfg->NEW_RANK_MODE, SHU_B0_DQ13_RG_TX_ARDQ_DLY_LAT_EN_B0));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ2), P_Fld(a_cfg->NEW_RANK_MODE, SHU_B0_DQ2_RG_ARPI_OFFSET_LAT_EN_B0) \
| P_Fld(a_cfg->NEW_RANK_MODE, SHU_B0_DQ2_RG_ARPI_OFFSET_ASYNC_EN_B0));
if(!isLP4_DSC)
{
//B1
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ13), P_Fld(a_cfg->NEW_RANK_MODE, SHU_B1_DQ13_RG_TX_ARDQ_DLY_LAT_EN_B1));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ2), P_Fld(a_cfg->NEW_RANK_MODE, SHU_B1_DQ2_RG_ARPI_OFFSET_LAT_EN_B1) \
| P_Fld(a_cfg->NEW_RANK_MODE, SHU_B1_DQ2_RG_ARPI_OFFSET_ASYNC_EN_B1));
//CA
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD13), P_Fld(0, SHU_CA_CMD13_RG_TX_ARCA_DLY_LAT_EN_CA));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD2), P_Fld(0, SHU_CA_CMD2_RG_ARPI_OFFSET_LAT_EN_CA) \
| P_Fld(0, SHU_CA_CMD2_RG_ARPI_OFFSET_ASYNC_EN_CA));
}
else
{
//B1
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ13), P_Fld(0, SHU_B1_DQ13_RG_TX_ARDQ_DLY_LAT_EN_B1));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ2), P_Fld(0, SHU_B1_DQ2_RG_ARPI_OFFSET_LAT_EN_B1) \
| P_Fld(0, SHU_B1_DQ2_RG_ARPI_OFFSET_ASYNC_EN_B1));
//CA
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD13), P_Fld(a_cfg->NEW_RANK_MODE, SHU_CA_CMD13_RG_TX_ARCA_DLY_LAT_EN_CA));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD2), P_Fld(a_cfg->NEW_RANK_MODE, SHU_CA_CMD2_RG_ARPI_OFFSET_LAT_EN_CA) \
| P_Fld(a_cfg->NEW_RANK_MODE, SHU_CA_CMD2_RG_ARPI_OFFSET_ASYNC_EN_CA));
@ -796,7 +781,7 @@ static void ANA_TX_shuffle_config(DRAMC_CTX_T *p,ANA_top_config_T *a_cfg,U8 grou
#if SA_CONFIG_EN
// enable after runtime configs
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ13) , P_Fld( 0, SHU_B0_DQ13_RG_TX_ARDQ_DLY_LAT_EN_B0 ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ2) , P_Fld( 0 , SHU_B0_DQ2_RG_ARPI_OFFSET_LAT_EN_B0 ));
if(!isLP4_DSC)
@ -823,12 +808,12 @@ static void ANA_RX_shuffle_config(DRAMC_CTX_T *p,U8 group_id)
#if (ENABLE_LP4Y_DFS && LP4Y_BACKUP_SOLUTION)
RDQS_SE_EN = DFS(group_id)->data_rate<=1600 ? 1 : 0;
#else
RDQS_SE_EN = 0; //TODO for LPDDR5
RDQS_SE_EN = 0;
#endif
DQSIEN_MODE = DFS(group_id)->DQSIEN_MODE;
NEW_RANK_MODE = A_T->NEW_RANK_MODE;
//B0
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ10) , P_Fld( RDQS_SE_EN , SHU_B0_DQ10_RG_RX_ARDQS_SE_EN_B0 ) \
| P_Fld(DQSIEN_MODE , SHU_B0_DQ10_RG_RX_ARDQS_DQSIEN_MODE_B0 ) \
| P_Fld(1 , SHU_B0_DQ10_RG_RX_ARDQS_DLY_LAT_EN_B0 ) \
@ -838,7 +823,7 @@ static void ANA_RX_shuffle_config(DRAMC_CTX_T *p,U8 group_id)
| P_Fld(NEW_RANK_MODE , SHU_B0_DQ11_RG_RX_ARDQ_RANK_SEL_LAT_EN_B0 ) );
if(isLP4_DSC){
//CA
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD10) , P_Fld( RDQS_SE_EN , SHU_CA_CMD10_RG_RX_ARCLK_SE_EN_CA ) \
| P_Fld(DQSIEN_MODE , SHU_CA_CMD10_RG_RX_ARCLK_DQSIEN_MODE_CA ) \
| P_Fld(1 , SHU_CA_CMD10_RG_RX_ARCLK_DLY_LAT_EN_CA ) \
@ -849,7 +834,7 @@ static void ANA_RX_shuffle_config(DRAMC_CTX_T *p,U8 group_id)
}
else
{
//B1
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ10) , P_Fld( RDQS_SE_EN , SHU_B1_DQ10_RG_RX_ARDQS_SE_EN_B1 ) \
| P_Fld(DQSIEN_MODE , SHU_B1_DQ10_RG_RX_ARDQS_DQSIEN_MODE_B1 ) \
| P_Fld(1 , SHU_B1_DQ10_RG_RX_ARDQS_DLY_LAT_EN_B1 ) \
@ -859,7 +844,7 @@ static void ANA_RX_shuffle_config(DRAMC_CTX_T *p,U8 group_id)
| P_Fld(NEW_RANK_MODE , SHU_B1_DQ11_RG_RX_ARDQ_RANK_SEL_LAT_EN_B1 ));
}
#if SA_CONFIG_EN
// enable after runtime configs
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ10) , P_Fld( 0 , SHU_B0_DQ10_RG_RX_ARDQS_DLY_LAT_EN_B0 ));
if(isLP4_DSC){
@ -885,7 +870,7 @@ static void ANA_RX_nonshuffle_config(DRAMC_CTX_T *p)
{
BOOL isLP4_DSC = (p->DRAMPinmux == PINMUX_DSC)?1:0;
//B0
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ5) , P_Fld( 1 , B0_DQ5_RG_RX_ARDQ_VREF_EN_B0 ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ6) , P_Fld( 0 , B0_DQ6_RG_RX_ARDQ_DDR3_SEL_B0 ) \
@ -898,7 +883,7 @@ static void ANA_RX_nonshuffle_config(DRAMC_CTX_T *p)
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ3) , P_Fld( 1 , B0_DQ3_RG_RX_ARDQ_STBENCMP_EN_B0 ) \
| P_Fld( 1 , B0_DQ3_RG_RX_ARDQ_SMT_EN_B0 ));
//B1
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ5) , P_Fld( (!isLP4_DSC) , B1_DQ5_RG_RX_ARDQ_VREF_EN_B1 ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ6) , P_Fld( 0 , B1_DQ6_RG_RX_ARDQ_DDR3_SEL_B1 ) \
@ -911,7 +896,7 @@ static void ANA_RX_nonshuffle_config(DRAMC_CTX_T *p)
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ3) , P_Fld( (!isLP4_DSC) , B1_DQ3_RG_RX_ARDQ_STBENCMP_EN_B1 ) \
| P_Fld( (!isLP4_DSC) , B1_DQ3_RG_RX_ARDQ_SMT_EN_B1 ));
//CA
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD5), P_Fld(isLP4_DSC, CA_CMD5_RG_RX_ARCMD_VREF_EN));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD6) , P_Fld( 0 , CA_CMD6_RG_RX_ARCMD_DDR3_SEL ) \
@ -924,7 +909,7 @@ static void ANA_RX_nonshuffle_config(DRAMC_CTX_T *p)
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD3), P_Fld(isLP4_DSC, CA_CMD3_RG_RX_ARCMD_STBENCMP_EN) \
| P_Fld(isLP4_DSC, CA_CMD3_RG_RX_ARCMD_SMT_EN));
//RX reset
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD9) , P_Fld( 1 , CA_CMD9_RG_RX_ARCMD_STBEN_RESETB ) \
| P_Fld( 1 , CA_CMD9_RG_RX_ARCLK_STBEN_RESETB ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ9) , P_Fld( 1 , B0_DQ9_RG_RX_ARDQ_STBEN_RESETB_B0 ) \
@ -932,16 +917,16 @@ static void ANA_RX_nonshuffle_config(DRAMC_CTX_T *p)
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ9) , P_Fld( 1 , B1_DQ9_RG_RX_ARDQ_STBEN_RESETB_B1 ) \
| P_Fld( 1 , B1_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B1 ));
//Justin confirm that: All set 1 for improving internal timing option
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD8) , P_Fld( 1 , CA_CMD8_RG_RX_ARCLK_SER_RST_MODE ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ8) , P_Fld( 1 , B0_DQ8_RG_RX_ARDQS_SER_RST_MODE_B0 ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ8) , P_Fld( 1 , B1_DQ8_RG_RX_ARDQS_SER_RST_MODE_B1 ));
}
//============================================
// RESET
//============================================
void RESETB_PULL_DN(DRAMC_CTX_T *p)
{
mcSHOW_DBG_MSG6(("============ PULL DRAM RESETB DOWN ============\n"));
@ -957,9 +942,9 @@ void RESETB_PULL_DN(DRAMC_CTX_T *p)
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD11) , P_Fld( 0 , CA_CMD11_RG_TX_RRESETB_PULL_DN ));
mcSHOW_DBG_MSG6(("========== PULL DRAM RESETB DOWN end =========\n"));
}
//============================================
// SUSPEND_OFF_control
//============================================
static void SUSPEND_ON(DRAMC_CTX_T *p)
{
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_LP_CTRL0) , P_Fld( 0 , B0_LP_CTRL0_RG_ARDMSUS_10_B0 ));
@ -968,9 +953,9 @@ static void SUSPEND_ON(DRAMC_CTX_T *p)
vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DDRPHY_REG_CA_LP_CTRL0) , P_Fld( 0 , CA_LP_CTRL0_RG_ARDMSUS_10_CA ));
DramcBroadcastOnOff(DRAMC_BROADCAST_ON);
}
//============================================
// SPM_control
//============================================
static void SPM_control(DRAMC_CTX_T *p,ANA_top_config_T *a_cfg)
{
BOOL isLP4_DSC = (p->DRAMPinmux == PINMUX_DSC)?1:0;
@ -1069,10 +1054,10 @@ static void SPM_control(DRAMC_CTX_T *p,ANA_top_config_T *a_cfg)
| P_Fld( 1 , CA_LP_CTRL0_RG_ARPI_DDR400_EN_CA_LP_SEL) \
| P_Fld( 1 , CA_LP_CTRL0_RG_CA_DLL_EN_OP_SEQ_LP_SEL) \
| P_Fld( 1 , CA_LP_CTRL0_RG_DA_PICG_CA_CTRL_LOW_BY_LPC) \
| P_Fld( 0 , CA_LP_CTRL0_RG_RX_ARCMD_BIAS_EN_LP_SEL )); //use CA as DQ set 1
| P_Fld( 0 , CA_LP_CTRL0_RG_RX_ARCMD_BIAS_EN_LP_SEL ));
DramcBroadcastOnOff(DRAMC_BROADCAST_ON);
REG_TRANSFER_T MS_SLV_LP_SEL_Reg;//TODO:check
REG_TRANSFER_T MS_SLV_LP_SEL_Reg;
if (isLP4_DSC){
MS_SLV_LP_SEL_Reg.u4Addr = DDRPHY_REG_B1_LP_CTRL0;
MS_SLV_LP_SEL_Reg.u4Fld = B1_LP_CTRL0_RG_B1_MS_SLV_LP_SEL;
@ -1106,7 +1091,7 @@ static void SPM_control(DRAMC_CTX_T *p,ANA_top_config_T *a_cfg)
DramcBroadcastOnOff(DRAMC_BROADCAST_ON);
}
//FOR DDR400 OPEN-LOOP MODE
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CG_CTRL9), P_Fld( 1 , MISC_CG_CTRL9_RG_M_CK_OPENLOOP_MODE_EN ) \
| P_Fld( 1 , MISC_CG_CTRL9_RG_MCK4X_I_OPENLOOP_MODE_EN ) \
| P_Fld( 1 , MISC_CG_CTRL9_RG_CG_DDR400_MCK4X_I_OFF ) \
@ -1116,7 +1101,7 @@ static void SPM_control(DRAMC_CTX_T *p,ANA_top_config_T *a_cfg)
| P_Fld( 1 , MISC_CG_CTRL9_RG_CG_DDR400_MCK4X_Q_OFF ) \
| P_Fld( 0 , MISC_CG_CTRL9_RG_DDR400_MCK4X_Q_FORCE_ON ) \
| P_Fld( 1 , MISC_CG_CTRL9_RG_MCK4X_Q_FB_CK_CG_OFF ));
#if 0 // @Darren-, new APHY remove 45/135 phases
#if 0
| P_Fld( 1 , MISC_CG_CTRL9_RG_MCK4X_O_OPENLOOP_MODE_EN ) \
| P_Fld( 1 , MISC_CG_CTRL9_RG_CG_DDR400_MCK4X_O_OFF ) \
| P_Fld( 0 , MISC_CG_CTRL9_RG_DDR400_MCK4X_O_FORCE_ON ) \
@ -1126,31 +1111,13 @@ static void SPM_control(DRAMC_CTX_T *p,ANA_top_config_T *a_cfg)
static void DIG_DCM_nonshuffle_config(DRAMC_CTX_T *p)
{
//RX DCM
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_RX_CG_CTRL), P_Fld(3 , MISC_SHU_RX_CG_CTRL_RX_DCM_EXT_DLY ));
}
static void DIG_PHY_SHU_MISC_CG_CTRL(DRAMC_CTX_T *p)
{
//bit 0 : DPHY_NAO_GLUE_B0.mck_dq_cg_ctrl
//bit 1 : DPHY_NAO_GLUE_B1.mck_dq_cg_ctrl
//bit 2 : DPHY_NAO_GLUE_CA.mck_ca_cg_ctrl
//bit 4 : DPHY_NAO_GLUE_B0.rx_mck_dq_cg_ctrl
//bit 5 : DPHY_NAO_GLUE_B1.rx_mck_dq_cg_ctrl
//bit 6 : DPHY_NAO_GLUE_CA.rx_mck_ca_cg_ctrl
//bit [9 : 8] : DPHY_TX_BRIDGE_GLUE.ddrphy_idle
//bit [11:10] : DPHY_TX_BRIDGE_GLUE.ddrphy_idle_dq
//bit [13:12] : DPHY_TX_BRIDGE_GLUE.ddrphy_idle_tx_cmd
//bit [17:16] : DPHY_TX_BRIDGE_GLUE.ddrphy_idle_tx_b0
//bit [19:18] : DPHY_TX_BRIDGE_GLUE.ddrphy_idle_tx_b1
//bit [22:20] : DPHY_TX_BRIDGE_GLUE.ddrphy_idle_rx_cmd
//bit [26:24] : DPHY_TX_BRIDGE_GLUE.ddrphy_idle_rx_b0
//bit [30:28] : DPHY_TX_BRIDGE_GLUE.ddrphy_idle_rx_b1
// vIO32Write4B (DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_CG_CTRL0), 0x333f3f00);
// //1. ignore NAO_GLUE cg ctrl,
// 2.00:ddrphy_idle/_ca/b0/b1 01: ddrphy_idle_shuopt 10: ddrphy_idle_shuopt_pinmux
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_CG_CTRL0), 0x33400000);//rx_cmd_idle tie 1 others DCM control depend on CA B0 B1 independtly -- could save more power
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_CG_CTRL0), 0x33400000);
}
static void ANA_IMP_configure(DRAMC_CTX_T *p)
@ -1167,18 +1134,14 @@ static void ANA_IMP_configure(DRAMC_CTX_T *p)
static void ANA_CLOCK_SWITCH(DRAMC_CTX_T *p)
{
//OPENLOOP MODE. w_chg_mem_mck1x
if(A_D->DQ_CA_OPEN)
{
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CG_CTRL0) , P_Fld( 1 , MISC_CG_CTRL0_RESERVED_MISC_CG_CTRL0_BIT3_1));
mcDELAY_XNS(100);
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CG_CTRL0) , P_Fld( 0 , MISC_CG_CTRL0_RESERVED_MISC_CG_CTRL0_BIT3_1));
}
//mem_sel _____|------------------------------------
//w_chg_mem ______________|------------|______________
//BLCK __|---|___|---|____________|-|_|-|_|-|_|-
// |<- 26M ->|<- MUTE ->|<- MCK4X ->|
//before DLL enable switch feedback clock
DramcBroadcastOnOff(DRAMC_BROADCAST_OFF);
vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CKMUX_SEL) , P_Fld( 1 , MISC_CKMUX_SEL_R_PHYCTRLDCM ) \
| P_Fld( 1 , MISC_CKMUX_SEL_R_PHYCTRLMUX ));
@ -1186,12 +1149,11 @@ static void ANA_CLOCK_SWITCH(DRAMC_CTX_T *p)
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CG_CTRL0) , P_Fld( 1 , MISC_CG_CTRL0_CLK_MEM_SEL ) \
| P_Fld( 1 , MISC_CG_CTRL0_W_CHG_MEM ));
mcDELAY_XNS(100);//reserve 100ns period for clock mute and latch the rising edge sync condition for BCLK
mcDELAY_XNS(100);
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CG_CTRL0) , P_Fld( 0 , MISC_CG_CTRL0_W_CHG_MEM ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CG_CTRL0) , P_Fld( 1 , MISC_CG_CTRL0_RG_FREERUN_MCK_CG ));
//after clock change, if OPEN LOOP MODE should change clock to 1x. bit7 is RG_dvfs_clk_mem_mck1x_sel
if(A_D->DQ_CA_OPEN)
{
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CG_CTRL0) , P_Fld( 1 , MISC_CG_CTRL0_RESERVED_MISC_CG_CTRL0_BIT7));
@ -1221,15 +1183,10 @@ void ANA_Config_shuffle(DRAMC_CTX_T *p,ANA_top_config_T *a_cfg,U8 group_id)
DIG_PHY_SHU_MISC_CG_CTRL(p);
ANA_CLK_DIV_config_setting(p,A_D,a_cfg);
ANA_DLL_shuffle_Config(p,a_cfg);
// ANA_sequence_shuffle_colletion(p,&ana_core_p);
}
static void ANA_PHY_Config(DRAMC_CTX_T *p,ANA_top_config_T *a_cfg)
{
//RESET DPM
//vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_MD32_REG_SSPM_CFGREG_SW_RSTN), 32'h1000_0001 );
// SC_DPY_MODE_SW(PULL_UP);
ANA_Config_nonshuffle(p,a_cfg);
ANA_Config_shuffle(p,a_cfg,0);
}
@ -1253,8 +1210,6 @@ static void ANA_MIDPI_sequence(DRAMC_CTX_T *p,ANA_DVFS_CORE_T *tr)
vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ1) , 1, SHU_B1_DQ1_RG_ARPI_MIDPI_LDO_VREF_SEL_B1 );
vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD1) , 1, SHU_CA_CMD1_RG_ARPI_MIDPI_LDO_VREF_SEL_CA );
//ASVA 2-6
//step1: CG high. --disable 8 phase clk output
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DLL_ARPI2) , P_Fld( 1 , SHU_B0_DLL_ARPI2_RG_ARPI_MPDIV_CG_B0 ) \
| P_Fld( 1 , SHU_B0_DLL_ARPI2_RG_ARPI_CG_FB_B0 ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DLL_ARPI2) , P_Fld( 1 , SHU_B1_DLL_ARPI2_RG_ARPI_MPDIV_CG_B1 ) \
@ -1262,7 +1217,6 @@ static void ANA_MIDPI_sequence(DRAMC_CTX_T *p,ANA_DVFS_CORE_T *tr)
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_DLL_ARPI2) , P_Fld( 1 , SHU_CA_DLL_ARPI2_RG_ARPI_MPDIV_CG_CA ) \
| P_Fld( 1 , SHU_CA_DLL_ARPI2_RG_ARPI_CG_FB_CA ));
//CG
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DLL_ARPI2), P_Fld(0x1, SHU_B0_DLL_ARPI2_RG_ARPI_CG_MCK_B0)
| P_Fld(0x1, SHU_B0_DLL_ARPI2_RG_ARPI_CG_MCK_FB2DLL_B0)
| P_Fld(0x1, SHU_B0_DLL_ARPI2_RG_ARPI_CG_MCTL_B0)
@ -1291,12 +1245,11 @@ static void ANA_MIDPI_sequence(DRAMC_CTX_T *p,ANA_DVFS_CORE_T *tr)
| P_Fld(0x1, SHU_CA_DLL_ARPI2_RG_ARPI_CG_CLKIEN)
| P_Fld(0x1, SHU_CA_DLL_ARPI2_RG_ARPI_MPDIV_CG_CA));
//step2:PLLGP_CK_SEL -- Initial no need it
//step3: PLLCK_EN disable
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_PLL2) , P_Fld( 0 , SHU_PLL2_RG_RPHYPLL_ADA_MCK8X_EN_SHU )); //refer to MISC_DVFSCTRL2
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_PLL2) , P_Fld( 0 , SHU_PLL2_RG_RPHYPLL_ADA_MCK8X_EN_SHU ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_PHYPLL2) , P_Fld( 0 , PHYPLL2_RG_RPHYPLL_AD_MCK8X_EN ) \
| P_Fld( 0 , PHYPLL2_RG_RPHYPLL_ADA_MCK8X_EN ));
//step4:MIDPI_EN
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ1) , P_Fld((!((tr->DQ_SEMI_OPEN)||(tr->DQ_CA_OPEN)))&&(!(tr->DQ_CKDIV4_EN)), SHU_B0_DQ1_RG_ARPI_MIDPI_EN_B0 ) \
| P_Fld((!(tr->DQ_SEMI_OPEN))&&(tr->DQ_CKDIV4_EN), SHU_B0_DQ1_RG_ARPI_MIDPI_CKDIV4_EN_B0 ) \
| P_Fld( tr->PH8_DLY , SHU_B0_DQ1_RG_ARPI_MIDPI_8PH_DLY_B0 ));
@ -1314,7 +1267,7 @@ static void ANA_MIDPI_sequence(DRAMC_CTX_T *p,ANA_DVFS_CORE_T *tr)
}
else// for DSC semi-open CHA B1 and CHB B1 is different
else
{
DramcBroadcastOnOff(DRAMC_BROADCAST_OFF);
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ1) , P_Fld((!tr->DQ_CA_OPEN)&&(!(tr->CA_CKDIV4_EN)), SHU_B1_DQ1_RG_ARPI_MIDPI_EN_B1 ) \
@ -1353,7 +1306,7 @@ static void ANA_MIDPI_sequence(DRAMC_CTX_T *p,ANA_DVFS_CORE_T *tr)
DramcBroadcastOnOff(DRAMC_BROADCAST_ON);
}
// for both EMCP and DSC semi-open CHA CA and CHB CA settings are needed
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD1) , P_Fld( (!(tr->DQ_CA_OPEN))&&(!(tr->CA_CKDIV4_EN)), SHU_CA_CMD1_RG_ARPI_MIDPI_EN_CA ) \
| P_Fld( tr->CA_CKDIV4_EN , SHU_CA_CMD1_RG_ARPI_MIDPI_CKDIV4_EN_CA )
| P_Fld( tr->PH8_DLY , SHU_CA_CMD1_RG_ARPI_MIDPI_8PH_DLY_CA ));
@ -1361,7 +1314,7 @@ static void ANA_MIDPI_sequence(DRAMC_CTX_T *p,ANA_DVFS_CORE_T *tr)
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_SHU_MIDPI_CTRL) , P_Fld( (!(tr->DQ_CA_OPEN))&&(!(tr->CA_CKDIV4_EN)), CA_SHU_MIDPI_CTRL_MIDPI_ENABLE_CA ) \
| P_Fld( tr->CA_CKDIV4_EN , CA_SHU_MIDPI_CTRL_MIDPI_DIV4_ENABLE_CA ));
//step5:PI_RESETB
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_DLL_ARPI0) , P_Fld( 0 , CA_DLL_ARPI0_RG_ARPI_RESETB_CA ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DLL_ARPI0) , P_Fld( 0 , B0_DLL_ARPI0_RG_ARPI_RESETB_B0 ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DLL_ARPI0) , P_Fld( 0 , B1_DLL_ARPI0_RG_ARPI_RESETB_B1 ));
@ -1369,12 +1322,11 @@ static void ANA_MIDPI_sequence(DRAMC_CTX_T *p,ANA_DVFS_CORE_T *tr)
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_DLL_ARPI0) , P_Fld( 1 , CA_DLL_ARPI0_RG_ARPI_RESETB_CA ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DLL_ARPI0) , P_Fld( 1 , B0_DLL_ARPI0_RG_ARPI_RESETB_B0 ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DLL_ARPI0) , P_Fld( 1 , B1_DLL_ARPI0_RG_ARPI_RESETB_B1 ));
//step6: PLLCK_EN enable
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_PLL2) , P_Fld( 1 , SHU_PLL2_RG_RPHYPLL_ADA_MCK8X_EN_SHU )); //refer to MISC_DVFSCTRL2
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_PLL2) , P_Fld( 1 , SHU_PLL2_RG_RPHYPLL_ADA_MCK8X_EN_SHU ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_PHYPLL2) , P_Fld( 1 , PHYPLL2_RG_RPHYPLL_AD_MCK8X_EN ) \
| P_Fld( 1 , PHYPLL2_RG_RPHYPLL_ADA_MCK8X_EN ));
//step7: release CG 8 Phase clk enable
//CG
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DLL_ARPI2), P_Fld(0x0, SHU_B0_DLL_ARPI2_RG_ARPI_CG_MCK_B0)
| P_Fld(0x0, SHU_B0_DLL_ARPI2_RG_ARPI_CG_MCK_FB2DLL_B0)
| P_Fld(0x0, SHU_B0_DLL_ARPI2_RG_ARPI_CG_MCTL_B0)
@ -1431,11 +1383,11 @@ static void ANA_DLL_sequence(DRAMC_CTX_T *p,ANA_DVFS_CORE_T *tr,ANA_top_config_T
ALL_SLAVE_EN = a_cfg->ALL_SLAVE_EN;
mcSHOW_DBG_MSG6(("[ANA_INIT] DLL >>>>>>>> \n"));
//step1: DLL_RESETB
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD8) , P_Fld( 1 , CA_CMD8_RG_ARDLL_RESETB_CA ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ8) , P_Fld( 1 , B0_DQ8_RG_ARDLL_RESETB_B0 ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ8) , P_Fld( 1 , B1_DQ8_RG_ARDLL_RESETB_B1 ));
//step2: master DLL_EN
if(ALL_SLAVE_EN == 1)
{
if (tr->DQ_SEMI_OPEN)
@ -1446,7 +1398,7 @@ static void ANA_DLL_sequence(DRAMC_CTX_T *p,ANA_DVFS_CORE_T *tr,ANA_top_config_T
mcDELAY_XNS(300);
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DLL1) , P_Fld( 0 , SHU_B0_DLL1_RG_ARDLL_PHDET_EN_B0));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DLL1) , P_Fld( 0 , SHU_B1_DLL1_RG_ARDLL_PHDET_EN_B1));
mcDELAY_XNS(400); //2nd DLL > 77TMCK
mcDELAY_XNS(400);
}
else
{
@ -1456,7 +1408,7 @@ static void ANA_DLL_sequence(DRAMC_CTX_T *p,ANA_DVFS_CORE_T *tr,ANA_top_config_T
mcDELAY_XNS(300);
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DLL1) , P_Fld(!(tr->DQ_SEMI_OPEN), SHU_B0_DLL1_RG_ARDLL_PHDET_EN_B0));
vIO32WriteFldMulti(DRAMC_REG_ADDR(SLV_DLL_PHDET_EN_Reg.u4Addr) , P_Fld(!(tr->DQ_SEMI_OPEN), SLV_DLL_PHDET_EN_Reg.u4Fld));
mcDELAY_XNS(400); //2nd DLL > 77TMCK
mcDELAY_XNS(400);
}
}
else
@ -1466,47 +1418,42 @@ static void ANA_DLL_sequence(DRAMC_CTX_T *p,ANA_DVFS_CORE_T *tr,ANA_top_config_T
DramcBroadcastOnOff(DRAMC_BROADCAST_OFF);
vIO32WriteFldMulti_All(DRAMC_REG_ADDR(MS_DLL_PHDET_EN_Reg.u4Addr) , P_Fld( 1 , MS_DLL_PHDET_EN_Reg.u4Fld));
DramcBroadcastOnOff(DRAMC_BROADCAST_ON);
mcDELAY_XNS(300); //1st DLL > 55 TMCK
mcDELAY_XNS(300);
}
else
{
DramcBroadcastOnOff(DRAMC_BROADCAST_OFF);
vIO32WriteFldMulti(DRAMC_REG_ADDR(MS_DLL_PHDET_EN_Reg.u4Addr) , P_Fld( 1 , MS_DLL_PHDET_EN_Reg.u4Fld));
mcDELAY_XNS(300); //1st DLL >55T MCK
mcDELAY_XNS(300);
vSetPHY2ChannelMapping(p, CHANNEL_B);
vIO32WriteFldMulti(DRAMC_REG_ADDR(MS_DLL_PHDET_EN_Reg.u4Addr) , P_Fld( 1 , MS_DLL_PHDET_EN_Reg.u4Fld));
#if (CHANNEL_NUM>2)
if (channel_num_auxadc > 2) {
vSetPHY2ChannelMapping(p, CHANNEL_C);
vIO32WriteFldMulti(DRAMC_REG_ADDR(MS_DLL_PHDET_EN_Reg.u4Addr) , P_Fld( 1 , MS_DLL_PHDET_EN_Reg.u4Fld));
mcDELAY_XNS(300); //1st DLL >55T MCK
mcDELAY_XNS(300);
vSetPHY2ChannelMapping(p, CHANNEL_D);
vIO32WriteFldMulti(DRAMC_REG_ADDR(MS_DLL_PHDET_EN_Reg.u4Addr) , P_Fld( 1 , MS_DLL_PHDET_EN_Reg.u4Fld));
}
#endif
mcDELAY_XNS(300); //1st DLL >55T MCK
mcDELAY_XNS(300);
vSetPHY2ChannelMapping(p, CHANNEL_A);
DramcBroadcastOnOff(DRAMC_BROADCAST_ON);
}
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DLL1) , P_Fld(!(tr->DQ_SEMI_OPEN), SHU_B0_DLL1_RG_ARDLL_PHDET_EN_B0 ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(SLV_DLL_PHDET_EN_Reg.u4Addr) , P_Fld(!(tr->DQ_SEMI_OPEN), SLV_DLL_PHDET_EN_Reg.u4Fld ));
mcDELAY_XNS(400); //2nd DLL > 77TMCK
mcDELAY_XNS(400);
mcSHOW_DBG_MSG6(("[ANA_INIT] DLL <<<<<<<< \n"));
}
}
//shuffle register for ANA initial flow control
//It is not easy for initial sequence SA/DV coding --- same register for different group. need two different method to manage it
//1. for seqeunce
//2. for another shuffle group need to DMA to SRAM
void ANA_sequence_shuffle_colletion(DRAMC_CTX_T *p,ANA_DVFS_CORE_T *tr)
{
BOOL isLP4_DSC = (p->DRAMPinmux == PINMUX_DSC)?1:0;
//PLL
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_PLL2) , P_Fld( 1 , SHU_PLL2_RG_RPHYPLL_ADA_MCK8X_EN_SHU )); //refer to MISC_DVFSCTRL2
//MIDPI
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_PLL2) , P_Fld( 1 , SHU_PLL2_RG_RPHYPLL_ADA_MCK8X_EN_SHU ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DLL_ARPI2) , P_Fld( tr->DQ_SEMI_OPEN , SHU_B0_DLL_ARPI2_RG_ARPI_MPDIV_CG_B0 ) \
| P_Fld( 0 , SHU_B0_DLL_ARPI2_RG_ARPI_CG_FB_B0 ) \
| P_Fld( tr->DQ_SEMI_OPEN , SHU_B0_DLL_ARPI2_RG_ARPI_CG_MCK_FB2DLL_B0));
@ -1550,24 +1497,20 @@ void ANA_sequence_shuffle_colletion(DRAMC_CTX_T *p,ANA_DVFS_CORE_T *tr)
static void ANA_ClockOff_Sequence(DRAMC_CTX_T *p)
{
BOOL isLP4_DSC = (p->DRAMPinmux == PINMUX_DSC)?1:0;
/* Dynamic CKE to let HW disable CLK_TXD, avoiding CLK parking state violation during CKE high
* Note: BROADCAST is ON here
*/
CKEFixOnOff(p, TO_ALL_RANK, CKE_DYNAMIC, TO_ONE_CHANNEL);
mcDELAY_US(1);
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CG_CTRL0), P_Fld(0, MISC_CG_CTRL0_CLK_MEM_SEL)
| P_Fld(1, MISC_CG_CTRL0_W_CHG_MEM));
mcDELAY_XNS(100);//reserve 100ns period for clock mute and latch the rising edge sync condition for BCLK
mcDELAY_XNS(100);
vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CG_CTRL0), 0, MISC_CG_CTRL0_W_CHG_MEM);
// @Darren, Fix 26M clock issue after DDR400 open loop mode (fail case: 26M/4)
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CG_CTRL0) , P_Fld( 0 , MISC_CG_CTRL0_RESERVED_MISC_CG_CTRL0_BIT3_1));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CG_CTRL0) , P_Fld( 1 , MISC_CG_CTRL0_RESERVED_MISC_CG_CTRL0_BIT3_1));
mcDELAY_XNS(100);
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CG_CTRL0) , P_Fld( 0 , MISC_CG_CTRL0_RESERVED_MISC_CG_CTRL0_BIT3_1));
//DLL Off
vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DLL1), 0, SHU_B0_DLL1_RG_ARDLL_PHDET_EN_B0);
if (!isLP4_DSC)
{
@ -1584,7 +1527,6 @@ static void ANA_ClockOff_Sequence(DRAMC_CTX_T *p)
DramcBroadcastOnOff(DRAMC_BROADCAST_ON);
}
//CG
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DLL_ARPI2), P_Fld(0x1, SHU_B0_DLL_ARPI2_RG_ARPI_CG_MCK_B0)
| P_Fld(0x1, SHU_B0_DLL_ARPI2_RG_ARPI_CG_MCK_FB2DLL_B0)
| P_Fld(0x1, SHU_B0_DLL_ARPI2_RG_ARPI_CG_MCTL_B0)
@ -1637,12 +1579,10 @@ static void ANA_ClockOff_Sequence(DRAMC_CTX_T *p)
| P_Fld(0x1, SHU_B1_DLL_ARPI2_RG_ARPI_MPDIV_CG_B1));
}
//PLLCK
vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_PLL2), 0, SHU_PLL2_RG_RPHYPLL_ADA_MCK8X_EN_SHU); //refer to MISC_DVFSCTRL2
vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_PLL2), 0, SHU_PLL2_RG_RPHYPLL_ADA_MCK8X_EN_SHU);
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_PHYPLL2), P_Fld(0, PHYPLL2_RG_RPHYPLL_AD_MCK8X_EN)
| P_Fld(0, PHYPLL2_RG_RPHYPLL_ADA_MCK8X_EN));
//PLL
vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_PHYPLL0), 0, PHYPLL0_RG_RPHYPLL_EN);
vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_PHYPLL2), 0, PHYPLL2_RG_RPHYPLL_RESETB);
@ -1655,11 +1595,11 @@ static void TransferToSPM_Sequence(DRAMC_CTX_T *p)
mcDELAY_XUS(20);
vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_RG_DFS_CTRL), 0x1, MISC_RG_DFS_CTRL_SPM_DVFS_CONTROL_SEL);
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_MD32_REG_LPIF_FSM_CFG_1),
/* TBA set control mux in DV initial */
P_Fld(0x1, LPIF_FSM_CFG_1_LPIF_LEGACY_CONTROL) | // 0: DPM, 1: SPM
P_Fld(0x1, LPIF_FSM_CFG_1_LPIF_LEGACY_CONTROL_2ND) | // 0: DPM, 1: SPM
P_Fld(0x1, LPIF_FSM_CFG_1_LPIF_LEGACY_CONTROL_FOR_PWR) | // 0: DPM, 1: SPM
P_Fld(0x1, LPIF_FSM_CFG_1_LPIF_LEGACY_CONTROL_FOR_PWR_2ND)); // 0: DPM, 1: SPM
P_Fld(0x1, LPIF_FSM_CFG_1_LPIF_LEGACY_CONTROL) |
P_Fld(0x1, LPIF_FSM_CFG_1_LPIF_LEGACY_CONTROL_2ND) |
P_Fld(0x1, LPIF_FSM_CFG_1_LPIF_LEGACY_CONTROL_FOR_PWR) |
P_Fld(0x1, LPIF_FSM_CFG_1_LPIF_LEGACY_CONTROL_FOR_PWR_2ND));
}
static void ANA_init_sequence(DRAMC_CTX_T *p,ANA_DVFS_CORE_T *tr,ANA_top_config_T *a_cfg)
@ -1667,7 +1607,7 @@ static void ANA_init_sequence(DRAMC_CTX_T *p,ANA_DVFS_CORE_T *tr,ANA_top_config_
mcSHOW_DBG_MSG6(("[ANA_INIT] flow start \n"));
ANA_PLL_sequence(p);
ANA_MIDPI_sequence(p,tr);
ANA_CLOCK_SWITCH(p); //clock switch supply correct FB clk. have to do this before DLL
ANA_CLOCK_SWITCH(p);
ANA_DLL_sequence(p,tr,a_cfg);
mcSHOW_DBG_MSG6(("[ANA_INIT] flow end \n"));
}
@ -1676,7 +1616,7 @@ void ANA_init(DRAMC_CTX_T *p)
{
BOOL isLP4_DSC = (p->DRAMPinmux == PINMUX_DSC)?1:0;
#if (fcFOR_CHIP_ID == fc8195)
DRAM_PINMUX DRAM_Pinmux = p->DRAMPinmux; // 0: EMCP, 1: DSC, 2: MCP, 3:DSC_REV
DRAM_PINMUX DRAM_Pinmux = p->DRAMPinmux;
#endif
DRAMC_SUBSYS_PRE_CONFIG(p, &DV_p);
@ -1687,7 +1627,6 @@ void ANA_init(DRAMC_CTX_T *p)
#endif
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CKMUX_SEL) , P_Fld( isLP4_DSC, MISC_CKMUX_SEL_R_DMMCTLPLL_CKSEL ));
//Disable CMD
CmdOEOnOff(p, DISABLE, CMDOE_DIS_TO_ONE_CHANNEL);
#if REPLACE_DFS_RG_MODE
TransferToSPM_Sequence(p);
@ -1695,7 +1634,7 @@ void ANA_init(DRAMC_CTX_T *p)
ANA_ClockOff_Sequence(p);
ANA_PHY_Config(p,A_T);
ANA_init_sequence(p,A_D,A_T);
//Enable CMD
CmdOEOnOff(p, ENABLE, CMDOE_DIS_TO_ONE_CHANNEL);
LP4_single_end_DRAMC_post_config(p, M_LP4->LP4Y_EN);
mcSHOW_DBG_MSG6(("[ANA_INIT] <<<<<<<<<<<<< \n"));

159
src/vendorcode/mediatek/mt8195/dramc/DIG_NONSHUF_config.c
View File

@ -5,9 +5,6 @@
Gating_confg_T Gat_p;
//============================================
// digital PHY config
//============================================
static void DIG_PHY_config(DRAMC_CTX_T *p)
{
#if ENABLE_PINMUX_FOR_RANK_SWAP
@ -43,7 +40,7 @@ static void DIG_PHY_config(DRAMC_CTX_T *p)
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DVFS_EMI_CLK) , P_Fld( 1 , MISC_DVFS_EMI_CLK_RG_DLL_SHUFFLE_DDRPHY ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ9) , P_Fld( 1 , B0_DQ9_R_DMRXFIFO_STBENCMP_EN_B0 ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ9) , P_Fld( (!isLP4_DSC) , B1_DQ9_R_DMRXFIFO_STBENCMP_EN_B1 ));//TODO:check
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ9) , P_Fld( (!isLP4_DSC) , B1_DQ9_R_DMRXFIFO_STBENCMP_EN_B1 ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD9) , P_Fld( isLP4_DSC , CA_CMD9_R_DMRXFIFO_STBENCMP_EN_CA ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CTRL1) , P_Fld(RK_SWAP_EN, MISC_CTRL1_R_RK_PINMUXSWAP_EN ));
@ -52,21 +49,21 @@ static void DIG_PHY_config(DRAMC_CTX_T *p)
if(A_T->NEW_RANK_MODE==0)
{
//B0
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ9) , P_Fld( 4 , B0_DQ9_R_IN_GATE_EN_LOW_OPT_B0 ) \
| P_Fld( 0 , B0_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B0 ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ10) , P_Fld( 0 , B0_DQ10_ARPI_CG_RK1_SRC_SEL_B0 ));//TODO:check
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ10) , P_Fld( 0 , B0_DQ10_ARPI_CG_RK1_SRC_SEL_B0 ));
if (isLP4_DSC)
{
//CA
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD9) , P_Fld( 4 , CA_CMD9_R_IN_GATE_EN_LOW_OPT_CA ) \
| P_Fld( 0 , CA_CMD9_R_DMRXDVS_R_F_DLY_RK_OPT ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD10) , P_Fld( 0 , CA_CMD10_ARPI_CG_RK1_SRC_SEL_CA ));//TODO:check
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD10) , P_Fld( 0 , CA_CMD10_ARPI_CG_RK1_SRC_SEL_CA ));
}
else
{
//B1
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ9) , P_Fld( 4 , B1_DQ9_R_IN_GATE_EN_LOW_OPT_B1 ) \
| P_Fld( 0 , B1_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B1 ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ10) , P_Fld( 0 , B1_DQ10_ARPI_CG_RK1_SRC_SEL_B1 ));
@ -74,24 +71,24 @@ static void DIG_PHY_config(DRAMC_CTX_T *p)
}
else
{
//B0
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ9) , P_Fld( 0 , B0_DQ9_R_IN_GATE_EN_LOW_OPT_B0 ) \
| P_Fld( 1 , B0_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B0 ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ10) , P_Fld( 1 , B0_DQ10_ARPI_CG_RK1_SRC_SEL_B0 ));
if (isLP4_DSC)
{
//CA
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD9) , P_Fld( 0 , CA_CMD9_R_IN_GATE_EN_LOW_OPT_CA ) \
| P_Fld( 1 , CA_CMD9_R_DMRXDVS_R_F_DLY_RK_OPT ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD10) , P_Fld( 1 , CA_CMD10_ARPI_CG_RK1_SRC_SEL_CA ));//TODO:check
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD10) , P_Fld( 1 , CA_CMD10_ARPI_CG_RK1_SRC_SEL_CA ));
}
else
{
//B1
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ9) , P_Fld( 0 , B1_DQ9_R_IN_GATE_EN_LOW_OPT_B1 ) \
| P_Fld( 1 , B1_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B1 ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ10) , P_Fld( 1 , B1_DQ10_ARPI_CG_RK1_SRC_SEL_B1 ));//TODO:check
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ10) , P_Fld( 1 , B1_DQ10_ARPI_CG_RK1_SRC_SEL_B1 ));
}
}
@ -109,11 +106,11 @@ static void DIG_PHY_config(DRAMC_CTX_T *p)
static void GATING_MODE_CFG(Gating_confg_T *tr)
{
tr->GAT_TRACK_EN = ((A_D->DQ_SEMI_OPEN == 1)||(A_D->DQ_CA_OPEN==1))?0:1;
tr->RX_GATING_MODE = 2; //fix 7UI mode under LPDDR4
tr->RX_GATING_TRACK_MODE = 2; //fix FIFO mode under LPDDR4
tr->PICG_EARLY_EN = 1; //fix under LPDDR4, if LPDDR5 have to set 1
tr->SELPH_MODE = 1; //random inside {0,1} //for improve APHY XRTR2R. NEW_APHY MODE with 1.
tr->VALID_LAT_VALUE = 1; //random inside {0,1}
tr->RX_GATING_MODE = 2;
tr->RX_GATING_TRACK_MODE = 2;
tr->PICG_EARLY_EN = 1;
tr->SELPH_MODE = 1;
tr->VALID_LAT_VALUE = 1;
mcSHOW_DBG_MSG6(("============================================================== \n"));
mcSHOW_DBG_MSG6(("Gating Mode config\n" ));
@ -132,9 +129,9 @@ static void GATING_MODE_CFG(Gating_confg_T *tr)
mcSHOW_DBG_MSG6(("============================================================== \n"));
}
//======================================
//gating widnow mode
//======================================
static void DPHY_GAT_TRACK_Config(DRAMC_CTX_T *p,Gating_confg_T *gat_c)
{
BOOL isLP4_DSC = (p->DRAMPinmux == PINMUX_DSC)?1:0;
@ -155,12 +152,9 @@ static void DPHY_GAT_TRACK_Config(DRAMC_CTX_T *p,Gating_confg_T *gat_c)
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL2) , P_Fld( 1 , MISC_STBCAL2_STB_PICG_EARLY_1T_EN ));
}
//================================
//gating Mode config
//================================
switch (gat_c->RX_GATING_MODE)
{
//Pulse Mode
case 0:
{
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ9) , P_Fld( 0 , B0_DQ9_RG_RX_ARDQS0_DQSIENMODE_B0 ));
@ -170,7 +164,7 @@ static void DPHY_GAT_TRACK_Config(DRAMC_CTX_T *p,Gating_confg_T *gat_c)
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_STBCAL) , P_Fld( 0 , MISC_SHU_STBCAL_DQSIEN_BURST_MODE ));
break;
}
// Burst Mode (8UI)
case 1:
{
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ9) , P_Fld( 1 , B0_DQ9_RG_RX_ARDQS0_DQSIENMODE_B0 ));
@ -179,7 +173,7 @@ static void DPHY_GAT_TRACK_Config(DRAMC_CTX_T *p,Gating_confg_T *gat_c)
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ6) , P_Fld( 1 , B1_DQ6_RG_RX_ARDQ_BIAS_VREF_SEL_B1));
break;
}
// Burst Mode (7UI)
case 2:
{
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ9) , P_Fld( 1 , B0_DQ9_RG_RX_ARDQS0_DQSIENMODE_B0 ));
@ -189,7 +183,7 @@ static void DPHY_GAT_TRACK_Config(DRAMC_CTX_T *p,Gating_confg_T *gat_c)
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL1) , P_Fld( 1 , MISC_STBCAL1_DQSIEN_7UI_EN ));
break;
}
// Oringinal Burst
case 3:
{
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ9) , P_Fld( 1 , B0_DQ9_RG_RX_ARDQS0_DQSIENMODE_B0 ));
@ -205,15 +199,12 @@ static void DPHY_GAT_TRACK_Config(DRAMC_CTX_T *p,Gating_confg_T *gat_c)
}
}
//================================
//Gating tracking Mode config
//================================
switch (gat_c->RX_GATING_TRACK_MODE)
{
//Valid DLY Mode
case 0:
{
//TODO SHU1_DQSG if -like mode should set STB_UPDMASKCYC = 0 STB_UPDMASK_EN=0 others STB_UPDMASKCYC=9 STB_UPDMASK_EN=1
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL) , P_Fld( 1 , MISC_STBCAL_STB_DQIEN_IG ) \
| P_Fld( 1 , MISC_STBCAL_PICHGBLOCK_NORD ) \
| P_Fld( 0 , MISC_STBCAL_REFUICHG ) \
@ -231,7 +222,7 @@ static void DPHY_GAT_TRACK_Config(DRAMC_CTX_T *p,Gating_confg_T *gat_c)
| P_Fld( 2 , MISC_CTRL0_R_DMVALID_DLY ) \
| P_Fld( 1 , MISC_CTRL0_R_DMVALID_DLY_OPT ) \
| P_Fld( 0 , MISC_CTRL0_R_DMSTBEN_SYNCOPT ) \
| P_Fld( 0 , MISC_CTRL0_R_DMVALID_NARROW_IG )); //TODO
| P_Fld( 0 , MISC_CTRL0_R_DMVALID_NARROW_IG ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ6) , P_Fld( 1 , B0_DQ6_RG_RX_ARDQ_DMRANK_OUTSEL_B0));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ9) , P_Fld( 0 , B0_DQ9_R_DMDQSIEN_RDSEL_LAT_B0 ) \
| P_Fld( 0 , B0_DQ9_R_DMDQSIEN_VALID_LAT_B0 ));
@ -246,7 +237,7 @@ static void DPHY_GAT_TRACK_Config(DRAMC_CTX_T *p,Gating_confg_T *gat_c)
}
break;
}
//-like Mode
case 1:
{
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL) , P_Fld( 0 , MISC_STBCAL_STB_DQIEN_IG ) \
@ -281,7 +272,7 @@ static void DPHY_GAT_TRACK_Config(DRAMC_CTX_T *p,Gating_confg_T *gat_c)
}
break;
}
//FIFO Mode
case 2:
{
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL) , P_Fld( 1 , MISC_STBCAL_STB_DQIEN_IG ) \
@ -301,7 +292,7 @@ static void DPHY_GAT_TRACK_Config(DRAMC_CTX_T *p,Gating_confg_T *gat_c)
| P_Fld( 0 , MISC_CTRL0_R_DMVALID_DLY ) \
| P_Fld( 0 , MISC_CTRL0_R_DMVALID_DLY_OPT ) \
| P_Fld( 0 , MISC_CTRL0_R_DMSTBEN_SYNCOPT ) \
| P_Fld( 0 , MISC_CTRL0_R_DMVALID_NARROW_IG )); // @Darren, func no use sync MP settings from HJ
| P_Fld( 0 , MISC_CTRL0_R_DMVALID_NARROW_IG ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ6) , P_Fld( 0 , B0_DQ6_RG_RX_ARDQ_DMRANK_OUTSEL_B0));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ9) , P_Fld( 1+gat_c->VALID_LAT_VALUE , B0_DQ9_R_DMDQSIEN_RDSEL_LAT_B0 ) \
| P_Fld( 0+gat_c->VALID_LAT_VALUE , B0_DQ9_R_DMDQSIEN_VALID_LAT_B0 ));
@ -341,7 +332,7 @@ static void DPHY_GAT_TRACK_Config(DRAMC_CTX_T *p,Gating_confg_T *gat_c)
| P_Fld( 0 , MISC_STBCAL2_STB_GERR_RST ) \
| P_Fld( 1 , MISC_STBCAL2_STB_GERR_B01 ) \
| P_Fld( 0 , MISC_STBCAL2_STB_GERR_B23 ));
//PICG_MODE only support new mode so here fix 1
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_RX_IN_GATE_EN_CTRL), P_Fld(1, MISC_RX_IN_GATE_EN_CTRL_RX_IN_GATE_EN_OPT ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_RX_IN_BUFF_EN_CTRL), P_Fld(1, MISC_RX_IN_BUFF_EN_CTRL_RX_IN_BUFF_EN_OPT ));
@ -356,17 +347,17 @@ static void DPHY_GAT_TRACK_Config(DRAMC_CTX_T *p,Gating_confg_T *gat_c)
static void RX_INTPUT_Config(DRAMC_CTX_T *p)
{
U8 VALID_LAT = 1;// TODO inside {0,1}
U8 RDSEL_LAT = 2;// TODO alywas VALID_LAT+1;
U8 VALID_LAT = 1;
U8 RDSEL_LAT = 2;
U8 dq_min = 0;
U8 dq_max = 0xff;
U8 scale = 3;
U8 threadhold = 0;
U32 dqs_min = 0;
U32 dqs_max = 0x1ff;
U8 RX_force_upd = 0; //TODO
U8 F_LEADLAG = 0; //TODO
U8 RG_MODE_EN = 0; //TODO
U8 RX_force_upd = 0;
U8 F_LEADLAG = 0;
U8 RG_MODE_EN = 0;
U8 irank = 0;
U8 backup_rank = 0;
BOOL isLP4_DSC = (p->DRAMPinmux == PINMUX_DSC)?1:0;
@ -404,7 +395,7 @@ static void RX_INTPUT_Config(DRAMC_CTX_T *p)
for(irank = RANK_0; irank < p->support_rank_num; irank++)
{
vSetRank(p, irank);
//RK0--B0
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_RK_B0_RXDVS3 ) , P_Fld( dq_min , RK_B0_RXDVS3_RG_RK0_ARDQ_MIN_DLY_B0 ) \
| P_Fld( dq_max , RK_B0_RXDVS3_RG_RK0_ARDQ_MAX_DLY_B0 ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_RK_B0_RXDVS4 ) , P_Fld( dqs_min , RK_B0_RXDVS4_RG_RK0_ARDQS0_MIN_DLY_B0 ) \
@ -421,7 +412,7 @@ static void RX_INTPUT_Config(DRAMC_CTX_T *p)
| P_Fld( threadhold , RK_B0_RXDVS1_R_RK0_B0_DVS_TH_LEAD ));
//RK0--B1
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_RK_B1_RXDVS3 ) , P_Fld( dq_min , RK_B1_RXDVS3_RG_RK0_ARDQ_MIN_DLY_B1 ) \
| P_Fld( dq_max , RK_B1_RXDVS3_RG_RK0_ARDQ_MAX_DLY_B1 ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_RK_B1_RXDVS4 ) , P_Fld( dqs_min , RK_B1_RXDVS4_RG_RK0_ARDQS0_MIN_DLY_B1 ) \
@ -440,7 +431,7 @@ static void RX_INTPUT_Config(DRAMC_CTX_T *p)
vSetRank(p, backup_rank);
vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CG_CTRL1 ) , 0xffffffff , MISC_CG_CTRL1_R_DVS_DIV4_CG_CTRL ); //TODO
vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CG_CTRL1 ) , 0xffffffff , MISC_CG_CTRL1_R_DVS_DIV4_CG_CTRL );
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_RXDVS1 ) , P_Fld( F_LEADLAG , B0_RXDVS1_F_LEADLAG_TRACK_B0 ));
@ -481,13 +472,13 @@ static void RX_INTPUT_Config(DRAMC_CTX_T *p)
}
vSetRank(p, backup_rank);
//Enable RX input delay tracking..
//TODO notice here if SA should not enbale it before RX perbit calibration
if (RG_MODE_EN == 1)
{
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_RG_DFS_CTRL) , P_Fld( 1 , MISC_RG_DFS_CTRL_RG_DPY_RXDLY_TRACK_EN ));
} else {
// `TBA_TOP.dvfs_spm_vif.sc_dphy_reserved[1:0] = 2'b11; //TODO
}
mcSHOW_DBG_MSG6(("[RX_INPUT] configuration <<<<< \n"));
@ -495,9 +486,9 @@ static void RX_INTPUT_Config(DRAMC_CTX_T *p)
static void DDRPHY_PICG_Config(DRAMC_CTX_T *p)
{
U8 PICG_MODE = 1; // only support new Mode under
U8 PICG_MODE = 1;
U8 MISC_CG_EN = 1;
U8 MISC_CG_REVERSE_DEFAULT_ON = 0; //for default CG enable.
U8 MISC_CG_REVERSE_DEFAULT_ON = 0;
mcSHOW_DBG_MSG6(("Enter into PICG configuration >>>> \n"));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CTRL4) , P_Fld( PICG_MODE , MISC_CTRL4_R_OPT2_MPDIV_CG ) \
@ -512,7 +503,7 @@ static void DDRPHY_PICG_Config(DRAMC_CTX_T *p)
| P_Fld( !PICG_MODE , MISC_CTRL3_ARPI_CG_DQS_OPT ) \
| P_Fld( !PICG_MODE , MISC_CTRL3_ARPI_CG_DQ_OPT ));
//Notice here: MISC_CG_CTRL0_RG_CG_COMB0_OFF_DISABLE = 1 will leading other_shuffle_group before register settle down latch ->error. can not set to 1
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CG_CTRL0) , P_Fld( !MISC_CG_EN , MISC_CG_CTRL0_RG_CG_DRAMC_OFF_DISABLE ) \
| P_Fld( !MISC_CG_EN , MISC_CG_CTRL0_RG_CG_PHY_OFF_DIABLE ) \
| P_Fld( !MISC_CG_EN , MISC_CG_CTRL0_RG_CG_COMB_OFF_DISABLE ) \
@ -536,8 +527,8 @@ static void DDRPHY_PICG_Config(DRAMC_CTX_T *p)
| P_Fld( MISC_CG_EN , MISC_CG_CTRL5_R_DQ0_PI_DCM_EN ) \
| P_Fld( MISC_CG_EN , MISC_CG_CTRL5_R_CA_PI_DCM_EN ));
//defualt DCM enable, if we wanner to test CG enable, modified default CG condition.
//disable DCM.--- I think just for debug
if(MISC_CG_REVERSE_DEFAULT_ON == 1)
{
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_RX_CG_SET0) , P_Fld( 1 , RX_CG_SET0_RDATCKAR ) \
@ -565,7 +556,7 @@ static void DDRPHY_PICG_Config(DRAMC_CTX_T *p)
DramcBroadcastOnOff(DRAMC_BROADCAST_ON);
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DUTYSCAN1) , P_Fld( 1 , MISC_DUTYSCAN1_EYESCAN_DQS_OPT ));
//TODO -- for DPHY shuffle RG have to set to different Group into SRAM or not.--here just conf0 but not all frequency group
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ8) , P_Fld( 1 , SHU_B0_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B0 ) \
| P_Fld( 1 , SHU_B0_DQ8_R_RMRODTEN_CG_IG_B0 ) \
| P_Fld( 1 , SHU_B0_DQ8_R_RMRX_TOPHY_CG_IG_B0 ) \
@ -610,19 +601,19 @@ static void DDRPHY_PICG_Config(DRAMC_CTX_T *p)
static void DRAMC_COMMON_Config(DRAMC_CTX_T *p)
{
U8 RD2MRR_EXTEND_EN = 1; // for fix Samsung RD2MRR seamless error, If the samsung fix that bug, this could set 0
U8 RD2MRR_EXTEND_EN = 1;
U8 EBG_EN = 0 ;
U8 TMRRI_MODE = 1; // !!!Notice here: 0: Old Mode, 1: New Mode --- FIX NEW MODE. Pertrus not support old mode anymore
U8 TMRRI_MODE = 1;
U8 NOBLOCKALE_EN = 1;
U8 RUNTIME_MRR = 1;
//pre configuration calculate
if(TMRRI_MODE == 1)
{
NOBLOCKALE_EN = 1;
RUNTIME_MRR = 1;
} else {
//TODO
mcSHOW_DBG_MSG6(("NONBLOCKALE RUNTIMEMRR could be random.--for MP should setting 1. just record it."));
}
@ -634,7 +625,7 @@ static void DRAMC_COMMON_Config(DRAMC_CTX_T *p)
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_DDRCOMMON0) , P_Fld( 1 , DDRCOMMON0_BK8EN ) \
| P_Fld( LPDDR5_EN_S , DDRCOMMON0_LPDDR5EN ) \
| P_Fld( LPDDR4_EN_S , DDRCOMMON0_LPDDR4EN ) \
| P_Fld( 0 , DDRCOMMON0_TRCDEARLY )); //if LPDDR5 set1 HEFF mode ACT -> R/W delay-1
| P_Fld( 0 , DDRCOMMON0_TRCDEARLY ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_RX_SET0) , P_Fld( 0 , RX_SET0_DM4TO1MODE ));
@ -769,7 +760,7 @@ static void DRAMC_COMMON_Config(DRAMC_CTX_T *p)
| P_Fld( TMRRI_MODE , SCSMCTRL_SC_PG_UPD_OPT ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHUCTRL1) , P_Fld( 0x1a , SHUCTRL1_FC_PRDCNT )); //TODO
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHUCTRL1) , P_Fld( 0x1a , SHUCTRL1_FC_PRDCNT ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_DVFS_TIMING_CTRL1) , P_Fld( 1 , DVFS_TIMING_CTRL1_DMSHU_CNT ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_REFPEND1) , P_Fld( 0x5 , REFPEND1_MPENDREFCNT_TH0 ) \
| P_Fld( 0x5 , REFPEND1_MPENDREFCNT_TH1 ) \
@ -789,7 +780,7 @@ static void DRAMC_COMMON_Config(DRAMC_CTX_T *p)
{
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TX_SET0) , P_Fld( 1 , TX_SET0_OE_DOWNGRADE ));
}
//@Jouling, UI reloade path is updated. (DQSOSCR_SREF_TXUI_RELOAD_OPT)
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_DQSOSCR) , P_Fld( 0 , DQSOSCR_SREF_TXUI_RELOAD_OPT ) \
| P_Fld( 1 , DQSOSCR_SREF_TXPI_RELOAD_OPT ));
@ -805,7 +796,7 @@ static void DRAMC_COMMON_Config(DRAMC_CTX_T *p)
| P_Fld( 0 , DUMMY_RD_INTV_DUMMY_RD_CNT2 ) \
| P_Fld( 0 , DUMMY_RD_INTV_DUMMY_RD_CNT1 ) \
| P_Fld( 0 , DUMMY_RD_INTV_DUMMY_RD_CNT0 ));
//Byte Mode choose
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_RK_DQSOSC) , P_Fld( p->dram_cbt_mode[RANK_0] , RK_DQSOSC_RK0_BYTE_MODE ));
vSetRank(p, RANK_1);
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_RK_DQSOSC) , P_Fld( p->dram_cbt_mode[RANK_1] , RK_DQSOSC_RK0_BYTE_MODE ));
@ -814,7 +805,7 @@ static void DRAMC_COMMON_Config(DRAMC_CTX_T *p)
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TX_TRACKING_SET0) , P_Fld( 0 , TX_TRACKING_SET0_TX_TRACKING_OPT ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TX_CG_SET0) , P_Fld( 1 , TX_CG_SET0_SELPH_4LCG_DIS ));
//DVFS support SRAM_EN only
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TX_FREQ_RATIO_OLD_MODE0), P_Fld(DV_p.SRAM_EN, TX_FREQ_RATIO_OLD_MODE0_SHUFFLE_LEVEL_MODE_SELECT));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL1) , P_Fld( 1 , SWCMD_CTRL1_WRFIFO_MODE2 ));
@ -826,14 +817,14 @@ static void DRAMC_COMMON_Config(DRAMC_CTX_T *p)
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_RX_SET0) , P_Fld( 1 , RX_SET0_PRE_DLE_VLD_OPT ) \
| P_Fld( 7 , RX_SET0_DATLAT_PDLE_TH ));
//TODO SRAM DPM control
// @Darren, sync MP settings from Joe (APB will be available when SRAM DMA access)
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SRAM_DMA0) , P_Fld( 1 , MISC_SRAM_DMA0_PENABLE_LAT_WR ) \
| P_Fld( 1 , MISC_SRAM_DMA0_KEEP_APB_ARB_ENA ) \
| P_Fld( 1 , MISC_SRAM_DMA0_KEEP_SRAM_ARB_ENA ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_MD32_REG_SSPM_MCLK_DIV), P_Fld( 1 , SSPM_MCLK_DIV_MCLK_DCM_EN ));
//Indivial random sync
vIO32Write4B(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DBG_IRQ_CTRL1), 0xFFFFFFFF);
vIO32Write4B(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DBG_IRQ_CTRL4), 0xFFFFFFFF);
vIO32Write4B(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DBG_IRQ_CTRL7), 0xFFFFFFFF);
@ -881,8 +872,8 @@ static void IO_Release(DRAMC_CTX_T *p)
| P_Fld( 0 , B1_DQ7_RG_TX_ARDQM0_PULL_UP_B1 ) \
| P_Fld( 0 , B1_DQ7_RG_TX_ARDQ_PULL_DN_B1 ) \
| P_Fld( 0 , B1_DQ7_RG_TX_ARDQ_PULL_UP_B1 ));
//for dram spec CA_CMD2_RG_TX_ARCS_OE_TIE_EN_CA will help to fix CKE=0 before for meet 10ns tINIT2
//Assert DRAM reset PIN
#if !SA_CONFIG_EN
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CTRL1) , P_Fld( 1 , MISC_CTRL1_R_DMDA_RRESETB_I ));
#endif
@ -891,9 +882,9 @@ static void IO_Release(DRAMC_CTX_T *p)
static void DVFS_PRE_config(DRAMC_CTX_T *p)
{
#if (fcFOR_CHIP_ID == fc8195)
U32 MCP_EN = 0; //remove for MCP timing issue
U32 MCP_EN = 0;
#else
U32 MCP_EN = 1; //for MCP should adjust some setting between CHs (A-B/C-D)
U32 MCP_EN = 1;
#endif
U32 REF_104M_EN = 1;
BOOL isLP4_DSC = (p->DRAMPinmux == PINMUX_DSC)?1:0;
@ -904,21 +895,21 @@ static void DVFS_PRE_config(DRAMC_CTX_T *p)
| P_Fld( 0 , DVFS_CTRL0_DVFS_SYNC_MASK ) \
| P_Fld( 1 , DVFS_CTRL0_MR13_SHU_EN ) \
| P_Fld( 1 , DVFS_CTRL0_HWSET_WLRL ) \
| P_Fld( 0 , DVFS_CTRL0_MRWWOPRA )); //Have to fix 0, 1 with bug (some bank without precharge)
//for DVFS sync
vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DDRPHY_REG_MISC_RG_DFS_CTRL) , P_Fld( 0 , MISC_RG_DFS_CTRL_SPM_DVFS_CONTROL_SEL ));//SPM mode TODO should random 0 for SPM mode default
| P_Fld( 0 , DVFS_CTRL0_MRWWOPRA ));
vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DDRPHY_REG_MISC_RG_DFS_CTRL) , P_Fld( 0 , MISC_RG_DFS_CTRL_SPM_DVFS_CONTROL_SEL ));
vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SRAM_DMA0 ) , P_Fld( 0 , MISC_SRAM_DMA0_DMA_TIMER_EN ));
vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SRAM_DMA1 ) , P_Fld( 0x1ffff , MISC_SRAM_DMA1_SPM_RESTORE_STEP_EN ));
vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CG_CTRL7 ) , P_Fld( 1 , MISC_CG_CTRL7_ARMCTL_CK_OUT_CG_SEL ));
vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DVFSCTL ) , P_Fld( 1 , MISC_DVFSCTL_R_DVFS_PICG_POSTPONE ) \
| P_Fld( 1 , MISC_DVFSCTL_R_DMSHUFFLE_CHANGE_FREQ_OPT ));
//for channel balance
vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DVFSCTL2) , P_Fld( 0 , MISC_DVFSCTL2_R_CDC_MUX_SEL_OPTION ) \
| P_Fld( 0 , MISC_DVFSCTL2_R_DVFS_SYNC_MODULE_RST_SEL ));
//Could be randomed
vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DRAMC_REG_DVFS_CTRL0 ) , P_Fld( 0 , DVFS_CTRL0_DVFS_CKE_OPT ) \
| P_Fld( 1 , DVFS_CTRL0_SCARB_PRI_OPT ));
//here is a flow??--TODO
vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DVFSCTL3 ) , P_Fld( 1 , MISC_DVFSCTL3_RG_PHY_ST_DELAY_AFT_CHG_TO_MCLK ) \
| P_Fld( 0 , MISC_DVFSCTL3_RG_PHY_ST_DELAY_AFT_CHG_TO_BCLK ) \
| P_Fld( 0 , MISC_DVFSCTL3_RG_PHY_ST_DELAY_BEF_CHG_TO_MCLK ) \
@ -933,7 +924,7 @@ static void DVFS_PRE_config(DRAMC_CTX_T *p)
| P_Fld( 1 , MISC_CLK_CTRL_DVFS_MEM_CK_MUX_UPDATE_EN ));
vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DVFSCTL3 ) , P_Fld( 0x10 , MISC_DVFSCTL3_RG_CNT_PHY_ST_DELAY_AFT_CHG_TO_BCLK));
//flow end??
vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DRAMC_REG_DVFS_TIMING_CTRL1) , P_Fld( 1 , DVFS_TIMING_CTRL1_DMSHU_CNT )\
| P_Fld( 1 , DVFS_TIMING_CTRL1_SHU_PERIOD_GO_ZERO_CNT ));
@ -945,8 +936,8 @@ static void DVFS_PRE_config(DRAMC_CTX_T *p)
vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CKMUX_SEL ) , P_Fld( REF_104M_EN , MISC_CKMUX_SEL_RG_52M_104M_SEL ));
//notice here:
//*SHU_PHDET_SPM_EN = 1 means during DFS period as master. 2 means slave.
U32 MS_DLL_PHDET_FLD, SLV_DLL_PHDET_FLD;
if (!isLP4_DSC)
{
@ -1035,12 +1026,12 @@ void DIG_STATIC_SETTING(DRAMC_CTX_T *p)
GATING_MODE_CFG(&Gat_p);
DPHY_GAT_TRACK_Config(p,&Gat_p);
DRAMC_COMMON_Config(p);
#if 1//!SA_CONFIG_EN
DVFS_PRE_config(p);//for DVFS initial config.-- bring-up no need this code. but DVFS will need this
#if 1
DVFS_PRE_config(p);
#endif
DDRPHY_PICG_Config(p);
IO_Release(p);
RX_INTPUT_Config(p);//TODO dummy write trigger
RX_INTPUT_Config(p);
}
#if FOR_DV_SIMULATION_USED

122
src/vendorcode/mediatek/mt8195/dramc/DIG_SHUF_config.c
View File

@ -2,13 +2,7 @@
#include "dramc_dv_init.h"
//====================================
//TX CA delay configuration
//------------------------------------
//Notice:
//TX config with shuffle register with all data_rate the same
//if under real IC , need to banlance the PI/Dline calibrated result
//====================================
static void DIG_CONFIG_SHUF_ALG_TXCA(DRAMC_CTX_T *p, int ch_id, int group_id)
{
mcSHOW_DBG_MSG6(("[DIG_FREQ_CONFIG][TX_CA][Delay] ch_id:%2d, group_id:%2d >>>>>\n", ch_id, group_id));
@ -17,7 +11,7 @@ static void DIG_CONFIG_SHUF_ALG_TXCA(DRAMC_CTX_T *p, int ch_id, int group_id)
u8 backup_ShuRGAccessIdx = p->ShuRGAccessIdx;
u8 TX_UI;
TX_UI = (DFS(group_id)->data_rate<=800) ? 1: 0 ; //TODO -- LPDDR5 need confirm
TX_UI = (DFS(group_id)->data_rate<=800) ? 1: 0 ;
vSetPHY2ChannelMapping(p, ch_id);
@ -93,18 +87,12 @@ static void DIG_CONFIG_SHUF_ALG_TXCA(DRAMC_CTX_T *p, int ch_id, int group_id)
mcSHOW_DBG_MSG6(("[DIG_FREQ_CONFIG][TX_CA][Delay] ch_id:%2d, group_id:%2d <<<<<\n", ch_id, group_id));
}
//====================================
//Impdance configuration
//------------------------------------
//Notice:
//ANA result depend on calibration
//====================================
static void DIG_CONFIG_SHUF_IMP(DRAMC_CTX_T *p, int ch_id, int group_id)
{
mcSHOW_DBG_MSG6(("[DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id:%2d, group_id:%2d >>>>>\n", ch_id, group_id));
U8 IPM_ODT_EN;
U8 CHKCYCLE = 7; //200ns algrith --TODO, @Darren, fix hw imp tracking
U8 TXDLY_CMD = 8; //Need algrithm support .. RL . TODO
U8 CHKCYCLE = 7;
U8 TXDLY_CMD = 8;
U8 backup_ch_id = p->channel;
u8 backup_ShuRGAccessIdx = p->ShuRGAccessIdx;
vSetPHY2ChannelMapping(p, ch_id);
@ -134,18 +122,13 @@ static void DIG_CONFIG_SHUF_IMP(DRAMC_CTX_T *p, int ch_id, int group_id)
mcSHOW_DBG_MSG6(("[DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id:%2d, group_id:%2d <<<<<\n", ch_id, group_id));
}
//====================================
//RX input delay configuration by mode choose
//------------------------------------
//Notice:
//
//====================================
static void DIG_CONFIG_SHUF_RXINPUT(DRAMC_CTX_T *p, int ch_id, int group_id)
{
U8 PERBYTE_TRACK_EN = 1;//TODO
U8 DQM_TRACK_EN = 0;//TODO --following RD DBI
U8 DQM_FLOW_DQ_SEL = 3;//TODO
U8 RX_force_upd = 0;//TODO
U8 PERBYTE_TRACK_EN = 1;
U8 DQM_TRACK_EN = 0;
U8 DQM_FLOW_DQ_SEL = 3;
U8 RX_force_upd = 0;
U8 backup_ch_id = p->channel;
u8 backup_ShuRGAccessIdx = p->ShuRGAccessIdx;
@ -206,20 +189,14 @@ static void WDQSMode2TxDQOE_CNT(DRAMC_CTX_T *p, U8 *u1DQOE_CNT)
}
#endif
//====================================
// MISC shuffle register fit
//------------------------------------
//Notice:
// MISC shuffle reigster should be fixed
//====================================
static void DIG_CONFIG_SHUF_MISC_FIX(DRAMC_CTX_T *p,U32 ch_id, U32 group_id)
{
U8 PICG_MODE = 1;
U8 LP5_HEFF = 0;//TODO
U8 LP5WRAPEN = 1;//Could random 1bit
U8 LP5_HEFF = 0;
U8 LP5WRAPEN = 1;
U8 DQSIEN_DQSSTB_MODE=0;
U8 irank = 0;
U8 LP5_CASMODE = 1; //TODO Impact AC timing 1,2,3 three mode support 1:Low Power; 2:Low Freq; 3:High Eff;
U8 LP5_CASMODE = 1;
U8 WCKDUAL = 0;
U8 NEW_RANK_MODE = 1;
U8 DUALSCHEN = 1;
@ -274,7 +251,7 @@ static void DIG_CONFIG_SHUF_MISC_FIX(DRAMC_CTX_T *p,U32 ch_id, U32 group_id)
| P_Fld( (A_D->DQ_P2S_RATIO==8) , SHU_COMMON0_FREQDIV4 ) \
| P_Fld( (A_D->DQ_P2S_RATIO==4) , SHU_COMMON0_FDIV2 ) \
| P_Fld( LPDDR4_EN_S , SHU_COMMON0_BC4OTF ) \
| P_Fld( !(A_D->DQ_P2S_RATIO==4) , SHU_COMMON0_DM64BITEN ));//TODO
| P_Fld( !(A_D->DQ_P2S_RATIO==4) , SHU_COMMON0_DM64BITEN ));
if(LPDDR5_EN_S == 1)
{
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_COMMON0) , P_Fld( (A_D->DQ_P2S_RATIO==16) , SHU_COMMON0_FREQDIV8 ) \
@ -285,8 +262,8 @@ static void DIG_CONFIG_SHUF_MISC_FIX(DRAMC_CTX_T *p,U32 ch_id, U32 group_id)
| P_Fld( LP5WRAPEN , SHU_COMMON0_LP5WRAPEN ) \
| P_Fld( LP5_HEFF , SHU_COMMON0_LP5HEFF_MODE ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_WCKCTRL) , P_Fld( WCKDUAL , SHU_WCKCTRL_WCKDUAL ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_WCKCTRL_1) , P_Fld( (A_D->CKR==2) , SHU_WCKCTRL_1_WCKSYNC_PRE_MODE));//TODO
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_LP5_CMD) , P_Fld( (A_D->CA_P2S_RATIO==2) , SHU_LP5_CMD_LP5_CMD1TO2EN ));//TODO
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_WCKCTRL_1) , P_Fld( (A_D->CKR==2) , SHU_WCKCTRL_1_WCKSYNC_PRE_MODE));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_LP5_CMD) , P_Fld( (A_D->CA_P2S_RATIO==2) , SHU_LP5_CMD_LP5_CMD1TO2EN ));
}
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_ACTIMING_CONF), P_Fld( 1 , SHU_ACTIMING_CONF_TREFBWIG ) \
@ -300,24 +277,24 @@ static void DIG_CONFIG_SHUF_MISC_FIX(DRAMC_CTX_T *p,U32 ch_id, U32 group_id)
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_MATYPE) , P_Fld( 2 , SHU_MATYPE_MATYPE ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_SCHEDULER) , P_Fld( DUALSCHEN , SHU_SCHEDULER_DUALSCHEN ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TX_SET0) , P_Fld( 1 , TX_SET0_WPRE2T ));
//TODO SHU_TX_SET0_WPST1P5T OVER3200 DRAM spec need 1 but in TBA should random
//OE_EXT2UI strange rule.--TODO
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_TX_SET0) , P_Fld( (A_D->DQ_P2S_RATIO==4) , SHU_TX_SET0_WDATRGO ) \
| P_Fld( (DFS(group_id)->data_rate>=3200) , SHU_TX_SET0_WPST1P5T ) \
| P_Fld( DQOE_OPT , SHU_TX_SET0_DQOE_OPT ) \
| P_Fld( DQOE_CNT , SHU_TX_SET0_DQOE_CNT ) \
| P_Fld( LPDDR5_EN_S , SHU_TX_SET0_OE_EXT2UI ) \
| P_Fld( ((DFS(group_id)->data_rate==1600) && (A_D->DQ_P2S_RATIO==8))?5:2, SHU_TX_SET0_TXUPD_W2R_SEL )); //TODO
| P_Fld( ((DFS(group_id)->data_rate==1600) && (A_D->DQ_P2S_RATIO==8))?5:2, SHU_TX_SET0_TXUPD_W2R_SEL ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_STBCAL1), P_Fld( 0x30 , MISC_SHU_STBCAL1_STB_PI_TRACKING_RATIO) \
| P_Fld( 1 , MISC_SHU_STBCAL1_STB_UPDMASK_EN ) \
| P_Fld( 9 , MISC_SHU_STBCAL1_STB_UPDMASKCYC ) \
| P_Fld( (DFS(group_id)->data_rate > 1600) , MISC_SHU_STBCAL1_DQSINCTL_PRE_SEL)); //TODO
| P_Fld( (DFS(group_id)->data_rate > 1600) , MISC_SHU_STBCAL1_DQSINCTL_PRE_SEL));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_STBCAL) , P_Fld( Gat_p.GAT_TRACK_EN , MISC_SHU_STBCAL_STBCALEN ) \
| P_Fld( Gat_p.GAT_TRACK_EN , MISC_SHU_STBCAL_STB_SELPHCALEN ) \
| P_Fld( DQSIEN_DQSSTB_MODE , MISC_SHU_STBCAL_DQSIEN_DQSSTB_MODE)); //TODO
| P_Fld( DQSIEN_DQSSTB_MODE , MISC_SHU_STBCAL_DQSIEN_DQSSTB_MODE));
//@Darren, NOTE: Fix gating error or fifo mismatch => DMSTBLAT date_rate=1866 >= 3 : 1
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_STBCAL) , P_Fld( (((Gat_p.GAT_TRACK_EN)&&(DFS(group_id)->data_rate>=1866))?(2+Gat_p.VALID_LAT_VALUE):(0+Gat_p.VALID_LAT_VALUE)) , MISC_SHU_STBCAL_DMSTBLAT ) \
| P_Fld( 1 , MISC_SHU_STBCAL_PICGLAT ) \
| P_Fld( 1 , MISC_SHU_STBCAL_DQSG_MODE ) \
@ -333,7 +310,7 @@ static void DIG_CONFIG_SHUF_MISC_FIX(DRAMC_CTX_T *p,U32 ch_id, U32 group_id)
}
vSetRank(p, backup_rank);
//RODT offset TODO
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_RODTENSTB), P_Fld( 1 , MISC_SHU_RODTENSTB_RODTENSTB_TRACK_EN ) \
| P_Fld( 0 , MISC_SHU_RODTENSTB_RODTEN_P1_ENABLE ) \
| P_Fld( (NEW_RANK_MODE)?1:PICG_MODE , MISC_SHU_RODTENSTB_RODTENSTB_SELPH_MODE ) \
@ -342,8 +319,8 @@ static void DIG_CONFIG_SHUF_MISC_FIX(DRAMC_CTX_T *p,U32 ch_id, U32 group_id)
| P_Fld( ((A_D->DQ_P2S_RATIO == 4)?1:4) , MISC_SHU_RODTENSTB_RODTENSTB__UI_OFFSET ) \
| P_Fld( ((A_D->DQ_P2S_RATIO == 16)?19:((A_D->DQ_P2S_RATIO == 8)?13:10)) , MISC_SHU_RODTENSTB_RODTENSTB_EXT ));
//[SV] //SHL, fix RODT rd_period low 1T issue
// @Darren, confirm MP settings w/ Chau-Wei Wang (Jason)
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_RODTENSTB1), P_Fld( ((DFS(group_id)->data_rate >=3200)?1:0) , MISC_SHU_RODTENSTB1_RODTENCGEN_TAIL ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_RODTENSTB1), P_Fld( ((DFS(group_id)->data_rate >=3200)?2:1) , MISC_SHU_RODTENSTB1_RODTENCGEN_HEAD ));
@ -397,26 +374,26 @@ static void DIG_CONFIG_SHUF_DQSGRETRY(DRAMC_CTX_T *p, int ch_id, int group_id)
mcSHOW_DBG_MSG6(("[DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id=%2d \n", group_id));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_DQSG_RETRY1), P_Fld( 0 , MISC_SHU_DQSG_RETRY1_RETRY_SW_RESET ) \
| P_Fld( 0 , MISC_SHU_DQSG_RETRY1_RETRY_SW_EN ) \
| P_Fld( 0 /*@Jimmy, sync MP settings by YT*/ , MISC_SHU_DQSG_RETRY1_RETRY_DDR1866_PLUS ) \
| P_Fld( 0 , MISC_SHU_DQSG_RETRY1_RETRY_DDR1866_PLUS ) \
| P_Fld( 0 , MISC_SHU_DQSG_RETRY1_RETRY_ONCE ) \
| P_Fld( 0 /*@Jimmy, sync MP settings by YT*/ , MISC_SHU_DQSG_RETRY1_RETRY_3TIMES ) \
| P_Fld( 0 , MISC_SHU_DQSG_RETRY1_RETRY_3TIMES ) \
| P_Fld( 0 , MISC_SHU_DQSG_RETRY1_RETRY_1RANK ) \
| P_Fld( 0 /*@Jimmy, sync MP settings by YT*/ , MISC_SHU_DQSG_RETRY1_RETRY_BY_RANK ) \
| P_Fld( 0 , MISC_SHU_DQSG_RETRY1_RETRY_BY_RANK ) \
| P_Fld( 0 , MISC_SHU_DQSG_RETRY1_RETRY_DM4BYTE ) \
| P_Fld( 0 , MISC_SHU_DQSG_RETRY1_RETRY_DQSIENLAT ) \
| P_Fld( 0 , MISC_SHU_DQSG_RETRY1_RETRY_STBENCMP_ALLBYTE) \
| P_Fld( 0 , MISC_SHU_DQSG_RETRY1_XSR_DQSG_RETRY_EN ) \
| P_Fld( 0 /*@Darren, sync MP settings by YT (DFS(group_id)->data_rate>=3733)*/ , MISC_SHU_DQSG_RETRY1_XSR_RETRY_SPM_MODE ) \
| P_Fld( 0 , MISC_SHU_DQSG_RETRY1_XSR_RETRY_SPM_MODE ) \
| P_Fld( 0 , MISC_SHU_DQSG_RETRY1_RETRY_CMP_DATA ) \
| P_Fld( 0 , MISC_SHU_DQSG_RETRY1_RETRY_ALE_BLOCK_MASK ) \
| P_Fld( 0 /*@Jimmy, sync MP settings by YT*/ , MISC_SHU_DQSG_RETRY1_RETRY_RDY_SEL_DLE ) \
| P_Fld( 0 /*@Jimmy, sync MP settings by YT*/ , MISC_SHU_DQSG_RETRY1_RETRY_USE_NON_EXTEND ) \
| P_Fld( 0 /*@Jimmy, sync MP settings by YT*/ , MISC_SHU_DQSG_RETRY1_RETRY_USE_CG_GATING ) \
| P_Fld( 0 /*@Jimmy, sync MP settings by YT*/ , MISC_SHU_DQSG_RETRY1_RETRY_ROUND_NUM ) \
| P_Fld( 0 , MISC_SHU_DQSG_RETRY1_RETRY_RDY_SEL_DLE ) \
| P_Fld( 0 , MISC_SHU_DQSG_RETRY1_RETRY_USE_NON_EXTEND ) \
| P_Fld( 0 , MISC_SHU_DQSG_RETRY1_RETRY_USE_CG_GATING ) \
| P_Fld( 0 , MISC_SHU_DQSG_RETRY1_RETRY_ROUND_NUM ) \
| P_Fld( 0 , MISC_SHU_DQSG_RETRY1_RETRY_RANKSEL_FROM_PHY) \
| P_Fld( 0 , MISC_SHU_DQSG_RETRY1_RETRY_PA_DISABLE ) \
| P_Fld( 0 , MISC_SHU_DQSG_RETRY1_RETRY_STBEN_RESET_MSK ) \
| P_Fld( 0 /*@Jimmy, sync MP settings by YT*/ , MISC_SHU_DQSG_RETRY1_RETRY_USE_BURST_MODE ));
| P_Fld( 0 , MISC_SHU_DQSG_RETRY1_RETRY_USE_BURST_MODE ));
vSetPHY2ChannelMapping(p, backup_ch_id);
p->ShuRGAccessIdx = backup_ShuRGAccessIdx;
@ -425,8 +402,8 @@ static void DIG_CONFIG_SHUF_DQSGRETRY(DRAMC_CTX_T *p, int ch_id, int group_id)
static void DIG_CONFIG_SHUF_DBI(DRAMC_CTX_T *p, int ch_id, int group_id)
{
U8 RD_DBI_EN = 1;//TODO
U8 WR_DBI_EN = 1;//TODO
U8 RD_DBI_EN = 1;
U8 WR_DBI_EN = 1;
U8 backup_ch_id = p->channel;
u8 backup_ShuRGAccessIdx = p->ShuRGAccessIdx;
@ -456,7 +433,7 @@ static void DIG_CONFIG_SHUF_DBI(DRAMC_CTX_T *p, int ch_id, int group_id)
mcSHOW_DBG_MSG6(("[DIG_SHUF_CONFIG] DBI <<<<<<, group_id=%2d \n", group_id));
}
//TODO LPDDR5
static void DIG_CONFIG_SHUF_DVFSWLRL(DRAMC_CTX_T *p, int ch_id, int group_id)
{
U8 backup_ch_id = p->channel;
@ -476,7 +453,7 @@ static void DIG_CONFIG_SHUF_DVFSWLRL(DRAMC_CTX_T *p, int ch_id, int group_id)
LP4_DRAM_config (DFS(group_id)->data_rate,&LP4_temp);
HWSET_MR13_OP_Value = ((LP4_temp.WORK_FSP & 1) << 7) | ((LP4_temp.WORK_FSP & 1) << 6) | (( 0 << 5) | 8); //DMI default enable
HWSET_MR13_OP_Value = ((LP4_temp.WORK_FSP & 1) << 7) | ((LP4_temp.WORK_FSP & 1) << 6) | (( 0 << 5) | 8);
HWSET_VRCG_OP_Value = ((LP4_temp.WORK_FSP & 1) << 7) | ((LP4_temp.WORK_FSP & 1) << 6);
HWSET_MR2_OP_Value = ((LP4_temp.MR_WL & 7) << 3) | (LP4_temp.MR_WL & 7);
} else {
@ -494,13 +471,6 @@ static void DIG_CONFIG_SHUF_DVFSWLRL(DRAMC_CTX_T *p, int ch_id, int group_id)
}
//=================================================
//Jump ratio calculate and setting
//------------------------------------------------
//notice: 400 800 not support tracking TODO
// should confirm it with DQ_SEMI_OPEN =1 or not but not data_rate as condition
//
//================================================
#if 0
void TX_RX_jumpratio_calculate(DRAMC_CTX_T *p,int ch_id,int group_id)
{
@ -515,19 +485,17 @@ void TX_RX_jumpratio_calculate(DRAMC_CTX_T *p,int ch_id,int group_id)
mcSHOW_DBG_MSG(("[TX_RX_jumpratio_calculate]>>>>>>>> group_id = %1d",group_id));
for(tar = 0; tar<DFS_GROUP_NUM;tar++)
{
if(((DFS(group_id)->data_rate == 800) || (DFS(group_id)->data_rate == 400)) || ((DFS(tar)->data_rate == 800) || (DFS(tar)->data_rate == 400))) //TODO wihtout tracking
if(((DFS(group_id)->data_rate == 800) || (DFS(group_id)->data_rate == 400)) || ((DFS(tar)->data_rate == 800) || (DFS(tar)->data_rate == 400)))
{
result[tar] = 0;
}
else
{
result[tar] = (int)(((float)(DFS(tar)->data_rate) * (float)ratio) / (float)(DFS(group_id)->data_rate) + 0.5); //+0.5 for roundup
result[tar] = (int)(((float)(DFS(tar)->data_rate) * (float)ratio) / (float)(DFS(group_id)->data_rate) + 0.5);
}
mcSHOW_DBG_MSG(("\n[TXRX_jumpratio]current_group data_rate=%1d,tar_data_rate=%1d,jumpratio=%1d;\n",DFS(group_id)->data_rate,DFS(tar)->data_rate,result[tar]));
}
//=============================
//setting
//=============================
p->ShuRGAccessIdx = (group_id == 0) ? DRAM_DFS_REG_SHU0 : DRAM_DFS_REG_SHU1;
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_FREQ_RATIO_SET0), P_Fld( result[0] , SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO0) \
@ -557,12 +525,6 @@ static void DIG_CONFIG_DVFS_DEPENDENCE(DRAMC_CTX_T *p,U32 ch_id, U32 group_id)
| P_Fld( 0 , MISC_SHU_DVFSDLL_R_BYPASS_2ND_DLL ));
}
//====================================
// Digital shuffle configuration entry
//------------------------------------
//Notice:
//
//====================================
void DIG_CONFIG_SHUF(DRAMC_CTX_T *p,U32 ch_id, U32 group_id)
{
DIG_CONFIG_SHUF_ALG_TXCA(p,ch_id,group_id);
@ -581,12 +543,12 @@ static void OTHER_GP_INIT(DRAMC_CTX_T *p,U32 ch_id, U32 group_id)
U8 backup_ch_id = p->channel;
U8 backup_ShuRGAccessIdx = p->ShuRGAccessIdx;
//notice here. Replace the A_D A_T with new frequency auto-generation
ANA_TOP_FUNCTION_CFG(A_T,DFS(group_id)->data_rate);
ANA_CLK_DIV_config(A_D,DFS(group_id));
p->ShuRGAccessIdx = (group_id == 0) ? DRAM_DFS_REG_SHU0 : DRAM_DFS_REG_SHU1;
ANA_sequence_shuffle_colletion(p,A_D);//these RG will be set during flow,but for DV another GP should be set directly
ANA_sequence_shuffle_colletion(p,A_D);
ANA_Config_shuffle(p,A_T,group_id);
DIG_CONFIG_SHUF(p,ch_id,group_id);
vSetPHY2ChannelMapping(p, backup_ch_id);

71
src/vendorcode/mediatek/mt8195/dramc/DRAMC_SUBSYS_config.c
View File

@ -13,11 +13,6 @@ DRAMC_SUBSYS_CONFIG_T DV_p;
void ANA_TOP_FUNCTION_CFG(ANA_top_config_T *tr,U16 data_rate)
{
// tr-> DLL_ASYNC_EN = 0 ; //from DV random
// tr-> NEW_RANK_MODE = 1 ; //from DV random
// tr-> DLL_IDLE_MODE = 1 ; //from DV random
// tr-> LP45_APHY_COMB_EN= 1 ; //from DV define
// tr-> NEW_8X_MODE = 1 ;
tr->ALL_SLAVE_EN = (data_rate <= 1866)?1:0;
@ -46,22 +41,22 @@ void ANA_TOP_FUNCTION_CFG(ANA_top_config_T *tr,U16 data_rate)
void ANA_CLK_DIV_config( ANA_DVFS_CORE_T *tr,DRAMC_DVFS_GROUP_CONFIG_T *dfs)
{
U32 SEMI_OPEN_FMIN = 300;
U32 SEMI_OPEN_FMAX = 500; //lp4 600
U32 SEMI_OPEN_FMAX = 500;
U32 PI_FMIN = 600;
U32 DQ_PICK;
U32 CA_PICK; //U
U32 CA_MCKIO; //S
U32 MCKIO_SEMI; //Q
U32 CA_PICK;
U32 CA_MCKIO;
U32 MCKIO_SEMI;
U16 data_rate;
data_rate = dfs->data_rate;
tr->DQ_P2S_RATIO = dfs->DQ_P2S_RATIO;
tr->CKR = dfs->CKR;
//tr->CA_P2S_RATIO
tr->CA_P2S_RATIO = tr->DQ_P2S_RATIO/tr->CKR;
//tr->DQ_CA_OPEN
tr->DQ_CA_OPEN = ( data_rate < (SEMI_OPEN_FMIN * 2) ) ? 1 : 0;
tr->DQ_SEMI_OPEN = ( data_rate/2 < PI_FMIN ) ? (1-tr->DQ_CA_OPEN) : ((data_rate <= SEMI_OPEN_FMAX*2) ? (1-tr->DQ_CA_OPEN) : 0);
tr->CA_SEMI_OPEN = (( data_rate/(tr->CKR*2) < PI_FMIN ) ? ((data_rate/(tr->CKR*2) > SEMI_OPEN_FMAX) ? 0 : (((tr->CA_P2S_RATIO>2)||(tr->DQ_SEMI_OPEN))*(1-tr->DQ_CA_OPEN))) : tr->DQ_SEMI_OPEN);
@ -79,7 +74,7 @@ void ANA_CLK_DIV_config( ANA_DVFS_CORE_T *tr,DRAMC_DVFS_GROUP_CONFIG_T *dfs)
#if SA_CONFIG_EN
if(LPDDR4_EN_S)
{
// @Darren, for LP4 8PH Delay
if (data_rate <= 1866)
tr->PH8_DLY = 0;
else if (data_rate <= 2400)
@ -99,28 +94,28 @@ void ANA_CLK_DIV_config( ANA_DVFS_CORE_T *tr,DRAMC_DVFS_GROUP_CONFIG_T *dfs)
MCKIO_SEMI = (tr->DQ_SEMI_OPEN * tr->CA_SEMI_OPEN * (data_rate/2)) + (1-tr->DQ_SEMI_OPEN) * tr->CA_SEMI_OPEN * CA_MCKIO;
tr->SEMI_OPEN_CA_PICK_MCK_RATIO = ( MCKIO_SEMI == 0) ? DONT_CARE_VALUE : (CA_PICK*tr->DQ_P2S_RATIO)/data_rate ; //need to be improved
tr->SEMI_OPEN_CA_PICK_MCK_RATIO = ( MCKIO_SEMI == 0) ? DONT_CARE_VALUE : (CA_PICK*tr->DQ_P2S_RATIO)/data_rate ;
tr->DQ_AAMCK_DIV = (tr->DQ_SEMI_OPEN == 0) ? ((tr->DQ_P2S_RATIO/2)*(1-tr->DQ_SEMI_OPEN)) : DONT_CARE_VALUE;
tr->CA_AAMCK_DIV = (tr->CA_SEMI_OPEN == 0) ? ((tr->DQ_P2S_RATIO/(2*tr->CKR))*(1+tr->CA_FULL_RATE)) : DONT_CARE_VALUE;
tr->CA_ADMCK_DIV = CA_PICK/(data_rate/tr->DQ_P2S_RATIO); //need to be improved
//tr->DQ_TRACK_CA_EN = ((data_rate/2) >= 2133) ? 1 : 0 ; //for Alucary confirm that 'interface timing' sign NOT OK.
tr->CA_ADMCK_DIV = CA_PICK/(data_rate/tr->DQ_P2S_RATIO);
//tr->DQ_TRACK_CA_EN = ((data_rate/2) >= 2133) ? 1 : 0 ;
tr->DQ_TRACK_CA_EN = 0 ;
tr->PLL_FREQ = ((DQ_PICK*2*(tr->DQ_CKDIV4_EN+1)) > (CA_PICK*2*(tr->CA_CKDIV4_EN+1))) ? (DQ_PICK*2*(tr->DQ_CKDIV4_EN+1)) : (CA_PICK*2*(tr->CA_CKDIV4_EN+1));
#if SA_CONFIG_EN
//de-sense
if(data_rate==2400)
tr->PLL_FREQ = 2366; //DDR2366
tr->PLL_FREQ = 2366;
else if(data_rate==1200)
tr->PLL_FREQ = 2288; //DDR1144
tr->PLL_FREQ = 2288;
else if(data_rate==3200 || data_rate==1600)
tr->PLL_FREQ = 3068; //DDR3068 DDR1534
tr->PLL_FREQ = 3068;
else if(data_rate==800)
tr->PLL_FREQ = 3016; //DDR754
tr->PLL_FREQ = 3016;
else if(data_rate==400)
tr->PLL_FREQ = 1600; //DDR400 1600/div4
tr->PLL_FREQ = 1600;
#endif
tr->DQ_UI_PI_RATIO = 32; //TODO:notice here. infact if DQ_SEMI_OPEM == 1 UI_PI_RATIO will only 4 lower 2bit wihtout use
tr->DQ_UI_PI_RATIO = 32;
tr->CA_UI_PI_RATIO = (tr->CA_SEMI_OPEN == 0) ? ((tr->CA_FULL_RATE == 1)? 64 : DONT_CARE_VALUE) : 32;
mcSHOW_DBG_MSG6(("=================================== \n"));
@ -211,17 +206,17 @@ void DRAMC_SUBSYS_PRE_CONFIG(DRAMC_CTX_T *p, DRAMC_SUBSYS_CONFIG_T *tr)
tr->lp4_init->EX_ROW_EN[1] = p->u110GBEn[RANK_1] ;
tr->lp4_init->BYTE_MODE[0] = 0 ;
tr->lp4_init->BYTE_MODE[1] = 0 ;
tr->lp4_init->LP4Y_EN = 0;//DUT_p.LP4Y_EN ;
tr->lp4_init->WR_PST = 1;//DUT_p.LP4_WR_PST ;
tr->lp4_init->OTF = 1;//DUT_p.LP4_OTF ;
tr->a_cfg->NEW_8X_MODE = 1;//DUT_p.NEW_8X_MODE ;
tr->lp4_init->LP4Y_EN = 0;
tr->lp4_init->WR_PST = 1;
tr->lp4_init->OTF = 1;
tr->a_cfg->NEW_8X_MODE = 1;
tr->a_cfg->LP45_APHY_COMB_EN = 1 ;
tr->a_cfg->DLL_IDLE_MODE = 1;//DUT_p.DLL_IDLE_MODE ;
tr->a_cfg->NEW_RANK_MODE = 1;//DUT_p.NEW_RANK_MODE ;
tr->a_cfg->DLL_ASYNC_EN = 0;//DUT_p.DLL_ASYNC_EN ;
tr->MD32_EN = 0;//DUT_p.MD32_EN ;
tr->SRAM_EN = 1;//DUT_p.SRAM_EN ;
tr->GP_NUM = 10;//DUT_p.GP_NUM ;
tr->a_cfg->DLL_IDLE_MODE = 1;
tr->a_cfg->NEW_RANK_MODE = 1;
tr->a_cfg->DLL_ASYNC_EN = 0;
tr->MD32_EN = 0;
tr->SRAM_EN = 1;
tr->GP_NUM = 10;
if(p->freq_sel==LP4_DDR4266)
{
@ -261,22 +256,12 @@ void DRAMC_SUBSYS_PRE_CONFIG(DRAMC_CTX_T *p, DRAMC_SUBSYS_CONFIG_T *tr)
}
#endif
//==============================================
//Oterwise, SA should rebuild Top configuration.
//==============================================
LP4_DRAM_config(tr->DFS_GP[0]->data_rate,tr->lp4_init);
}
//TODO for LPDDR5
//data_rate DQ_P2S_RATIO
//[4800:6400] 16
//[1600:4800) 8
//[400 :1600] 4
//=========================
//data_rate CKR
//[3733:6400] 4
//[400 :3733) 2
ANA_TOP_FUNCTION_CFG(tr->a_cfg,tr->DFS_GP[0]->data_rate);
ANA_CLK_DIV_config(tr->a_opt,tr->DFS_GP[0]);

22
src/vendorcode/mediatek/mt8195/dramc/DRAM_config_collctioin.c
View File

@ -2,18 +2,18 @@
#include "dramc_dv_init.h"
//DRAM LP4 initial configuration
void LP4_DRAM_config(U32 data_rate, LP4_DRAM_CONFIG_T *tr)
{
tr->BYTE_MODE[0] = 0;//TODO
tr->BYTE_MODE[1] = 0;//TODO
#if 0 // @Darren, remove it
tr->BYTE_MODE[0] = 0;
tr->BYTE_MODE[1] = 0;
#if 0
#if SA_CONFIG_EN
tr->EX_ROW_EN[0] = 0;//TODO
tr->EX_ROW_EN[1] = 0;//TODO
tr->EX_ROW_EN[0] = 0;
tr->EX_ROW_EN[1] = 0;
#else
tr->EX_ROW_EN[0] = 1;//TODO
tr->EX_ROW_EN[1] = 0;//TODO
tr->EX_ROW_EN[0] = 1;
tr->EX_ROW_EN[1] = 0;
#endif
#endif
tr->MR_WL = LP4_DRAM_INIT_RLWL_MRfield_config(data_rate);
@ -22,7 +22,7 @@ void LP4_DRAM_config(U32 data_rate, LP4_DRAM_CONFIG_T *tr)
tr->RPST = 0;
tr->RD_PRE = 0;
tr->WR_PRE = 1;
tr->WR_PST = (data_rate>=2667)?1:0; //TODO
tr->WR_PST = (data_rate>=2667)?1:0;
#if SA_CONFIG_EN
tr->DBI_WR = 0;
tr->DBI_RD = 0;
@ -33,7 +33,7 @@ void LP4_DRAM_config(U32 data_rate, LP4_DRAM_CONFIG_T *tr)
// tr->DMI = 1;
tr->OTF = 1;
#if (ENABLE_LP4Y_DFS && LP4Y_BACKUP_SOLUTION)
tr->LP4Y_EN = (data_rate>=1866)?0:1; //TODO, @Darren for LP4Y
tr->LP4Y_EN = (data_rate>=1866)?0:1;
#else
tr->LP4Y_EN = 0;
#endif
@ -60,7 +60,7 @@ void LP4_DRAM_config(U32 data_rate, LP4_DRAM_CONFIG_T *tr)
mcSHOW_DBG_MSG2(("OTF = 0x%1x\n",tr->OTF ));
mcSHOW_DBG_MSG2(("=================================== \n"));
}
//LP4 dram initial ModeRegister setting
U8 LP4_DRAM_INIT_RLWL_MRfield_config(U32 data_rate)
{
U8 MR2_RLWL;

121
src/vendorcode/mediatek/mt8195/dramc/Hal_io.c
View File

@ -25,12 +25,12 @@ U32 u4RegBaseAddrTraslate(DRAM_DFS_REG_SHU_T eShu, DRAM_RANK_T eRank, U32 u4reg_
return u4reg_addr;
}
if (u4RegType >= 2 && u4RegType <= 3)// ChA/B Dramc AO Register
if (u4RegType >= 2 && u4RegType <= 3)
{
if (u4Offset < DRAMC_REG_AO_SHUFFLE0_BASE_ADDR || u4Offset > DRAMC_REG_AO_SHUFFLE0_END_ADDR)
eShu = 0;
}
else if (u4RegType >= 6 && u4RegType <= 7)// ChA/B Dramc AO Register
else if (u4RegType >= 6 && u4RegType <= 7)
{
if (u4Offset < DDRPHY_AO_SHUFFLE0_BASE_ADDR || u4Offset > DDRPHY_AO_SHUFFLE0_END_ADDR)
eShu = 0;
@ -38,7 +38,7 @@ U32 u4RegBaseAddrTraslate(DRAM_DFS_REG_SHU_T eShu, DRAM_RANK_T eRank, U32 u4reg_
if (eRank == RANK_1)
{
if (u4RegType >= 2 && u4RegType <= 3)// ChA/B Dramc AO Register
if (u4RegType >= 2 && u4RegType <= 3)
{
if (u4Offset >= DRAMC_REG_AO_RANK0_WO_SHUFFLE_BASE_ADDR &&
u4Offset <= DRAMC_REG_AO_RANK0_WO_SHUFFLE_END_ADDR)
@ -51,52 +51,52 @@ U32 u4RegBaseAddrTraslate(DRAM_DFS_REG_SHU_T eShu, DRAM_RANK_T eRank, U32 u4reg_
u4Offset += DRAMC_REG_AO_RANK_OFFSET;
}
}
else if (u4RegType >= 6 && u4RegType <= 7)// PhyA/B AO Register
else if (u4RegType >= 6 && u4RegType <= 7)
{
// 0x60~0xE0
if (u4Offset >= DDRPHY_AO_RANK0_B0_NON_SHU_BASE_ADDR &&
u4Offset <= DDRPHY_AO_RANK0_B0_NON_SHU_END_ADDR)
{
u4Offset += DDRPHY_AO_RANK_OFFSET;
}
// 0x1E0~0x260
else if (u4Offset >= DDRPHY_AO_RANK0_B1_NON_SHU_BASE_ADDR &&
u4Offset <= DDRPHY_AO_RANK0_B1_NON_SHU_END_ADDR)
{
u4Offset += DDRPHY_AO_RANK_OFFSET;
}
// 0x360~0x3E0
else if (u4Offset >= DDRPHY_AO_RANK0_CA_NON_SHU_BASE_ADDR &&
u4Offset <= DDRPHY_AO_RANK0_CA_NON_SHU_END_ADDR)
{
u4Offset += DDRPHY_AO_RANK_OFFSET;
}
// 0x760~0x7E0
else if (u4Offset >= DDRPHY_AO_RANK0_B0_SHU0_BASE_ADDR &&
u4Offset <= DDRPHY_AO_RANK0_B0_SHU0_END_ADDR)
{
u4Offset += DDRPHY_AO_RANK_OFFSET;
}
// 0x8E0~0x960
else if (u4Offset >= DDRPHY_AO_RANK0_B1_SHU0_BASE_ADDR &&
u4Offset <= DDRPHY_AO_RANK0_B1_SHU0_END_ADDR)
{
u4Offset += DDRPHY_AO_RANK_OFFSET;
}
// 0xA60~0xAE0
else if (u4Offset >= DDRPHY_AO_RANK0_CA_SHU0_BASE_ADDR &&
u4Offset <= DDRPHY_AO_RANK0_CA_SHU0_END_ADDR)
{
u4Offset += DDRPHY_AO_RANK_OFFSET;
}
// 0xBE0~0xC60
else if (u4Offset >= DDRPHY_AO_RANK0_MISC_SHU0_BASE_ADDR &&
u4Offset <= DDRPHY_AO_RANK0_MISC_SHU0_END_ADDR)
{
u4Offset += DDRPHY_AO_RANK_OFFSET;
}
}
else if (u4RegType <= 1)// ChA/B Dramc NAO Register
else if (u4RegType <= 1)
{
if (u4Offset >= (DRAMC_REG_RK0_DQSOSC_STATUS - DRAMC_NAO_BASE_ADDRESS) &&
u4Offset < (DRAMC_REG_RK1_DQSOSC_STATUS - DRAMC_NAO_BASE_ADDRESS))
@ -109,9 +109,9 @@ U32 u4RegBaseAddrTraslate(DRAM_DFS_REG_SHU_T eShu, DRAM_RANK_T eRank, U32 u4reg_
u4Offset += DRAMC_REG_NAO_RANK_OFFSET;
}
}
else if (u4RegType >= 4 && u4RegType <= 5) // PhyA/B NAO Register
else if (u4RegType >= 4 && u4RegType <= 5)
{
// PhyA/B NAO Register
if (u4Offset >= DDRPHY_NAO_RANK0_B0_DQSIEN_AUTOK_STATUS_START &&
u4Offset < DDRPHY_NAO_RANK0_B0_DQSIEN_AUTOK_STATUS_END)
{
@ -181,12 +181,12 @@ static U32 u4RegBaseAddrTraslate(DRAM_DFS_REG_SHU_T eShu, DRAM_RANK_T eRank, U32
return u4reg_addr;
}
if (u4RegType >= 4 && u4RegType <= 7)// ChA/B Dramc AO Register
if (u4RegType >= 4 && u4RegType <= 7)
{
if (u4Offset < DRAMC_REG_AO_SHUFFLE0_BASE_ADDR || u4Offset > DRAMC_REG_AO_SHUFFLE0_END_ADDR)
eShu = 0;
}
else if (u4RegType >= 12 && u4RegType <= 15)// ChA/B Phy AO Register
else if (u4RegType >= 12 && u4RegType <= 15)
{
if (u4Offset < DDRPHY_AO_SHUFFLE0_BASE_ADDR || u4Offset > DDRPHY_AO_SHUFFLE0_END_ADDR)
eShu = 0;
@ -194,7 +194,7 @@ static U32 u4RegBaseAddrTraslate(DRAM_DFS_REG_SHU_T eShu, DRAM_RANK_T eRank, U32
if (eRank == RANK_1)
{
if (u4RegType >= 4 && u4RegType <= 7)// ChA/B Dramc AO Register
if (u4RegType >= 4 && u4RegType <= 7)
{
if (u4Offset >= DRAMC_REG_AO_RANK0_WO_SHUFFLE_BASE_ADDR &&
u4Offset <= DRAMC_REG_AO_RANK0_WO_SHUFFLE_END_ADDR)
@ -207,52 +207,52 @@ static U32 u4RegBaseAddrTraslate(DRAM_DFS_REG_SHU_T eShu, DRAM_RANK_T eRank, U32
u4Offset += DRAMC_REG_AO_RANK_OFFSET;
}
}
else if (u4RegType >= 12 && u4RegType <= 15)// PhyA/B AO Register
else if (u4RegType >= 12 && u4RegType <= 15)
{
// 0x60~0xE0
if (u4Offset >= DDRPHY_AO_RANK0_B0_NON_SHU_BASE_ADDR &&
u4Offset <= DDRPHY_AO_RANK0_B0_NON_SHU_END_ADDR)
{
u4Offset += DDRPHY_AO_RANK_OFFSET;
}
// 0x1E0~0x260
else if (u4Offset >= DDRPHY_AO_RANK0_B1_NON_SHU_BASE_ADDR &&
u4Offset <= DDRPHY_AO_RANK0_B1_NON_SHU_END_ADDR)
{
u4Offset += DDRPHY_AO_RANK_OFFSET;
}
// 0x360~0x3E0
else if (u4Offset >= DDRPHY_AO_RANK0_CA_NON_SHU_BASE_ADDR &&
u4Offset <= DDRPHY_AO_RANK0_CA_NON_SHU_END_ADDR)
{
u4Offset += DDRPHY_AO_RANK_OFFSET;
}
// 0x760~0x7E0
else if (u4Offset >= DDRPHY_AO_RANK0_B0_SHU0_BASE_ADDR &&
u4Offset <= DDRPHY_AO_RANK0_B0_SHU0_END_ADDR)
{
u4Offset += DDRPHY_AO_RANK_OFFSET;
}
// 0x8E0~0x960
else if (u4Offset >= DDRPHY_AO_RANK0_B1_SHU0_BASE_ADDR &&
u4Offset <= DDRPHY_AO_RANK0_B1_SHU0_END_ADDR)
{
u4Offset += DDRPHY_AO_RANK_OFFSET;
}
// 0xA60~0xAE0
else if (u4Offset >= DDRPHY_AO_RANK0_CA_SHU0_BASE_ADDR &&
u4Offset <= DDRPHY_AO_RANK0_CA_SHU0_END_ADDR)
{
u4Offset += DDRPHY_AO_RANK_OFFSET;
}
// 0xBE0~0xC60
else if (u4Offset >= DDRPHY_AO_RANK0_MISC_SHU0_BASE_ADDR &&
u4Offset <= DDRPHY_AO_RANK0_MISC_SHU0_END_ADDR)
{
u4Offset += DDRPHY_AO_RANK_OFFSET;
}
}
else if (u4RegType <= 3)// ChA/B Dramc NAO Register
else if (u4RegType <= 3)
{
if (u4Offset >= (DRAMC_REG_RK0_DQSOSC_STATUS - DRAMC_NAO_BASE_ADDRESS) &&
u4Offset < (DRAMC_REG_RK1_DQSOSC_STATUS - DRAMC_NAO_BASE_ADDRESS))
@ -260,9 +260,9 @@ static U32 u4RegBaseAddrTraslate(DRAM_DFS_REG_SHU_T eShu, DRAM_RANK_T eRank, U32
u4Offset += 0x100;
}
}
else if (u4RegType >= 8 && u4RegType <= 11) // PhyA/B NAO Register
else if (u4RegType >= 8 && u4RegType <= 11)
{
// PhyA/B NAO Register
if (u4Offset >= DDRPHY_NAO_RANK0_B0_DQSIEN_AUTOK_STATUS_START &&
u4Offset < DDRPHY_NAO_RANK0_B0_DQSIEN_AUTOK_STATUS_END)
{
@ -358,30 +358,22 @@ inline U32 _u4Dram_Register_Read(U64 u4reg_addr)
#if QT_GUI_Tool
ucDramRegRead_1(u4reg_addr, &u4reg_value);
#elif (FOR_DV_SIMULATION_USED == 1) //DV
#elif (FOR_DV_SIMULATION_USED == 1)
u4reg_value = register_read_c(u4reg_addr);
#else // real chip
#else
u4reg_value = *((volatile unsigned int *)u4reg_addr);
#endif
return u4reg_value;
}
//-------------------------------------------------------------------------
/** ucDram_Register_Read
* DRAM register read (32-bit).
* @param u4reg_addr register address in 32-bit.
* @param pu4reg_value Pointer of register read value.
* @retval 0: OK, 1: FAIL
*/
//-------------------------------------------------------------------------
// This function need to be porting by BU requirement
U32 u4Dram_Register_Read(DRAMC_CTX_T *p, U32 u4reg_addr)
{
U32 u4RegType = ((u4reg_addr - Channel_A_DRAMC_NAO_BASE_VIRTUAL) >> POS_BANK_NUM) & 0xf;
#if (fcFOR_CHIP_ID == fc8195)
//ignore CH-B
if ((p->support_channel_num == CHANNEL_SINGLE) && (u4reg_addr >= Channel_A_DRAMC_NAO_BASE_VIRTUAL && u4reg_addr < MAX_BASE_VIRTUAL))
{
if(u4RegType%2!=0)
@ -397,15 +389,6 @@ U32 u4Dram_Register_Read(DRAMC_CTX_T *p, U32 u4reg_addr)
}
//-------------------------------------------------------------------------
/** ucDram_Register_Write
* DRAM register write (32-bit).
* @param u4reg_addr register address in 32-bit.
* @param u4reg_value register write value.
* @retval 0: OK, 1: FAIL
*/
//-------------------------------------------------------------------------
#if REG_ACCESS_NAO_DGB
#if (fcFOR_CHIP_ID == fcCervino)
U8 Check_RG_Not_AO(U32 u4reg_addr)
@ -439,8 +422,8 @@ inline void _ucDram_Register_Write(U64 u4reg_addr, U32 u4reg_value)
ucDramRegWrite_1(u4reg_addr, u4reg_value);
#elif (FOR_DV_SIMULATION_USED == 1) //DV
register_write_c(u4reg_addr, u4reg_value);
#else // real chip
(*(volatile unsigned int *)u4reg_addr) = u4reg_value;//real chip
#else
(*(volatile unsigned int *)u4reg_addr) = u4reg_value;
#if !defined(__DPM__)
dsb();
#endif
@ -451,7 +434,7 @@ inline void _ucDram_Register_Write(U64 u4reg_addr, U32 u4reg_value)
{
mcSHOW_DUMP_INIT_RG_MSG(("*((UINT32P)(0x%x)) = 0x%x;\n",u4reg_addr,u4reg_value));
gDUMP_INIT_RG_LOG_TO_DE_RG_log_flag = 0;
mcDELAY_MS(1); // to receive log for log
mcDELAY_MS(1);
gDUMP_INIT_RG_LOG_TO_DE_RG_log_flag = 1;
}
#endif
@ -464,13 +447,13 @@ inline void _ucDram_Register_Write(U64 u4reg_addr, U32 u4reg_value)
#endif
}
//This function need to be porting by BU requirement
void ucDram_Register_Write(DRAMC_CTX_T *p, U32 u4reg_addr, U32 u4reg_value)
{
U32 u4RegType = ((u4reg_addr - Channel_A_DRAMC_NAO_BASE_VIRTUAL) >> POS_BANK_NUM) & 0xf;
#if (fcFOR_CHIP_ID == fc8195)
//ignore CH-B
if ((p->support_channel_num == CHANNEL_SINGLE) && (u4reg_addr >= Channel_A_DRAMC_NAO_BASE_VIRTUAL && u4reg_addr < MAX_BASE_VIRTUAL))
{
if(u4RegType%2!=0)
@ -495,7 +478,7 @@ void vIO32Write4BMsk2(DRAMC_CTX_T *p, U32 reg32, U32 val32, U32 msk32)
U32 u4Val;
U32 u4RegType = ((reg32 - Channel_A_DRAMC_NAO_BASE_VIRTUAL) >> POS_BANK_NUM) & 0xf;
//ignore CH-B
#if (fcFOR_CHIP_ID == fc8195)
if ((p->support_channel_num == CHANNEL_SINGLE) && (reg32 >= Channel_A_DRAMC_NAO_BASE_VIRTUAL && reg32 <= MAX_BASE_VIRTUAL))
{
@ -520,30 +503,30 @@ void vIO32Write4B_All2(DRAMC_CTX_T *p, U32 reg32, U32 val32)
U32 u4RegType = (reg32 & (0x1f << POS_BANK_NUM));
U8 u1BCSupport = TRUE;
reg32 &= 0xffff; // remove channel information
reg32 &= 0xffff;
u1AllCount = p->support_channel_num; // for all dramC and PHY
u1AllCount = p->support_channel_num;
if (u4RegType >= Channel_A_DDRPHY_DPM_BASE_VIRTUAL)//DPM
if (u4RegType >= Channel_A_DDRPHY_DPM_BASE_VIRTUAL)
{
reg32 += Channel_A_DDRPHY_DPM_BASE_VIRTUAL;
if (u1AllCount > 1)
u1AllCount >>= 1;
u1BCSupport = FALSE;
}
else if (u4RegType >= Channel_A_DDRPHY_AO_BASE_VIRTUAL)// PHY AO
else if (u4RegType >= Channel_A_DDRPHY_AO_BASE_VIRTUAL)
{
reg32 += Channel_A_DDRPHY_AO_BASE_VIRTUAL;
}
else if (u4RegType >= Channel_A_DDRPHY_NAO_BASE_VIRTUAL)// PHY NAO
else if (u4RegType >= Channel_A_DDRPHY_NAO_BASE_VIRTUAL)
{
reg32 += Channel_A_DDRPHY_NAO_BASE_VIRTUAL;
}
else if (u4RegType >= Channel_A_DRAMC_AO_BASE_VIRTUAL)// DramC AO
else if (u4RegType >= Channel_A_DRAMC_AO_BASE_VIRTUAL)
{
reg32 += Channel_A_DRAMC_AO_BASE_VIRTUAL;
}
else // DramC NAO
else
{
reg32 += Channel_A_DRAMC_NAO_BASE_VIRTUAL;
}
@ -570,30 +553,30 @@ void vIO32Write4BMsk_All2(DRAMC_CTX_T *p, U32 reg32, U32 val32, U32 msk32)
U32 u4RegType = (reg32 & (0x1f << POS_BANK_NUM));
U8 u1BCSupport = TRUE;
reg32 &= 0xffff; // remove channel information
reg32 &= 0xffff;
u1AllCount = p->support_channel_num; // for all dramC and PHY
u1AllCount = p->support_channel_num;
if (u4RegType >= Channel_A_DDRPHY_DPM_BASE_VIRTUAL)//DPM
if (u4RegType >= Channel_A_DDRPHY_DPM_BASE_VIRTUAL)
{
reg32 += Channel_A_DDRPHY_DPM_BASE_VIRTUAL;
if (u1AllCount > 1)
u1AllCount >>= 1;
u1BCSupport = FALSE;
}
else if (u4RegType >= Channel_A_DDRPHY_AO_BASE_VIRTUAL)// PHY AO
else if (u4RegType >= Channel_A_DDRPHY_AO_BASE_VIRTUAL)
{
reg32 += Channel_A_DDRPHY_AO_BASE_VIRTUAL;
}
else if (u4RegType >= Channel_A_DDRPHY_NAO_BASE_VIRTUAL)// PHY NAO
else if (u4RegType >= Channel_A_DDRPHY_NAO_BASE_VIRTUAL)
{
reg32 += Channel_A_DDRPHY_NAO_BASE_VIRTUAL;
}
else if (u4RegType >= Channel_A_DRAMC_AO_BASE_VIRTUAL)// DramC AO
else if (u4RegType >= Channel_A_DRAMC_AO_BASE_VIRTUAL)
{
reg32 += Channel_A_DRAMC_AO_BASE_VIRTUAL;
}
else // DramC NAO
else
{
reg32 += Channel_A_DRAMC_NAO_BASE_VIRTUAL;
}

49
src/vendorcode/mediatek/mt8195/dramc/LP4_dram_init.c
View File

@ -11,7 +11,7 @@ void CKE_FIX_ON(DRAMC_CTX_T *p, U8 EN, U8 rank)
default: mcSHOW_ERR_MSG(("ERROR: CKE FIX ON error. Unexpected Rank \n"));
}
}
//[SV] task LP4_MRS(bit [7:0] reg_addr, bit[7:0] reg_op, bit[1:0] rank);
static void LP4_MRS(DRAMC_CTX_T *p, U16 reg_addr, U8 reg_op, U8 rank)
{
U8 temp_MRS_RESPONSE ;
@ -37,13 +37,11 @@ static void LP4_MRS(DRAMC_CTX_T *p, U16 reg_addr, U8 reg_op, U8 rank)
static void LP4_FSP_WR_or_OP (DRAMC_CTX_T *p, U8 FSP_WR, U8 FSP_OP, U8 rank)
{
U8 MR13 = 0;
MR13 = ((FSP_OP & 1) << 7) | ((FSP_WR & 1) << 6) /*| ((LP4_DMI & 1) << 5)*/ | (1 << 4)/*[RRO] for MR4 refresh rate*/;
MR13 = ((FSP_OP & 1) << 7) | ((FSP_WR & 1) << 6) /*| ((LP4_DMI & 1) << 5)*/ | (1 << 4);
LP4_MRS(p, 13, MR13, rank);
}
//==================================
//uesage(constraint): DBI = 1 for FSPOP=1 if DBI=0 then FSP_OP =0
//==================================
static void lp4_dram_init_single_rank(DRAMC_CTX_T *p,LP4_DRAM_CONFIG_T *tr,U8 rank)
{
U8 MR1;
@ -54,7 +52,7 @@ static void lp4_dram_init_single_rank(DRAMC_CTX_T *p,LP4_DRAM_CONFIG_T *tr,U8 ra
U8 MR12;
U8 MR14;
//default value for LP4 DRAM CONFIG
U8 nWR =5;
U8 WR_LEV =0;
U8 PDDS =5;
@ -62,9 +60,9 @@ static void lp4_dram_init_single_rank(DRAMC_CTX_T *p,LP4_DRAM_CONFIG_T *tr,U8 ra
U8 PU_CAL =0;
U8 WLS =0;
//Notice: DBI default = 0
//field & configuration adaption
MR1 = ((tr->RPST & 1)<<7) | ((nWR & 7)<<4) | ((tr->RD_PRE & 1)<<3) | ((tr->WR_PRE & 1)<<2) | ((tr->BL & 3)<<0);
MR2 = ((WR_LEV & 1)<<7) | ((WLS & 1)<<6) | ((tr->MR_WL & 7)<<3) | ((tr->MR_RL & 7)<<0);
MR3 = ((tr->DBI_WR & 1)<<7) | ((tr->DBI_RD & 1)<<6) | (( PDDS & 7)<<3) | ((PPRP & 1)<<2) | ((tr->WR_PST & 1)<<1) | ((PU_CAL & 1)<<0);
@ -84,20 +82,20 @@ static void lp4_dram_init_single_rank(DRAMC_CTX_T *p,LP4_DRAM_CONFIG_T *tr,U8 ra
if(p->dram_fsp == FSP_1)
MR12 = 0x20;
#endif
//temp workaround for global variable of MR
u1MR02Value[tr->WORK_FSP] = MR2;
u1MR03Value[tr->WORK_FSP] = MR3;
#if ENABLE_LP4_ZQ_CAL
DramcZQCalibration(p, rank); //ZQ calobration should be done before CBT calibration by switching to low frequency
DramcZQCalibration(p, rank);
#endif
mcSHOW_DBG_MSG6(("[LP4_DRAM_INIT] Channle:%1d-Rank:%1d >>>>>>\n",vGetPHY2ChannelMapping(p),rank));
//first FSP
if(tr->WORK_FSP == 0) {LP4_FSP_WR_or_OP(p, 0, 1, rank);}
else {LP4_FSP_WR_or_OP(p, 1, 0, rank);}
mcDELAY_XNS(15); //TCKFSPE
mcDELAY_XNS(15);
LP4_MRS(p, 1, MR1 , rank);
LP4_MRS(p, 2, MR2 , rank);
@ -107,17 +105,17 @@ static void lp4_dram_init_single_rank(DRAMC_CTX_T *p,LP4_DRAM_CONFIG_T *tr,U8 ra
LP4_MRS(p, 14, MR14 , rank);
if(tr->LP4Y_EN == 1) { LP4_MRS(p, 51, MR51, rank); }
mcDELAY_XNS(15); //TCKFSPX
mcDELAY_XNS(15);
//2nd FSP
if(tr->WORK_FSP == 0) {LP4_FSP_WR_or_OP(p, 1, 0, rank);}
else {LP4_FSP_WR_or_OP(p, 0, 1, rank);}
mcDELAY_XNS(15); //TCKFSPE
mcDELAY_XNS(15);
LP4_MRS(p, 1, MR1 , rank);
LP4_MRS(p, 2, MR2 , rank);
//reverse the DBI
MR3 = ((!tr->DBI_WR & 1)<<7) | ((!tr->DBI_RD & 1)<<6) | (( PDDS & 7)<<3) | ((PPRP & 1)<<2) | ((tr->WR_PST & 1)<<1) | ((PU_CAL & 1)<<0);
LP4_MRS(p, 3, MR3 , rank);
LP4_MRS(p, 11, MR11 , rank);
@ -145,17 +143,17 @@ void LP4_single_end_DRAMC_post_config(DRAMC_CTX_T *p, U8 LP4Y_EN)
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD0) , P_Fld( 0 , SHU_CA_CMD0_R_LP4Y_WDN_MODE_CLK ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ0) , P_Fld( 0 , SHU_B0_DQ0_R_LP4Y_WDN_MODE_DQS0 ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ0) , P_Fld( 0 , SHU_B1_DQ0_R_LP4Y_WDN_MODE_DQS1 ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD7) , P_Fld( 0 , SHU_CA_CMD7_R_LP4Y_SDN_MODE_CLK )); //@Darren, debugging for DFS stress fail
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD7) , P_Fld( 0 , SHU_CA_CMD7_R_LP4Y_SDN_MODE_CLK ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ7) , P_Fld( LP4Y_EN , SHU_B0_DQ7_R_LP4Y_SDN_MODE_DQS0 ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ7) , P_Fld( LP4Y_EN , SHU_B1_DQ7_R_LP4Y_SDN_MODE_DQS1 ));
#if 1//ENABLE_LP4Y_DFS // @Darren, need confirm
// for strong pull low and normal mode
#if 1
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD7) , P_Fld( 0 , CA_CMD7_RG_TX_ARCLKB_PULL_DN_LP4Y ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ7) , P_Fld( 0 , B0_DQ7_RG_TX_ARDQS0B_PULL_DN_B0_LP4Y ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ7) , P_Fld( 0 , B1_DQ7_RG_TX_ARDQS0B_PULL_DN_B1_LP4Y ));
#else
// for weak pull low mode only
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD7) , P_Fld( 1 , CA_CMD7_RG_TX_ARCLKB_PULL_DN_LP4Y ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ7) , P_Fld( 1 , B0_DQ7_RG_TX_ARDQS0B_PULL_DN_B0_LP4Y ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ7) , P_Fld( 1 , B1_DQ7_RG_TX_ARDQS0B_PULL_DN_B1_LP4Y ));
@ -168,22 +166,23 @@ void LP4_DRAM_INIT(DRAMC_CTX_T *p)
U8 RANK;
#if SA_CONFIG_EN && DV_SIMULATION_DFS// @Darren, temp workaround
#if SA_CONFIG_EN && DV_SIMULATION_DFS
DramcPowerOnSequence(p);
#endif
mcDELAY_XNS(200); //tINIT3 = 2ms for DV fastup to 200ns
mcDELAY_XNS(200);
for(RANK=0;RANK<2;RANK++)
{
CKE_FIX_ON(p,1,RANK);
mcDELAY_XNS(400); //tINIT5 fastup to 400ns
mcDELAY_XNS(400);
//step4 moderegister setting
lp4_dram_init_single_rank(p,DV_p.lp4_init,RANK);
CKE_FIX_ON(p,0,RANK);
}
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_REFCTRL0), P_Fld(0, REFCTRL0_REFDIS)); //TODO enable refresh
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_REFCTRL0), P_Fld(0, REFCTRL0_REFDIS));
}

446
src/vendorcode/mediatek/mt8195/dramc/dramc_actiming.c
View File

File diff suppressed because it is too large Load Diff

751
src/vendorcode/mediatek/mt8195/dramc/dramc_debug.c
View File

File diff suppressed because it is too large Load Diff

10918
src/vendorcode/mediatek/mt8195/dramc/dramc_dv_freq_related.c
View File

File diff suppressed because it is too large Load Diff

514
src/vendorcode/mediatek/mt8195/dramc/dramc_dvfs.c
View File

File diff suppressed because it is too large Load Diff

79
src/vendorcode/mediatek/mt8195/dramc/dramc_lowpower.c
View File

@ -11,13 +11,10 @@
//-----------------------------------------------------------------------------
U8 gDRSEnableSelfWakeup = 0;
//----------------------------------------
// Auto Gen Code -- START
//----------------------------------------
#if (CHECK_GOLDEN_SETTING == TRUE)
typedef struct _GOLDEN_FIELD_T
{
char fieldName[64]; //field name
char fieldName[64];
U32 group;
U32 field;
U32 u4ChaValue;
@ -25,7 +22,7 @@ typedef struct _GOLDEN_FIELD_T
GOLDEN_FIELD_T *golden_setting_anwer;
#if APPLY_LOWPOWER_GOLDEN_SETTINGS
// DCM On
GOLDEN_FIELD_T shuf_golden_setting_anwer[] =
{
{"SHU_B1_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B1", DDRPHY_REG_SHU_B1_DQ8, SHU_B1_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B1, 0x0},
@ -169,7 +166,7 @@ GOLDEN_FIELD_T nonshuf_golden_setting_anwer[] =
};
#else
// DCM Off
GOLDEN_FIELD_T shuf_golden_setting_anwer[] =
{
{"SHU_B1_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B1", DDRPHY_REG_SHU_B1_DQ8, SHU_B1_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B1, 0x1},
@ -336,7 +333,7 @@ static void EnableCommonDCMNonShuffle(DRAMC_CTX_T *p)
P_Fld(0x0, MISC_CG_CTRL2_RG_PIPE0_CG_OFF_DISABLE) |
P_Fld(0x0, MISC_CG_CTRL2_RG_MEM_DCM_APB_TOG) |
P_Fld(0x5, MISC_CG_CTRL2_RG_MEM_DCM_DBC_CNT));
// RG group needs to be toggled!!
vIO32WriteFldAlign_All(DDRPHY_REG_MISC_CG_CTRL2, 1, MISC_CG_CTRL2_RG_MEM_DCM_APB_TOG);
vIO32WriteFldAlign_All(DDRPHY_REG_MISC_CG_CTRL2, 0, MISC_CG_CTRL2_RG_MEM_DCM_APB_TOG);
vIO32WriteFldAlign_All(DDRPHY_REG_CA_DLL_ARPI1, 0x0, CA_DLL_ARPI1_RG_ARPISM_MCK_SEL_CA_REG_OPT);
@ -395,7 +392,7 @@ void EnableDramcPhyDCMNonShuffle(DRAMC_CTX_T *p, bool bEn)
{
BOOL isLP4_DSC = (p->DRAMPinmux == PINMUX_DSC)?1:0;
U8 MPDIV_CG = 1;
// Special case
EnableCommonDCMNonShuffle(p);
if(bEn)
@ -407,7 +404,7 @@ void EnableDramcPhyDCMNonShuffle(DRAMC_CTX_T *p, bool bEn)
vIO32WriteFldMulti_All(DDRPHY_REG_MISC_CG_CTRL2,
P_Fld(0x0, MISC_CG_CTRL2_RG_MEM_DCM_FORCE_ON) |
P_Fld(0x1, MISC_CG_CTRL2_RG_MEM_DCM_DCM_EN));
// RG group needs to be toggled!!
vIO32WriteFldAlign_All(DDRPHY_REG_MISC_CG_CTRL2, 1, MISC_CG_CTRL2_RG_MEM_DCM_APB_TOG);
vIO32WriteFldAlign_All(DDRPHY_REG_MISC_CG_CTRL2, 0, MISC_CG_CTRL2_RG_MEM_DCM_APB_TOG);
vIO32WriteFldMulti_All(DRAMC_REG_TX_CG_SET0,
@ -475,7 +472,7 @@ void EnableDramcPhyDCMNonShuffle(DRAMC_CTX_T *p, bool bEn)
vIO32WriteFldMulti_All(DDRPHY_REG_MISC_CTRL4,
#if (RX_PICG_NEW_MODE || TX_PICG_NEW_MODE)
P_Fld(0x1, MISC_CTRL4_R_OPT2_CG_MCK) |
P_Fld(MPDIV_CG, MISC_CTRL4_R_OPT2_MPDIV_CG) | //WA for DDR800 DSC DRAM, Need to check in Sim
P_Fld(MPDIV_CG, MISC_CTRL4_R_OPT2_MPDIV_CG) |
#endif
#if RX_PICG_NEW_MODE
P_Fld(0x1, MISC_CTRL4_R_OPT2_CG_DQSIEN) |
@ -501,7 +498,7 @@ void EnableDramcPhyDCMNonShuffle(DRAMC_CTX_T *p, bool bEn)
vIO32WriteFldMulti_All(DDRPHY_REG_MISC_CG_CTRL2,
P_Fld(0x1, MISC_CG_CTRL2_RG_MEM_DCM_FORCE_ON) |
P_Fld(0x0, MISC_CG_CTRL2_RG_MEM_DCM_DCM_EN));
// RG group needs to be toggled!!
vIO32WriteFldAlign_All(DDRPHY_REG_MISC_CG_CTRL2, 1, MISC_CG_CTRL2_RG_MEM_DCM_APB_TOG);
vIO32WriteFldAlign_All(DDRPHY_REG_MISC_CG_CTRL2, 0, MISC_CG_CTRL2_RG_MEM_DCM_APB_TOG);
vIO32WriteFldMulti_All(DRAMC_REG_TX_CG_SET0,
@ -582,7 +579,7 @@ void EnableDramcPhyDCMNonShuffle(DRAMC_CTX_T *p, bool bEn)
void EnableDramcPhyDCMShuffle(DRAMC_CTX_T *p, bool bEn)
{
BOOL isLP4_DSC = (p->DRAMPinmux == PINMUX_DSC)?1:0;
// Special case
// DRAMC_REG_SHU_RX_CG_SET0 - SHU_RX_CG_SET0_READ_START_EXTEND3: Special case
// DRAMC_REG_SHU_RX_CG_SET0 - SHU_RX_CG_SET0_READ_START_EXTEND2: Special case
// DRAMC_REG_SHU_RX_CG_SET0 - SHU_RX_CG_SET0_READ_START_EXTEND1: Special case
@ -662,9 +659,7 @@ void EnableDramcPhyDCMShuffle(DRAMC_CTX_T *p, bool bEn)
return;
}
//----------------------------------------
// Auto Gen Code -- END
//----------------------------------------
void EnableDramcPhyDCM(DRAMC_CTX_T *p, bool bEn)
{
@ -672,7 +667,7 @@ void EnableDramcPhyDCM(DRAMC_CTX_T *p, bool bEn)
DramcBroadcastOnOff(DRAMC_BROADCAST_OFF);
EnableDramcPhyDCMNonShuffle(p, bEn);
EnableDramcPhyDCMShuffle(p, bEn);//only need to set SHU0 RG while init, SHU0 will copy to others
EnableDramcPhyDCMShuffle(p, bEn);
#if ((CHECK_GOLDEN_SETTING == TRUE) && (APPLY_LOWPOWER_GOLDEN_SETTINGS == 0))
DRAM_STATUS_T stResult = CheckGoldenSetting(p);
@ -726,7 +721,7 @@ DRAM_STATUS_T CheckRxPICGNewModeSetting(DRAMC_CTX_T *p)
u4Value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL2), MISC_STBCAL2_STB_STBENRST_EARLY_1T_EN);
mcSHOW_DBG_MSG(("MISC_STBCAL2_STB_STBENRST_EARLY_1T_EN:0x%x \n", u4Value));
for (u1RankIdx = 0; u1RankIdx < p->support_rank_num; u1RankIdx++)//Should set 2 rank
for (u1RankIdx = 0; u1RankIdx < p->support_rank_num; u1RankIdx++)
{
vSetRank(p, u1RankIdx);
@ -774,15 +769,15 @@ static DRAM_STATUS_T CheckGoldenField(DRAMC_CTX_T *p, GOLDEN_FIELD_T *golden_set
U16 u2Idx = 0;
for(u2Idx = 0; u2Idx < array_cnt; u2Idx++)
{
for(channel_idx = CHANNEL_A; channel_idx < p->support_channel_num; channel_idx++)//comapre CHA && CHB
for(channel_idx = CHANNEL_A; channel_idx < p->support_channel_num; channel_idx++)
{
vSetPHY2ChannelMapping(p, channel_idx);
u4Value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(golden_setting_anwer[u2Idx].group), golden_setting_anwer[u2Idx].field);
//mcSHOW_DBG_MSG(("%s: 0x%x\n", golden_setting_anwer[u2Idx].fieldName, u4Value));
u4Answer = *(&golden_setting_anwer[u2Idx].u4ChaValue);//golden_setting_anwer only has CHA value
u4Answer = *(&golden_setting_anwer[u2Idx].u4ChaValue);
if(u4Answer != 0xffffffff)//0xffffffff: no need to compare
if(u4Answer != 0xffffffff)
{
if(u4Answer == u4Value)
{
@ -823,11 +818,11 @@ DRAM_STATUS_T CheckGoldenSetting(DRAMC_CTX_T *p)
else
{
mcSHOW_DBG_MSG3(("CONF SHU0, DDR[%d]\n", p->frequency * 2));
u1SramShuffleIdx = u1BkShuffleIdx; //Restore to original freq && check conf SHU0
u1SramShuffleIdx = u1BkShuffleIdx;
}
//mcSHOW_DBG_MSG(("shuf_golden_setting_anwer:%d %d\n", sizeof(shuf_golden_setting_anwer), sizeof(shuf_golden_setting_anwer[0])));
DramcDFSDirectJump(p, u1SramShuffleIdx); //fill conf SHU0 && SHU1 from SRAM SHU(0~9) while DVFS twice
DramcDFSDirectJump(p, u1SramShuffleIdx);
DramcDFSDirectJump(p, u1SramShuffleIdx);
eStatus |= CheckGoldenField(p, shuf_golden_setting_anwer, sizeof(shuf_golden_setting_anwer));
@ -846,7 +841,7 @@ DRAM_STATUS_T CheckGoldenSetting(DRAMC_CTX_T *p)
}
#endif
//#ifdef HW_SAVE_FOR_SR
void HwSaveForSR(DRAMC_CTX_T *p)
{
vIO32WriteFldMulti_All(DRAMC_REG_SREF_DPD_CTRL, P_Fld(0, SREF_DPD_CTRL_GT_SYNC_MASK)
@ -854,15 +849,13 @@ void HwSaveForSR(DRAMC_CTX_T *p)
| P_Fld(1, SREF_DPD_CTRL_SREF2_OPTION)
| P_Fld(0, SREF_DPD_CTRL_SREF3_OPTION));
vIO32WriteFldAlign_All(DDRPHY_REG_MISC_DVFSCTL2, 0x0, MISC_DVFSCTL2_GT_SYNC_MASK_FOR_PHY);//PIC: Robert
vIO32WriteFldAlign_All(DDRPHY_REG_MISC_DVFSCTL2, 0x0, MISC_DVFSCTL2_GT_SYNC_MASK_FOR_PHY);
}
//#endif
//#ifdef CLK_FREE_FUN_FOR_DRAMC_PSEL
//If dramc enter SREF and power down, all configure need to sync 2T again after exit SREF.
//If Psel is 1, clock will be free run at the periof of 2T to let conf be applied.
//If Psel is 0, Clock will be gated
void ClkFreeRunForDramcPsel(DRAMC_CTX_T *p)
{
vIO32WriteFldMulti_All(DRAMC_REG_TX_CG_SET0, P_Fld(0, TX_CG_SET0_PSEL_OPT1)
@ -887,26 +880,26 @@ void DDR800semiPowerSavingOn(DRAMC_CTX_T *p, U8 next_shu_level, U8 u1OnOff)
U8 u1ShuLevel = u4IO32ReadFldAlign(DDRPHY_REG_MISC_DVFSCTL, MISC_DVFSCTL_R_OTHER_SHU_GP);
U8 u1IsDdr800Semi = u4IO32ReadFldAlign(DDRPHY_REG_SHU_PLL1 + (SHU_GRP_DDRPHY_OFFSET * u1ShuLevel), SHU_PLL1_RG_RPHYPLL_DDR400_EN);
if (u1IsDdr800Semi != 1) // close mode will return
if (u1IsDdr800Semi != 1)
return;
if ((next_shu_level != SRAM_SHU9) && (u1OnOff == DISABLE))
{
// for NORMAL_CLOSE_LOOP
EnableDllCg(p, DISABLE);
}
else if ((next_shu_level == SRAM_SHU9) && (u1OnOff == ENABLE))
{
// for DDR800_SEMI_LOOP power saving, clock gating
EnableDllCg(p, ENABLE);
}
#endif
}
#endif
#if 0 //Comment out unused code
#if 0
void DramcDRS(DRAMC_CTX_T *p, U8 bEnable)
{
//R_DMDRS_CNTX[6:0](DVT set 0, HQA set 4 or 5)
vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DRAMC_REG_DRSCTRL), P_Fld(0, DRSCTRL_DRSPB2AB_OPT)
| P_Fld(0, DRSCTRL_DRSMON_CLR)
| P_Fld(8, DRSCTRL_DRSDLY)
@ -919,7 +912,7 @@ void DramcDRS(DRAMC_CTX_T *p, U8 bEnable)
}
#endif
#if 0 //Comment out unused code
#if 0
#if (FOR_DV_SIMULATION_USED == 0 && SW_CHANGE_FOR_SIMULATION == 0)
void DramcEnterSelfRefresh(DRAMC_CTX_T *p, U8 op)
{
@ -931,11 +924,9 @@ void DramcEnterSelfRefresh(DRAMC_CTX_T *p, U8 op)
mcSHOW_DBG_MSG(("[EnterSelfRefresh] %s\n", ((op == 1) ? "enter" : "exit")));
if (op == 1) // enter self refresh
if (op == 1)
{
// ONLY work for LP4, not LP3
// MISCA_SRFPD_DIS =1, self-refresh
// MISCA_SRFPD_DIS =0, self-refresh power down
vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SREFCTRL), 1, SREFCTRL_SRFPD_DIS);
vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SREFCTRL), 1, SREFCTRL_SELFREF);
@ -949,7 +940,7 @@ void DramcEnterSelfRefresh(DRAMC_CTX_T *p, U8 op)
u4TimeCnt --;
}
}
else // exit self refresh
else
{
vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SREFCTRL), 0, SREFCTRL_SELFREF);
@ -974,26 +965,26 @@ void DramcEnterSelfRefresh(DRAMC_CTX_T *p, U8 op)
}
}
#endif
#endif //Comment out unused code
#endif
//#if ENABLE_RX_DCM_DPHY
void EnableRxDcmDPhy(DRAMC_CTX_T *p, U16 u2Freq)
{
U8 u1PRECAL_CG_EN = 0;
//open loop mode and semi-open do not enable tracking
if (u1IsPhaseMode(p) == TRUE)
u1PRECAL_CG_EN = 1;
else
u1PRECAL_CG_EN = 0;
//power gain
vIO32WriteFldMulti_All(DDRPHY_REG_MISC_SHU_RX_CG_CTRL,
P_Fld(0x1, MISC_SHU_RX_CG_CTRL_RX_DCM_OPT) |
P_Fld(0x1, MISC_SHU_RX_CG_CTRL_RX_APHY_CTRL_DCM_OPT) |
P_Fld(0x1, MISC_SHU_RX_CG_CTRL_RX_RODT_DCM_OPT) |
P_Fld(0x0, MISC_SHU_RX_CG_CTRL_RX_DQSIEN_STBCAL_CG_EN) |
P_Fld(0x1, MISC_SHU_RX_CG_CTRL_RX_DQSIEN_AUTOK_CG_EN) | // if Rx gating Auto K, set 0, Runtime set 1
P_Fld(0x1, MISC_SHU_RX_CG_CTRL_RX_DQSIEN_AUTOK_CG_EN) |
P_Fld(0x1, MISC_SHU_RX_CG_CTRL_RX_DQSIEN_RETRY_CG_EN) |
P_Fld(u1PRECAL_CG_EN, MISC_SHU_RX_CG_CTRL_RX_PRECAL_CG_EN) |
P_Fld(0x2, MISC_SHU_RX_CG_CTRL_RX_DCM_EXT_DLY) |
@ -1002,7 +993,7 @@ void EnableRxDcmDPhy(DRAMC_CTX_T *p, U16 u2Freq)
#if RDSEL_TRACKING_EN
if(u2Freq >= RDSEL_TRACKING_TH)
{
vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SHU_RX_CG_CTRL, 0x0, MISC_SHU_RX_CG_CTRL_RX_RDSEL_TRACKING_CG_EN); // if K, set 1, at runtime if enable, set 0, else 1
vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SHU_RX_CG_CTRL, 0x0, MISC_SHU_RX_CG_CTRL_RX_RDSEL_TRACKING_CG_EN);
}
else
#endif
@ -1022,7 +1013,7 @@ void EnableCmdPicgEffImprove(DRAMC_CTX_T *p)
{
u2Clk_Dyn_Gating_Sel = 0x6;
}
else //DIV8_MODE, DIV16_MODE
else
{
u2Clk_Dyn_Gating_Sel = 0x5;
}

1902
src/vendorcode/mediatek/mt8195/dramc/dramc_pi_basic_api.c
View File

File diff suppressed because it is too large Load Diff

2304
src/vendorcode/mediatek/mt8195/dramc/dramc_pi_calibration_api.c
View File

File diff suppressed because it is too large Load Diff

697
src/vendorcode/mediatek/mt8195/dramc/dramc_pi_main.c
View File

File diff suppressed because it is too large Load Diff

168
src/vendorcode/mediatek/mt8195/dramc/dramc_top.c
View File

@ -210,12 +210,12 @@ void mdl_setting(DRAMC_CTX_T *p)
emi_init();
enable_infra_emi_broadcast(1);
//The following is MDL settings
set_cen_emi_cona(emi_set->EMI_CONA_VAL);
set_cen_emi_conf(emi_set->EMI_CONF_VAL);
set_cen_emi_conh(emi_set->EMI_CONH_VAL);
// CHNA and CHNB uses the same CH0 setting
set_chn_emi_cona(emi_set->CHN0_EMI_CONA_VAL);
//set_chn_emi_conc(0x4);
enable_infra_emi_broadcast(0);
@ -466,13 +466,13 @@ unsigned int is_discrete_lpddr4(void)
#if DRAM_AUXADC_CONFIG
return dram_type_auxadc;
#else
return TRUE; /* for 4ch DSC */
return TRUE;
#endif
}
unsigned int mt_get_dram_type_from_hw_trap(void)
{
#if 1 //for bring up use
#if 1
return TYPE_LPDDR4X;
#else
unsigned int trap = get_dram_type() & 0x7;
@ -643,7 +643,7 @@ static void restore_pmic_setting(void)
return;
}
#if 0 //for bring-up
#if 0
dramc_set_vmdd_voltage(TYPE_LPDDR4, 1125000);
dramc_set_vmddq_voltage(TYPE_LPDDR4, 600000);
dramc_set_vmddr_voltage(750000);
@ -693,28 +693,28 @@ void release_dram(void)
int i;
int counter = TIMEOUT;
// scy: restore pmic setting (VCORE, VDRAM, VSRAM, VDDQ)
restore_pmic_setting();
drm_release_rg_dramc_conf_iso();//Release DRAMC/PHY conf ISO
drm_release_rg_dramc_conf_iso();
#if DDR_RESERVE_NEW_MODE //new modw
#if DDR_RESERVE_NEW_MODE
ASVA5_8_New_Mode_1();
Dramc_DDR_Reserved_Mode_setting();
drm_release_rg_dramc_iso();//Release PHY IO ISO
drm_release_rg_dramc_iso();
ASVA5_8_New_Mode_2();
#else //old mode
#else
Dramc_DDR_Reserved_Mode_setting();
ASVA5_8_CSCA_Pull_Down_EN();
drm_release_rg_dramc_iso();//Release PHY IO ISO
drm_release_rg_dramc_iso();
ASVA5_8_CSCA_Pull_Down_DIS();
#endif
drm_release_rg_dramc_sref();//Let DRAM Leave SR
drm_release_rg_dramc_sref();
while(counter)
{
if(is_dramc_exit_slf() == 1) /* expect to exit dram-self-refresh */
if(is_dramc_exit_slf() == 1)
break;
counter--;
}
@ -733,15 +733,11 @@ void release_dram(void)
}
Dramc_DDR_Reserved_Mode_AfterSR();
#if DDR_RESERVE_NEW_MODE //new modw
#if DDR_RESERVE_NEW_MODE
ASVA5_8_New_Mode_3();
#endif
//Expect to Use LPDDR3200 and PHYPLL as output, so no need to handle
//shuffle status since the status will be reset by system reset
//There is an PLLL_SHU_GP in SPM which will reset by system reset
// setup for EMI: touch center EMI and channel EMI to enable CLK
dramc_crit("[DDR reserve] EMI CEN CONA: %x\n", get_cen_emi_cona());
dramc_crit("[DDR reserve] EMI CHN CONA: %x\n", get_chn_emi_cona());
for (i=0;i<10;i++);
@ -777,8 +773,8 @@ static int check_qvl(DRAM_INFO_BY_MRR_T *dram_info, unsigned int dram_type)
mr5 = dram_info->u2MR5VendorID & 0xFF;
rank_size[0] = dram_info->u8MR8Density[0]; //now only K CHA to save time
rank_size[1] = dram_info->u8MR8Density[1]; //now only K CHA to save time
rank_size[0] = dram_info->u8MR8Density[0];
rank_size[1] = dram_info->u8MR8Density[1];
result = platform_get_mcp_id(id, emmc_nand_id_len,&fw_id_len);
for (i = 0; i < num_of_emi_records; i++) {
@ -786,23 +782,23 @@ static int check_qvl(DRAM_INFO_BY_MRR_T *dram_info, unsigned int dram_type)
"qvl", i,
"type", qvl_list[i].type,
"mr5", qvl_list[i].iLPDDR3_MODE_REG_5,
"rank0_size", qvl_list[i].DRAM_RANK_SIZE[0], //DA need (unsigned int) (qvl_list[i].DRAM_RANK_SIZE[0] & 0xFFFFFFFF), (unsigned int)(qvl_list[i].DRAM_RANK_SIZE[0] >> 32),
"rank1_size", qvl_list[i].DRAM_RANK_SIZE[1]);//DA need (unsigned int) (qvl_list[i].DRAM_RANK_SIZE[1] & 0xFFFFFFFF), (unsigned int)(qvl_list[i].DRAM_RANK_SIZE[1] >> 32));
/* check DRAM type */
"rank0_size", qvl_list[i].DRAM_RANK_SIZE[0],
"rank1_size", qvl_list[i].DRAM_RANK_SIZE[1]);
if ((qvl_list[i].type & 0xF) != (dram_type & 0xF))
continue;
/* check MR5 */
if (qvl_list[i].iLPDDR3_MODE_REG_5 != mr5)
continue;
/* check rank size */
if (qvl_list[i].DRAM_RANK_SIZE[0] != rank_size[0])
continue;
if (qvl_list[i].DRAM_RANK_SIZE[1] != rank_size[1])
continue;
/* check storage ID if MCP */
if (qvl_list[i].type & 0xF00) {
if (!result) {
if (memcmp(id, qvl_list[i].ID, qvl_list[i].id_length)) {
@ -845,8 +841,8 @@ int get_dram_rank_nr(void)
cen_emi_cona = g_default_emi_setting.EMI_CONA_VAL;
if ((cen_emi_cona & (1 << 17)) != 0 || //for channel 0
(cen_emi_cona & (1 << 16)) != 0 ) //for channel 1
if ((cen_emi_cona & (1 << 17)) != 0 ||
(cen_emi_cona & (1 << 16)) != 0 )
return 2;
else
return 1;
@ -864,9 +860,7 @@ int get_dram_freq_cnt(void)
#if (FOR_DV_SIMULATION_USED==0)
#if !__FLASH_TOOL_DA__ && !__ETT__
/*
* setup block
*/
void get_dram_rank_size(u64 dram_rank_size[DRAMC_MAX_RK])
{
@ -1403,14 +1397,14 @@ static int update_dram_setting(EMI_SETTINGS *default_emi_setting, unsigned int d
default_emi_setting->iLPDDR3_MODE_REG_5 = dram_info->u2MR5VendorID;
if (dram_info->u4RankNum == 1) { // single rank
if (dram_info->u4RankNum == 1) {
if (dram_info->u1DieNum[RANK_0] == 1)
default_emi_setting->dram_cbt_mode_extern = CBT_R0_R1_NORMAL;
else if (dram_info->u1DieNum[RANK_0] == 2)
default_emi_setting->dram_cbt_mode_extern = CBT_R0_R1_BYTE;
else
return -1;
} else if (dram_info->u4RankNum == 2) { // dual rank
} else if (dram_info->u4RankNum == 2) {
if ((dram_info->u1DieNum[RANK_0] == 1) && (dram_info->u1DieNum[RANK_1] == 1))
default_emi_setting->dram_cbt_mode_extern = CBT_R0_R1_NORMAL;
else if ((dram_info->u1DieNum[RANK_0] == 1) && (dram_info->u1DieNum[RANK_1] == 2))
@ -1435,7 +1429,7 @@ static int decode_emi_info(EMI_INFO_T *emi_info, unsigned int dram_type, DRAM_IN
unsigned long long die_size;
emi_info->dram_type = dram_type;
emi_info->ch_num = 2; //2; //FIXME use GPIO
emi_info->ch_num = 2;
emi_info->bank_width[0] = 3;
emi_info->bank_width[1] = 3;
emi_info->col_width[0] = 10;
@ -1451,37 +1445,30 @@ static int decode_emi_info(EMI_INFO_T *emi_info, unsigned int dram_type, DRAM_IN
//emi_info->rank_size[1] /= emi_info->ch_num;
emi_info->rk_num = dram_info->u4RankNum;
/**
* ranksize row width
* 4Gb -> 15
* 8Gb -> 16
* 16Gb -> 17
* 32Gb -> 18
**/
for (i = 0; i < emi_info->rk_num; i++) {
die_size = emi_info->rank_size[i] / dram_info->u1DieNum[i];
switch (die_size | (dram_info->u1DieNum[i] << 4) | u1IsLP4Family(dram_type)) {
case 0x20000011ULL: // 4Gb, x16, LP4
case 0x20000021ULL: // 4Gb, x8, LP4
case 0x40000021ULL: // 8Gb, x8, LP4
case 0x30000011ULL: // 6Gb, x16, LP4
case 0x40000011ULL: // 8Gb, x16, LP4
case 0x20000011ULL:
case 0x20000021ULL:
case 0x40000021ULL:
case 0x30000011ULL:
case 0x40000011ULL:
emi_info->row_width[i] = 15;
break;
case 0x30000021ULL: // 6Gb, x8, LP4
case 0x60000011ULL: // 12Gb, x16, LP4
case 0x80000011ULL: // 16Gb, x16, LP4
case 0x30000021ULL:
case 0x60000011ULL:
case 0x80000011ULL:
emi_info->row_width[i] = 16;
break;
case 0x060000021ULL: // 12Gb, x8, LP4
case 0x080000021ULL: // 16Gb, x8, LP4
case 0x0C0000011ULL: // 24Gb, x16, LP4
case 0x100000011ULL: // 32Gb, x16, LP4
case 0x060000021ULL:
case 0x080000021ULL:
case 0x0C0000011ULL:
case 0x100000011ULL:
emi_info->row_width[i] = 17;
break;
case 0x0C0000021ULL: // 24Gb, x8, LP4
case 0x100000021ULL: // 32Gb, x8, LP4
case 0x0C0000021ULL:
case 0x100000021ULL:
emi_info->row_width[i] = 18;
break;
default:
@ -1542,7 +1529,7 @@ void dram_auto_detection(void)
DRAMC_ASSERT(0);
}
// different files for mt6880 and 6890 (different folder)
ret = update_emi_setting(&g_default_emi_setting, &emi_info);
if (ret) {
dramc_crit("[DRAMC] update_emi_setting err %d\n", ret);
@ -1566,20 +1553,9 @@ void mt_set_emi(struct dramc_param *dparam)
EMI_rank_swap_handle();
#endif
// set voltage and hw trapping before mdl
setup_dramc_voltage_by_pmic();
/*
if ((doe_get_config("dram_all_3094_0825")) || (doe_get_config("dram_all_3094_0725")))
freq_table_are_all_3094();
else if (doe_get_config("dram_all_1534_0725"))
freq_table_are_all_1534();
else if (doe_get_config("dram_opp0_3733_others_3094_0825"))
freq_table_opp0_3733_others_3094();
else if (doe_get_config("dram_opp0_3094_others_1534_0725"))
freq_table_opp0_3094_others_1534();
else if (doe_get_config("dram_opp0_2400_others_1534_0725"))
freq_table_opp0_2400_others_1534();
*/
#if DRAM_AUXADC_CONFIG
get_ch_num_by_auxadc();
#endif
@ -1690,7 +1666,7 @@ unsigned int get_dramc_addr(dram_addr_t *dram_addr, unsigned int offset)
unsigned int get_dummy_read_addr(dram_addr_t *dram_addr)
{
return get_dramc_addr(dram_addr, 0x20); // 32-byte align for dummy RW pattern
return get_dramc_addr(dram_addr, 0x20);
}
static unsigned int get_ta2_addr(dram_addr_t *dram_addr)
@ -1705,20 +1681,20 @@ void init_ta2_single_channel(unsigned int channel)
DRAMC_CTX_T *p = psCurrDramCtx;
int test_cnt;
// disable self test engine1 and self test engine2
temp = u4IO32Read4B(DRAMC_ADDR_SHIFT_CHN(DRAMC_REG_TEST2_A3, channel)) & 0x1FFFFFFF;
vIO32Write4B(DRAMC_ADDR_SHIFT_CHN(DRAMC_REG_TEST2_A3, channel), temp);
// set rank address for test agent to auto
temp = u4IO32Read4B(DRAMC_ADDR_SHIFT_CHN(DRAMC_REG_TEST2_A4, channel)) & 0x8FFFFFFF;
temp |= (0x4 << 28);
vIO32Write4B(DRAMC_ADDR_SHIFT_CHN(DRAMC_REG_TEST2_A4, channel), temp);
// set test for both rank0 and rank1
temp = u4IO32Read4B(DRAMC_ADDR_SHIFT_CHN(DRAMC_REG_TEST2_A3, channel)) & 0xFFFFFFF0;
vIO32Write4B(DRAMC_ADDR_SHIFT_CHN(DRAMC_REG_TEST2_A3, channel), temp | 0x1);
// set base address for test agent to reserved space
dram_addr.ch = channel;
dram_addr.rk = 0;
temp = (u4IO32Read4B(DRAMC_ADDR_SHIFT_CHN(DRAMC_REG_RK_TEST2_A1, channel)) & 0x00000007);
@ -1727,11 +1703,11 @@ void init_ta2_single_channel(unsigned int channel)
temp = (u4IO32Read4B(DRAMC_ADDR_SHIFT_CHN(DRAMC_REG_RK_TEST2_A1+0x200, channel)) & 0x00000007);
vIO32Write4B(DRAMC_ADDR_SHIFT_CHN(DRAMC_REG_RK_TEST2_A1+0x200, channel), temp | get_ta2_addr(&dram_addr));
// set test length (offset) to 0x20
temp = (u4IO32Read4B(DRAMC_ADDR_SHIFT_CHN(DRAMC_REG_TEST2_A2, channel)) & 0x0000000F) | (0x20 << 4);
vIO32Write4B(DRAMC_ADDR_SHIFT_CHN(DRAMC_REG_TEST2_A2, channel), temp);
// set TA2 pattern to the worst case
test_cnt = (get_dram_rank_nr() > 1) ? 1 : 0;
vIO32WriteFldAlign(DRAMC_ADDR_SHIFT_CHN(DRAMC_REG_TEST2_A3, channel), 0, TEST2_A3_TESTAUDPAT);
vIO32WriteFldAlign(DRAMC_ADDR_SHIFT_CHN(DRAMC_REG_TEST2_A3, channel), test_cnt, TEST2_A3_TESTCNT);
@ -1759,7 +1735,7 @@ void update_last_dramc_info(void)
unsigned int *curr;
DRAMC_CTX_T *p = psCurrDramCtx;
// init checksum and magic pattern
if(last_dramc_info_ptr->ta2_result_magic != LAST_DRAMC_MAGIC_PATTERN) {
last_dramc_info_ptr->ta2_result_magic = LAST_DRAMC_MAGIC_PATTERN;
last_dramc_info_ptr->ta2_result_last = 0;
@ -1776,9 +1752,9 @@ void update_last_dramc_info(void)
last_dramc_info_ptr->ta2_result_checksum ^= last_dramc_info_ptr->reboot_count;
}
// TODO: check DCS status
// read data from latch register and reset
for (chn = 0; chn < CHANNEL_NUM; ++chn) {
//dramc_crit("[LastDRAMC] latch result before RST: %x\n", u4IO32Read4B(DRAMC_ADDR_SHIFT_CHN(DRAMC_REG_WDT_DBG_SIGNAL, chn)));
latch_result = (latch_result << 16) | u4IO32Read4B(DRAMC_ADDR_SHIFT_CHN(DRAMC_REG_WDT_DBG_SIGNAL, chn)) & 0xFFFF;
@ -1806,11 +1782,11 @@ void init_ta2_all_channel(void)
update_last_dramc_info();
//cache flush after update dramc info
#if CFG_ENABLE_DCACHE
plat_clean_invalidate_dcache();
#endif
// TODO: consider DCS
for (chn = 0; chn < CHANNEL_NUM; ++chn)
init_ta2_single_channel(chn);
}
@ -1845,7 +1821,7 @@ void dram_fatal_exception_detection_start(void)
last_dramc_info_ptr = (LAST_DRAMC_INFO_T *) get_dbg_info_base(KEY_LAST_DRAMC);
#if SUPPORT_SAVE_TIME_FOR_CALIBRATION
part_dram_data_addr = get_part_addr("boot_para") + 0x100000; // addr = 0x108000
part_dram_data_addr = get_part_addr("boot_para") + 0x100000;
if (part_dram_data_addr != 0x0)
dramc_crit("[dramc] init partition address is 0x%llx\n", part_dram_data_addr);
else {
@ -1859,7 +1835,7 @@ void dram_fatal_exception_detection_start(void)
if ((g_boot_reason == BR_POWER_KEY) || (g_boot_reason == BR_USB)
|| mtk_wdt_is_pmic_full_reset() || (is_last_dramc_initialized() == 0)){
/* cold boot: initialize last_dram_fatal_err_flag and dram_fatal_err_flag */
dramc_crit("[dramc] init SRAM region for DRAM exception detection\n");
last_dramc_info_ptr->last_fatal_err_flag = 0x0;
last_dramc_info_ptr->storage_api_err_flag = 0x0;
@ -1968,7 +1944,7 @@ void dram_fatal_set_err(unsigned int err_code, unsigned int mask, unsigned int o
#endif
#if (FOR_DV_SIMULATION_USED==0) // for DV sim build pass
#if (FOR_DV_SIMULATION_USED==0)
int doe_get_config(const char* feature)
{
#if defined(ENABLE_DOE)
@ -2000,9 +1976,9 @@ void log_to_storage(const char c)
if (log_start && (!logen)) {
logen = 1;
logcount = 0;
part_dram_data_addr_uart = get_part_addr("boot_para") + 0x100000; // addr = 0x1f300000, the first 1MB for debug
part_dram_data_addr_uart = get_part_addr("boot_para") + 0x100000;
memset(&logbuf, 0, sizeof(logbuf));
for (clr_count = 0; clr_count < 3072 ; clr_count++) //3M
for (clr_count = 0; clr_count < 3072 ; clr_count++)
ret = blkdev_write(bootdev, (part_dram_data_addr_uart + (1024 * clr_count)), 1024, (u8*)&logbuf, storage_get_part_id(STORAGE_PHYS_PART_USER));
}
@ -2012,7 +1988,7 @@ void log_to_storage(const char c)
// else
logbuf[logcount] = (char) c;
logcount = logcount + 1;
//write to storage
if (logcount==1024) {
logcount = 0;
ret = blkdev_write(bootdev, part_dram_data_addr_uart, 1024, (u8*)&logbuf, storage_get_part_id(STORAGE_PHYS_PART_USER));
@ -2048,7 +2024,7 @@ static u16 crc16(const u8* data, u32 length){
static void assign_checksum_for_dram_data(DRAM_CALIBRATION_SHU_DATA_T *shu_data)
{
/* need to initialize checksum to 0 before calculation */
shu_data->checksum = 0;
shu_data->checksum = crc16((u8*)shu_data, sizeof(*shu_data));
}
@ -2065,7 +2041,7 @@ static int check_checksum_for_dram_data(DRAM_CALIBRATION_SHU_DATA_T *shu_data)
#if !__ETT__
static void assign_checksum_for_mdl_data(DRAM_CALIBRATION_MRR_DATA_T *mrr_info)
{
/* need to initialize checksum to 0 before calculation */
mrr_info->checksum = 0;
mrr_info->checksum = crc16((u8*)mrr_info, sizeof(*mrr_info));
}
@ -2118,7 +2094,7 @@ int read_offline_dram_calibration_data(DRAM_DFS_SRAM_SHU_T shuffle, SAVE_TIME_FO
dramc_info("read calibration data from shuffle %d(For verify: WL B0:%u, B1: %u)\n",
shuffle, params->wr_level[CHANNEL_A][RANK_0][0], params->wr_level[CHANNEL_B][RANK_0][0]);
/* copy the data stored in storage to the data structure for calibration */
memcpy(offLine_SaveData, params, sizeof(*offLine_SaveData));
fastk_data_dump(params, shuffle);
@ -2137,7 +2113,7 @@ int clean_dram_calibration_data(void)
#else
#if 0
DRAM_CALIBRATION_DATA_T dram_data; // using global variable to avoid stack overflow
DRAM_CALIBRATION_DATA_T dram_data;
static int read_offline_dram_mdl_data(DRAM_INFO_BY_MRR_T *DramInfo)
{
@ -2273,24 +2249,24 @@ unsigned int get_mr8_by_mrr(U8 channel, U8 rank)
}
#endif
/* Get Channel Number from AUXADC */
#if DRAM_AUXADC_CONFIG
static unsigned int get_ch_num_by_auxadc(void)
{
unsigned int ret = 0, voltage = 0;//, u1ch_num = 0;
unsigned int ret = 0, voltage = 0;
ret = iio_read_channel_processed(5, &voltage);
if (ret == 0) {
if (voltage < 700) /* 4CH with DSC */
if (voltage < 700)
{
channel_num_auxadc = CHANNEL_FOURTH;
dram_type_auxadc = PINMUX_DSC;
}
else if (voltage >= 700 && voltage < 1200) /* 2CH with eMCP */
else if (voltage >= 700 && voltage < 1200)
{
channel_num_auxadc = CHANNEL_DUAL;
dram_type_auxadc = PINMUX_EMCP;
}
else /* 2CH with DSC*/
else
{
channel_num_auxadc = CHANNEL_DUAL;
dram_type_auxadc = PINMUX_DSC;

314
src/vendorcode/mediatek/mt8195/dramc/dramc_tracking.c
View File

@ -14,20 +14,20 @@
// Global variables
//-----------------------------------------------------------------------------
//U8 gu1MR23Done = FALSE; /* Not used starting from Vinson (all freqs use MR23=0x3F) */
//U8 gu1MR23Done = FALSE;
U8 gu1MR23[CHANNEL_NUM][RANK_MAX];
/* DQSOSCTHRD_INC & _DEC are 12 bits (Starting from Vinson) */
U16 gu2DQSOSCTHRD_INC[CHANNEL_NUM][RANK_MAX];
U16 gu2DQSOSCTHRD_DEC[CHANNEL_NUM][RANK_MAX];
U16 gu2MR18[CHANNEL_NUM][RANK_MAX]; /* Stores MRR MR18 (DQS ocillator count - MSB) */
U16 gu2MR19[CHANNEL_NUM][RANK_MAX]; /* Stores MRR MR19 (DQS ocillator count - LSB) */
U16 gu2DQSOSC[CHANNEL_NUM][RANK_MAX]; /* Stores tDQSOSC results */
U16 gu2MR18[CHANNEL_NUM][RANK_MAX];
U16 gu2MR19[CHANNEL_NUM][RANK_MAX];
U16 gu2DQSOSC[CHANNEL_NUM][RANK_MAX];
U16 gu2DQSOscCnt[CHANNEL_NUM][RANK_MAX][2];
void DramcDQSOSCInit(void)
{
memset(gu1MR23, 0x3F, sizeof(gu1MR23)); /* MR23 should be 0x3F for all freqs (Starting from Vinson) */
memset(gu1MR23, 0x3F, sizeof(gu1MR23));
memset(gu2DQSOSCTHRD_INC, 0x6, sizeof(gu2DQSOSCTHRD_INC));
memset(gu2DQSOSCTHRD_DEC, 0x4, sizeof(gu2DQSOSCTHRD_DEC));
}
@ -44,14 +44,12 @@ static DRAM_STATUS_T DramcStartDQSOSC_SCSM(DRAMC_CTX_T *p)
u4MRSRKBak = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL0), SWCMD_CTRL0_MRSRK);
//!!R_DMMRSRK(R_DMMPCRKEN=1) specify rank0 or rank1
vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_DQSOSCR), 0, DQSOSCR_DQSOSC2RK);
vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL0), u1GetRank(p), SWCMD_CTRL0_MRSRK);
vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_MPC_OPTION), 1, MPC_OPTION_MPCRKEN);
//R_DMDQSOSCENEN, 0x1E4[10]=1 for DQSOSC Start
//Wait dqsoscen_response=1 (dramc_conf_nao, 0x3b8[29])
//R_DMDQSOSCENEN, 0x1E4[10]=0
vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), 1, SWCMD_EN_DQSOSCENEN);
do
@ -65,7 +63,7 @@ static DRAM_STATUS_T DramcStartDQSOSC_SCSM(DRAMC_CTX_T *p)
vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL0), u4MRSRKBak, SWCMD_CTRL0_MRSRK);
if (u4TimeCnt == 0)//time out
if (u4TimeCnt == 0)
{
mcSHOW_ERR_MSG(("Start fail (time out)\n"));
return DRAM_FAIL;
@ -106,7 +104,7 @@ static DRAM_STATUS_T DramcStartDQSOSC_RTSWCMD(DRAMC_CTX_T *p)
vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_MPC_CTRL),
0, MPC_CTRL_RTSWCMD_HPRI_EN);
if (u4TimeCnt == 0)//time out
if (u4TimeCnt == 0)
{
mcSHOW_ERR_MSG(("[LP5 RT SW Cmd MRW ] Resp fail (time out)\n"));
return DRAM_FAIL;
@ -123,27 +121,27 @@ static DRAM_STATUS_T DramcStartDQSOSC_SWCMD(DRAMC_CTX_T *p)
U32 u4TimeCnt = TIME_OUT_CNT;
U32 u4RegBackupAddress[] = {DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL0), DRAMC_REG_ADDR(DRAMC_REG_DRAMC_PD_CTRL), DRAMC_REG_ADDR(DRAMC_REG_CKECTRL)};
// Backup rank, CKE fix on/off, HW MIOCK control settings
DramcBackupRegisters(p, u4RegBackupAddress, sizeof(u4RegBackupAddress)/sizeof(U32));
mcSHOW_DBG_MSG4(("[ZQCalibration]\n"));
//mcFPRINTF((fp_A60501, "[ZQCalibration]\n"));
// Disable HW MIOCK control to make CLK always on
DramCLKAlwaysOnOff(p, ON, TO_ONE_CHANNEL);
mcDELAY_US(1);
//if CKE2RANK=1, only need to set CKEFIXON, it will apply to both rank.
CKEFixOnOff(p, TO_ALL_RANK, CKE_FIXON, TO_ONE_CHANNEL);
//ZQCAL Start
vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), 1, SWCMD_EN_WCK2DQI_START_SWTRIG);
do
{
u4Response = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SPCMDRESP3), SPCMDRESP3_WCK2DQI_START_SWTRIG_RESPONSE);
u4TimeCnt --;
mcDELAY_US(1); // Wait tZQCAL(min) 1us or wait next polling
mcDELAY_US(1);
mcSHOW_DBG_MSG4(("%d- ", u4TimeCnt));
//mcFPRINTF((fp_A60501, "%d- ", u4TimeCnt));
@ -158,7 +156,7 @@ static DRAM_STATUS_T DramcStartDQSOSC_SWCMD(DRAMC_CTX_T *p)
return DRAM_FAIL;
}
// Restore rank, CKE fix on, HW MIOCK control settings
DramcRestoreRegisters(p, u4RegBackupAddress, sizeof(u4RegBackupAddress)/sizeof(U32));
mcSHOW_DBG_MSG4(("\n[DramcZQCalibration] Done\n\n"));
@ -174,7 +172,7 @@ static DRAM_STATUS_T DramcStartDQSOSC(DRAMC_CTX_T *p)
return DramcStartDQSOSC_SCSM(p);
#elif DQSOSC_RTSWCMD
return DramcStartDQSOSC_RTSWCMD(p);
#else //DQSOSC_SWCMD
#else
return DramcStartDQSOSC_SWCMD(p);
#endif
}
@ -194,16 +192,14 @@ DRAM_STATUS_T DramcDQSOSCAuto(DRAMC_CTX_T *p)
u4RegBak[0] = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_DRAMC_PD_CTRL));
u4RegBak[1] = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_CKECTRL));
//LPDDR4-3200, PI resolution = tCK/64 =9.76ps
//Only if MR23>=16, then error < PI resolution.
//Set MR23 == 0x3f, stop after 63*16 clock
//vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_MRS), u1GetRank(p), MRS_MRSRK);
DramcModeRegWriteByRank(p, p->rank, 23, u1MR23);
//SW mode
vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_DQSOSC_SET0), 1, SHU_DQSOSC_SET0_DQSOSCENDIS);
// Disable HW MIOCK control to make CLK always on
DramCLKAlwaysOnOff(p, ON, TO_ONE_CHANNEL);
CKEFixOnOff(p, p->rank, CKE_FIXON, TO_ONE_CHANNEL);
@ -215,17 +211,17 @@ DRAM_STATUS_T DramcDQSOSCAuto(DRAMC_CTX_T *p)
DramcModeRegReadByRank(p, p->rank, 19, &u2MR19);
#if (SW_CHANGE_FOR_SIMULATION == 0)
//B0
u2DQSCnt = (u2MR18 & 0x00FF) | ((u2MR19 & 0x00FF) << 8);
if (u2DQSCnt != 0)
u2DQSOsc[0] = u1MR23 * 16 * 1000000 / (2 * u2DQSCnt * DDRPhyGetRealFreq(p)); //tDQSOSC = 16*MR23*tCK/2*count
u2DQSOsc[0] = u1MR23 * 16 * 1000000 / (2 * u2DQSCnt * DDRPhyGetRealFreq(p));
else
u2DQSOsc[0] = 0;
//B1
u2DQSCnt = (u2MR18 >> 8) | ((u2MR19 & 0xFF00));
if (u2DQSCnt != 0)
u2DQSOsc[1] = u1MR23 * 16 * 1000000 / (2 * u2DQSCnt * DDRPhyGetRealFreq(p)); //tDQSOSC = 16*MR23*tCK/2*count
u2DQSOsc[1] = u1MR23 * 16 * 1000000 / (2 * u2DQSCnt * DDRPhyGetRealFreq(p));
else
u2DQSOsc[1] = 0;
mcSHOW_DBG_MSG2(("[DQSOSCAuto] RK%d, (LSB)MR18= 0x%x, (MSB)MR19= 0x%x, tDQSOscB0 = %d ps tDQSOscB1 = %d ps\n", u1GetRank(p), u2MR18, u2MR19, u2DQSOsc[0], u2DQSOsc[1]));
@ -246,14 +242,11 @@ DRAM_STATUS_T DramcDQSOSCAuto(DRAMC_CTX_T *p)
#if ENABLE_TX_TRACKING
/* Using gu2DQSOSC results calculated from DramcDQSOSCAuto
* -> calculate DQSOSCTHRD_INC, DQSOSCTHRD_DEC
* _INC, _DEC formulas are extracted from "Verification plan of Vinson LPDDR4 HW TX Tracking" doc
*/
DRAM_STATUS_T DramcDQSOSCMR23(DRAMC_CTX_T *p)
{
#if (SW_CHANGE_FOR_SIMULATION == 0)
/* Preloader doesn't support floating point numbers -> Manually expand/simpify _INC, _DEC formula */
U8 u1MR23 = gu1MR23[p->channel][p->rank];
U16 u2DQSOSC = gu2DQSOSC[p->channel][p->rank];
U32 u4tCK = 1000000 / DDRPhyGetRealFreq(p);
@ -272,16 +265,16 @@ DRAM_STATUS_T DramcDQSOSCMR23(DRAMC_CTX_T *p)
}
/* Sets DQSOSC_BASE for specified rank/byte */
DRAM_STATUS_T DramcDQSOSCSetMR18MR19(DRAMC_CTX_T *p)
{
U16 u2DQSOscCnt[2];
DramcDQSOSCAuto(p);
//B0
gu2DQSOscCnt[p->channel][p->rank][0] = u2DQSOscCnt[0] = (gu2MR18[p->channel][p->rank] & 0x00FF) | ((gu2MR19[p->channel][p->rank] & 0x00FF) << 8);
//B1
gu2DQSOscCnt[p->channel][p->rank][1] = u2DQSOscCnt[1] = (gu2MR18[p->channel][p->rank] >> 8) | ((gu2MR19[p->channel][p->rank] & 0xFF00));
if ((p->dram_cbt_mode[p->rank] == CBT_NORMAL_MODE) && (gu2DQSOscCnt[p->channel][p->rank][1] == 0))
@ -359,7 +352,7 @@ DRAM_STATUS_T DramcDQSOSCShuSettings(DRAMC_CTX_T *p)
u1FILT_PITHRD = 0x12;
u1W2R_SEL = 0x2;
}
else //4266
else
{
u1FILT_PITHRD = 0x17;
u1W2R_SEL = 0x2;
@ -372,7 +365,7 @@ DRAM_STATUS_T DramcDQSOSCShuSettings(DRAMC_CTX_T *p)
}
u1DQSOSCRCNT = ((p->frequency<< u1IsDiv4))/100;
if ((p->frequency%100) != 0) // @Darren, Round up for tOSCO timing (40ns)
if ((p->frequency%100) != 0)
u1DQSOSCRCNT++;
if (gu1MR23[p->channel][RANK_1] > gu1MR23[p->channel][RANK_0])
@ -385,16 +378,15 @@ DRAM_STATUS_T DramcDQSOSCShuSettings(DRAMC_CTX_T *p)
if (u1RoundUp != 0)
u2PRDCNT++;
//Don't power down dram during DQS interval timer run time, (MR23[7:0] /4) + (tOSCO/MCK unit/16)
vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_DQSOSC_SET0), u2PRDCNT, SHU_DQSOSC_SET0_DQSOSC_PRDCNT); //@Darren, unit: 16MCK and tOSCO=40ns/MCK
//set tOSCO constraint to read MR18/MR19, should be > 40ns/MCK
vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_DQSOSCR), u1DQSOSCRCNT, SHU_DQSOSCR_DQSOSCRCNT);//@Darren, unit: MCK to meet spec. tOSCO=40ns/MCK
vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_DQSOSC_SET0), u2PRDCNT, SHU_DQSOSC_SET0_DQSOSC_PRDCNT);
vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_DQSOSCR), u1DQSOSCRCNT, SHU_DQSOSCR_DQSOSCRCNT);
vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_TX_SET0), (u1FILT_PITHRD>>1), SHU_TX_SET0_DQS2DQ_FILT_PITHRD);
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_TX_SET0), P_Fld(u1W2R_SEL, SHU_TX_SET0_TXUPD_W2R_SEL) | P_Fld(0x0, SHU_TX_SET0_TXUPD_SEL));
/* Starting from Vinson, DQSOSCTHRD_INC & _DEC is split into RK0 and RK1 */
//Rank 0/1
for (u1RankIdx = RANK_0; u1RankIdx < p->support_rank_num; u1RankIdx++)
{
vSetRank(p, u1RankIdx);
@ -403,8 +395,7 @@ DRAM_STATUS_T DramcDQSOSCShuSettings(DRAMC_CTX_T *p)
}
vSetRank(p, u1RankIdxBak);
//set interval to do MPC(start DQSOSC) command, and dramc send DQSOSC start to rank0/1/2 at the same time
//TX tracking period unit: 3.9us
vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_DQSOSC_SET0), u2DQSOSCENCNT, SHU_DQSOSC_SET0_DQSOSCENCNT);
return DRAM_OK;
@ -415,22 +406,22 @@ void DramcHwDQSOSC(DRAMC_CTX_T *p)
DRAM_RANK_T rank_bak = u1GetRank(p);
DRAM_CHANNEL_T ch_bak = p->channel;
//Enable TX tracking new mode
vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TX_FREQ_RATIO_OLD_MODE0), 1, TX_FREQ_RATIO_OLD_MODE0_SHUFFLE_LEVEL_MODE_SELECT);
//Enable Freq_RATIO update
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TX_TRACKING_SET0), P_Fld(1, TX_TRACKING_SET0_SHU_PRELOAD_TX_HW)
| P_Fld(0, TX_TRACKING_SET0_SHU_PRELOAD_TX_START)
| P_Fld(0, TX_TRACKING_SET0_SW_UP_TX_NOW_CASE));
//DQSOSC MPC command violation
#if ENABLE_TMRRI_NEW_MODE
vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_MPC_CTRL), 1, MPC_CTRL_MPC_BLOCKALE_OPT);
#else
vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_MPC_CTRL), 0, MPC_CTRL_MPC_BLOCKALE_OPT);
#endif
//DQS2DQ UI/PI setting controlled by HW
#if ENABLE_SW_TX_TRACKING
vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CTRL1), 1, MISC_CTRL1_R_DMARPIDQ_SW);
#else
@ -441,15 +432,14 @@ void DramcHwDQSOSC(DRAMC_CTX_T *p)
#endif
vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_DQSOSCR), 1, DQSOSCR_ARUIDQ_SW);
//Set dqsosc oscillator run time by MRW
//write RK0 MR23
#if 0
vSetRank(p, RANK_0);
vSetPHY2ChannelMapping(p, CHANNEL_A);
DramcModeRegWrite(p, 23, u1MR23);
vSetPHY2ChannelMapping(p, CHANNEL_B);
DramcModeRegWrite(p, 23, u1MR23);
//write RK1 MR23
vSetRank(p, RANK_1);
vSetPHY2ChannelMapping(p, CHANNEL_A);
DramcModeRegWrite(p, 23, u1MR23);
@ -457,7 +447,7 @@ void DramcHwDQSOSC(DRAMC_CTX_T *p)
DramcModeRegWrite(p, 23, u1MR23);
#endif
//Enable HW read MR18/MR19 for each rank
#if ENABLE_SW_TX_TRACKING
vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_DQSOSCR), 1, DQSOSCR_DQSOSCRDIS);
#else
@ -472,8 +462,8 @@ void DramcHwDQSOSC(DRAMC_CTX_T *p)
vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_RK_DQSOSC), 1, RK_DQSOSC_DQSOSCR_RK0EN);
}
//@Jouling, Update MP setting
vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TX_SET0), 1, TX_SET0_DRSCLR_RK0_EN); //Set as 1 to fix issue of RANK_SINGLE, dual rank can also be enable
vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TX_SET0), 1, TX_SET0_DRSCLR_RK0_EN);
vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_DQSOSCR), 1, DQSOSCR_DQSOSC_CALEN);
@ -483,7 +473,7 @@ void DramcHwDQSOSC(DRAMC_CTX_T *p)
void Enable_TX_Tracking(DRAMC_CTX_T *p)
{
//open loop mode and semi-open do not enable tracking
if (u1IsPhaseMode(p) == TRUE)
{
vIO32WriteFldAlign_All(DRAMC_REG_SHU_DQSOSC_SET0, 1, SHU_DQSOSC_SET0_DQSOSCENDIS);
@ -498,8 +488,8 @@ void Enable_TX_Tracking(DRAMC_CTX_T *p)
#if RDSEL_TRACKING_EN
void Enable_RDSEL_Tracking(DRAMC_CTX_T *p, U16 u2Freq)
{
//Only enable at DDR4266
if (u2Freq >= RDSEL_TRACKING_TH) //add if(u1ShuffleIdx==DRAM_DFS_SRAM_MAX) to avoid enable tx-tracking when running DDR800 as RG-SHU0
if (u2Freq >= RDSEL_TRACKING_TH)
{
vIO32WriteFldAlign_All(DDRPHY_REG_SHU_MISC_RDSEL_TRACK, 0x0, SHU_MISC_RDSEL_TRACK_RDSEL_TRACK_EN);
vIO32WriteFldMulti_All(DDRPHY_REG_SHU_MISC_RDSEL_TRACK, P_Fld(0x1, SHU_MISC_RDSEL_TRACK_RDSEL_TRACK_EN)
@ -515,7 +505,7 @@ void Enable_RDSEL_Tracking(DRAMC_CTX_T *p, U16 u2Freq)
#ifdef HW_GATING
void Enable_Gating_Tracking(DRAMC_CTX_T *p)
{
//open loop mode and semi-open do not enable tracking
if (u1IsPhaseMode(p) == TRUE)
{
vIO32WriteFldMulti_All(DDRPHY_REG_MISC_SHU_STBCAL,
@ -552,14 +542,14 @@ void Enable_ClkTxRxLatchEn(DRAMC_CTX_T *p)
else
vIO32WriteFldAlign_All(DDRPHY_REG_SHU_CA_CMD10, 1, SHU_CA_CMD10_RG_RX_ARCLK_DLY_LAT_EN_CA);
// Set 1 to be make TX DQS/DQ/DQM PI take effect when TX OE low, for new cross rank mode.
vIO32WriteFldAlign_All(DDRPHY_REG_SHU_B0_DQ2, 1, SHU_B0_DQ2_RG_ARPI_OFFSET_LAT_EN_B0);
if (!isLP4_DSC)
vIO32WriteFldAlign_All(DDRPHY_REG_SHU_B1_DQ2, 1, SHU_B1_DQ2_RG_ARPI_OFFSET_LAT_EN_B1);
else
vIO32WriteFldAlign_All(DDRPHY_REG_SHU_CA_CMD2, 1, SHU_CA_CMD2_RG_ARPI_OFFSET_LAT_EN_CA);
// Default settings before init
vIO32WriteFldAlign_All(DDRPHY_REG_SHU_B0_DQ11, 1, SHU_B0_DQ11_RG_RX_ARDQ_OFFSETC_LAT_EN_B0);
vIO32WriteFldAlign_All(DDRPHY_REG_SHU_B1_DQ11, 1, SHU_B1_DQ11_RG_RX_ARDQ_OFFSETC_LAT_EN_B1);
vIO32WriteFldAlign_All(DDRPHY_REG_SHU_CA_CMD11, 1, SHU_CA_CMD11_RG_RX_ARCA_OFFSETC_LAT_EN_CA);
@ -578,7 +568,7 @@ void Enable_ClkTxRxLatchEn(DRAMC_CTX_T *p)
}
}
#if ENABLE_TX_WDQS // @Darren, To avoid unexpected DQS toggle during calibration
#if ENABLE_TX_WDQS
void Enable_TxWDQS(DRAMC_CTX_T *p)
{
BOOL isLP4_DSC = (p->DRAMPinmux == PINMUX_DSC)?1:0;
@ -609,8 +599,8 @@ static void Enable_and_Trigger_TX_Retry(DRAMC_CTX_T *p)
| P_Fld(0, TX_RETRY_SET0_TX_RETRY_UPDPI_CG_OPT)
| P_Fld(1, TX_RETRY_SET0_XSR_TX_RETRY_OPT)
| P_Fld(0, TX_RETRY_SET0_XSR_TX_RETRY_EN)
| P_Fld(0, TX_RETRY_SET0_XSR_TX_RETRY_SW_EN)); //If using SW mode, don;t have to set this field
//open loop mode and semi-open do not enable tracking
| P_Fld(0, TX_RETRY_SET0_XSR_TX_RETRY_SW_EN));
if (u1IsPhaseMode(p) == TRUE)
{
vIO32WriteFldAlign_All(DRAMC_REG_SHU_DQSOSC_SET0, 1, SHU_DQSOSC_SET0_DQSOSCENDIS);
@ -722,8 +712,7 @@ void DramcSWTxTracking(DRAMC_CTX_T *p)
u2MR1819_Runtime[p->rank][1] = u2MR1819_Runtime[p->rank][0];
}
//INC : MR1819>base. PI-
//DEC : MR1819<base. PI+
for (byteIdx = 0; byteIdx < 2; byteIdx++)
{
U16 deltaMR1819 = 0;
@ -828,16 +817,8 @@ void DramcRxInputDelayTrackingInit_byFreq(DRAMC_CTX_T *p)
U32 u4WbrBackup = GetDramcBroadcast();
DramcBroadcastOnOff(DRAMC_BROADCAST_ON);
//Monitor window size setting
//DDRPHY.SHU*_B*_DQ5.RG_RX_ARDQS0_DVS_DLY_B* (suggested value from A-PHY owner)
//WHITNEY_TO_BE_PORTING
#if (fcFOR_CHIP_ID == fc8195)
// 6400 5500 4266 3733 3200 2400 1600 1200 800
//UI 156p 181p 234p 268p 312p 417p 625p 833p 1250p
//DVS_EN O O O O O O X X X
//INI 1 2 3 N=5 N=5 N=7 N=12 N=15 N=15
//DVS delay O O O X X X X X X
//calibration
if(p->frequency >= 3200)
{
@ -874,12 +855,12 @@ void DramcRxInputDelayTrackingInit_byFreq(DRAMC_CTX_T *p)
#if RX_DVS_NOT_SHU_WA
if (isLP4_DSC)
{
//CA_CMD5_RG_RX_ARCLK_DVS_EN is not shu RG, so always enable. Fixed in IPMv2
u1DVS_En =1;
}
#endif
//Note that DVS DLY is _DQS_ and DVS_EN is _DQ_
vIO32WriteFldAlign((DDRPHY_REG_SHU_B0_DQ5), u1DVS_Delay, SHU_B0_DQ5_RG_RX_ARDQS0_DVS_DLY_B0);
if (!isLP4_DSC)
{
@ -890,13 +871,12 @@ void DramcRxInputDelayTrackingInit_byFreq(DRAMC_CTX_T *p)
vIO32WriteFldAlign((DDRPHY_REG_SHU_CA_CMD5), u1DVS_Delay, SHU_CA_CMD5_RG_RX_ARCLK_DVS_DLY);
}
/* Bian_co HW design issue: run-time PBYTE flag will lose it's function and become per-bit -> set to 0 */
vIO32WriteFldMulti((DDRPHY_REG_SHU_B0_DQ7), P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B0)
| P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B0));
vIO32WriteFldMulti((DDRPHY_REG_SHU_B1_DQ7), P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B1)
| P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B1));
//Note that DVS DLY is _DQS_ and DVS_EN is _DQ_
//Enable A-PHY DVS LEAD/LAG
vIO32WriteFldAlign((DDRPHY_REG_SHU_B0_DQ11), u1DVS_En, SHU_B0_DQ11_RG_RX_ARDQ_DVS_EN_B0);
if (!isLP4_DSC)
{
@ -911,13 +891,12 @@ void DramcRxInputDelayTrackingInit_byFreq(DRAMC_CTX_T *p)
}
#endif
///TODO: wait for porting +++
#if __A60868_TO_BE_PORTING__
#if RX_DLY_TRACK_ONLY_FOR_DEBUG
void DramcRxDlyTrackDebug(DRAMC_CTX_T *p)
{
/* indicate ROW_ADR = 2 for dummy write & read for Rx dly track debug feature, avoid pattern overwrite by MEM_TEST
* pattern(0xAAAA5555) locates: 0x40010000, 0x40010100, 0x80010000, 0x80010100 */
vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DRAMC_REG_RK0_DUMMY_RD_ADR), P_Fld(2, RK0_DUMMY_RD_ADR_DMY_RD_RK0_ROW_ADR)
| P_Fld(0, RK0_DUMMY_RD_ADR_DMY_RD_RK0_COL_ADR)
@ -937,16 +916,16 @@ void DramcRxDlyTrackDebug(DRAMC_CTX_T *p)
vIO32Write4B_All(DRAMC_REG_RK1_DUMMY_RD_WDATA2, 0xAAAA5555);
vIO32Write4B_All(DRAMC_REG_RK1_DUMMY_RD_WDATA3, 0xAAAA5555);
//disable Rx dly track debug and clear status lock
vIO32WriteFldMulti_All((DDRPHY_MISC_RXDVS2), P_Fld(0, MISC_RXDVS2_R_DMRXDVS_DBG_MON_EN)
| P_Fld(1, MISC_RXDVS2_R_DMRXDVS_DBG_MON_CLR)
| P_Fld(0, MISC_RXDVS2_R_DMRXDVS_DBG_PAUSE_EN));
//trigger dummy write pattern 0xAAAA5555
vIO32WriteFldAlign_All(DRAMC_REG_DUMMY_RD, 0x1, DUMMY_RD_DMY_WR_DBG);
vIO32WriteFldAlign_All(DRAMC_REG_DUMMY_RD, 0x0, DUMMY_RD_DMY_WR_DBG);
// enable Rx dly track debug feature
vIO32WriteFldMulti_All((DDRPHY_MISC_RXDVS2), P_Fld(1, MISC_RXDVS2_R_DMRXDVS_DBG_MON_EN)
| P_Fld(0, MISC_RXDVS2_R_DMRXDVS_DBG_MON_CLR)
| P_Fld(1, MISC_RXDVS2_R_DMRXDVS_DBG_PAUSE_EN));
@ -955,7 +934,7 @@ void DramcRxDlyTrackDebug(DRAMC_CTX_T *p)
void DramcPrintRxDlyTrackDebugStatus(DRAMC_CTX_T *p)
{
U32 backup_rank, u1ChannelBak, u4value;
U8 u1ChannelIdx, u1ChannelMax = p->support_channel_num;//channel A/B ...
U8 u1ChannelIdx, u1ChannelMax = p->support_channel_num;
u1ChannelBak = p->channel;
backup_rank = u1GetRank(p);
@ -1025,7 +1004,7 @@ void DummyReadForDqsGatingRetryShuffle(DRAMC_CTX_T *p, bool bEn)
{
if (bEn == 1)
{
vIO32WriteFldMulti_All(DDRPHY_REG_MISC_SHU_DQSG_RETRY1, P_Fld(0, MISC_SHU_DQSG_RETRY1_RETRY_ROUND_NUM)//Retry once
vIO32WriteFldMulti_All(DDRPHY_REG_MISC_SHU_DQSG_RETRY1, P_Fld(0, MISC_SHU_DQSG_RETRY1_RETRY_ROUND_NUM)
| P_Fld(1, MISC_SHU_DQSG_RETRY1_XSR_RETRY_SPM_MODE)
| P_Fld(0, MISC_SHU_DQSG_RETRY1_XSR_DQSG_RETRY_EN)
| P_Fld(0, MISC_SHU_DQSG_RETRY1_RETRY_SW_EN)
@ -1049,7 +1028,7 @@ void DummyReadForDqsGatingRetryNonShuffle(DRAMC_CTX_T *p, bool bEn)
if (bEn == 1)
{
vIO32WriteFldAlign_All(DRAMC_REG_TEST2_A4, 4, TEST2_A4_TESTAGENTRKSEL);//Dummy Read rank selection is controlled by Test Agent
vIO32WriteFldAlign_All(DRAMC_REG_TEST2_A4, 4, TEST2_A4_TESTAGENTRKSEL);
vIO32WriteFldMulti_All(DRAMC_REG_DUMMY_RD, P_Fld(1, DUMMY_RD_DQSG_DMYRD_EN)
| P_Fld(p->support_rank_num, DUMMY_RD_RANK_NUM)
| P_Fld(1, DUMMY_RD_DUMMY_RD_SW));
@ -1079,7 +1058,7 @@ void DramcImpedanceHWSaving(DRAMC_CTX_T *p)
void DramcImpedanceTrackingEnable(DRAMC_CTX_T *p)
{
U8 u1CHAB_en = DISABLE;
#if 0 //Impedance tracking offset for DRVP+2
#if 0
vIO32WriteFldMulti_All(DRAMC_REG_IMPEDAMCE_CTRL1, P_Fld(2, IMPEDAMCE_CTRL1_DQS1_OFF) | P_Fld(2, IMPEDAMCE_CTRL1_DOS2_OFF));
vIO32WriteFldMulti_All(DRAMC_REG_IMPEDAMCE_CTRL2, P_Fld(2, IMPEDAMCE_CTRL2_DQ1_OFF) | P_Fld(2, IMPEDAMCE_CTRL2_DQ2_OFF));
#endif
@ -1098,39 +1077,35 @@ void DramcImpedanceTrackingEnable(DRAMC_CTX_T *p)
vIO32WriteFldAlign_All(DDRPHY_REG_MISC_IMP_CTRL1, 1, MISC_IMP_CTRL1_IMP_ABN_LAT_EN);
#endif
//Write (DRAMC _BASE+ 0x8B) [31:0] = 32'he4000000//enable impedance tracking
//u1CHAB_en = (p->support_channel_num == CHANNEL_DUAL) ? ENABLE : DISABLE;
vIO32WriteFldAlign_All(DDRPHY_REG_MISC_CTRL0, u1CHAB_en, MISC_CTRL0_IMPCAL_CHAB_EN);//Set CHA this bit to enable dual channel tracking
//During shuffle, after CH_A IMP update done, CH_B has no enough time to update (IMPCAL_IMPCAL_DRVUPDOPT=1)
//enable ECO function for impedance load last tracking result of previous shuffle level (IMPCAL_IMPCAL_CHGDRV_ECO_OPT=1)
//enable ECO function for impcal_sm hange when DRVP>=0x1D (IMPCAL_IMPCAL_SM_ECO_OPT=1)
//u1CHAB_en = (p->support_channel_num == CHANNEL_DUAL) ? ENABLE : DISABLE;
vIO32WriteFldAlign_All(DDRPHY_REG_MISC_CTRL0, u1CHAB_en, MISC_CTRL0_IMPCAL_CHAB_EN);
vIO32WriteFldMulti_All(DDRPHY_REG_MISC_IMPCAL, P_Fld(1, MISC_IMPCAL_IMPCAL_HW) | P_Fld(0, MISC_IMPCAL_IMPCAL_EN) |
P_Fld(1, MISC_IMPCAL_IMPCAL_SWVALUE_EN) | P_Fld(1, MISC_IMPCAL_IMPCAL_NEW_OLD_SL) |
P_Fld(1, MISC_IMPCAL_IMPCAL_DRVUPDOPT) | P_Fld(1, MISC_IMPCAL_IMPCAL_CHGDRV_ECO_OPT) |
P_Fld(1, MISC_IMPCAL_IMPCAL_SM_ECO_OPT) | P_Fld(1, MISC_IMPCAL_IMPBINARY) |
P_Fld(1, MISC_IMPCAL_DRV_ECO_OPT));
//dual channel continuously tracking @ system busy, self-refresh, Hhbrid-S1
//vIO32WriteFldAlign_All(DDRPHY_REG_MISC_CTRL0, 0x1, MISC_CTRL0_IMPCAL_LP_ECO_OPT);
//@tg.Only CHA do Impcal tracking, CHB sync CHA result value
vIO32WriteFldMulti(DDRPHY_REG_MISC_CTRL0, P_Fld(0x1, MISC_CTRL0_IMPCAL_LP_ECO_OPT) |
P_Fld(0x0, MISC_CTRL0_IMPCAL_TRACK_DISABLE));
vIO32WriteFldMulti(DDRPHY_REG_MISC_CTRL0 + SHIFT_TO_CHB_ADDR, P_Fld(0x1, MISC_CTRL0_IMPCAL_LP_ECO_OPT) |
P_Fld(0x1, MISC_CTRL0_IMPCAL_TRACK_DISABLE));
// no update imp CA, because CA is unterm now
vIO32WriteFldAlign_All(DDRPHY_REG_MISC_IMPCAL, 1, MISC_IMPCAL_IMPCAL_BYPASS_UP_CA_DRV);
// CH_A set 1, CH_B set 0 (mp setting)
vIO32WriteFldMulti(DDRPHY_REG_MISC_IMPCAL, P_Fld(0, MISC_IMPCAL_DIS_SUS_CH0_DRV) |
P_Fld(1, MISC_IMPCAL_DIS_SUS_CH1_DRV) |
P_Fld(0, MISC_IMPCAL_IMPSRCEXT) | //Update mp setting
P_Fld(1, MISC_IMPCAL_IMPCAL_ECO_OPT)); //Update mp setting
P_Fld(0, MISC_IMPCAL_IMPSRCEXT) |
P_Fld(1, MISC_IMPCAL_IMPCAL_ECO_OPT));
vIO32WriteFldMulti(DDRPHY_REG_MISC_IMPCAL + SHIFT_TO_CHB_ADDR, P_Fld(1, MISC_IMPCAL_DIS_SUS_CH0_DRV) |
P_Fld(0, MISC_IMPCAL_DIS_SUS_CH1_DRV) |
P_Fld(1, MISC_IMPCAL_IMPSRCEXT) | //Update mp setting
P_Fld(0, MISC_IMPCAL_IMPCAL_ECO_OPT)); //Update mp setting
P_Fld(1, MISC_IMPCAL_IMPSRCEXT) |
P_Fld(0, MISC_IMPCAL_IMPCAL_ECO_OPT));
#if (CHANNEL_NUM > 2)
if (channel_num_auxadc > 2) {
vIO32WriteFldMulti(DDRPHY_REG_MISC_IMPCAL + SHIFT_TO_CHC_ADDR, P_Fld(0, MISC_IMPCAL_DIS_SUS_CH0_DRV) | P_Fld(1, MISC_IMPCAL_DIS_SUS_CH1_DRV));
@ -1142,8 +1117,8 @@ void DramcImpedanceTrackingEnable(DRAMC_CTX_T *p)
}
#endif
//Maoauo: keep following setting for SPMFW enable REFCTRL0_DRVCGWREF = 1 (Imp SW Save mode)
vIO32WriteFldAlign_All(DDRPHY_REG_MISC_IMPCAL, 1, MISC_IMPCAL_DRVCGWREF); //@Maoauo, Wait AB refresh to avoid IO drive via logic design
vIO32WriteFldAlign_All(DDRPHY_REG_MISC_IMPCAL, 1, MISC_IMPCAL_DRVCGWREF);
vIO32WriteFldAlign_All(DDRPHY_REG_MISC_IMPCAL, 1, MISC_IMPCAL_DQDRVSWUPD);
}
#endif
@ -1164,9 +1139,9 @@ void DramcPrintIMPTrackingStatus(DRAMC_CTX_T *p, U8 u1Channel)
mcSHOW_DBG_MSG3(("[IMPTrackingStatus] CH=%d\n", p->channel));
// if (u1Channel == CHANNEL_A)
{//460 464: ODTN DRVP, 468 46C: DRVN DRVP
{
//DQS
DQS_DRVN_2 = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_IMPCAL_STATUS2), MISC_IMPCAL_STATUS2_DRVNDQS_SAVE_2);
DQS_DRVP_2 = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_IMPCAL_STATUS2), MISC_IMPCAL_STATUS2_DRVPDQS_SAVE_2);
DQS_ODTN_2 = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_IMPCAL_STATUS2), MISC_IMPCAL_STATUS2_ODTNDQS_SAVE_2);
@ -1174,7 +1149,7 @@ void DramcPrintIMPTrackingStatus(DRAMC_CTX_T *p, U8 u1Channel)
DQS_DRVP = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_IMPCAL_STATUS1), MISC_IMPCAL_STATUS1_DRVPDQS_SAVE_1);
DQS_ODTN = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_IMPCAL_STATUS1), MISC_IMPCAL_STATUS1_ODTNDQS_SAVE_1);
//DQ
DQ_DRVN_2 = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_IMPCAL_STATUS4), MISC_IMPCAL_STATUS4_DRVNDQ_SAVE_2);
DQ_DRVP_2 = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_IMPCAL_STATUS4), MISC_IMPCAL_STATUS4_DRVPDQ_SAVE_2);
DQ_ODTN_2 = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_IMPCAL_STATUS4), MISC_IMPCAL_STATUS4_ODTNDQ_SAVE_2);
@ -1182,7 +1157,7 @@ void DramcPrintIMPTrackingStatus(DRAMC_CTX_T *p, U8 u1Channel)
DQ_DRVP = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_IMPCAL_STATUS3), MISC_IMPCAL_STATUS3_DRVPDQ_SAVE_1);
DQ_ODTN = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_IMPCAL_STATUS3), MISC_IMPCAL_STATUS3_ODTNDQ_SAVE_1);
//CMD
CMD_DRVN_2 = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_IMPCAL_STATUS8), MISC_IMPCAL_STATUS8_DRVNCMD_SAVE_2);
CMD_DRVP_2 = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_IMPCAL_STATUS8), MISC_IMPCAL_STATUS8_DRVPCMD_SAVE_2);
CMD_ODTN_2 = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_IMPCAL_STATUS8), MISC_IMPCAL_STATUS8_ODTNCMD_SAVE_2);
@ -1195,23 +1170,23 @@ void DramcPrintIMPTrackingStatus(DRAMC_CTX_T *p, U8 u1Channel)
{
U8 shu_level;
//Channel B is workaround
shu_level = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHUSTATUS), SHUSTATUS_SHUFFLE_LEVEL);
mcSHOW_DBG_MSG(("shu_level=%d\n", shu_level));
//DQ
DQ_DRVP_2 = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_DRVING1 + shu_level * SHU_GRP_DRAMC_OFFSET), SHU_DRVING1_DQDRV2_DRVP);
DQ_DRVP = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_DRVING2 + shu_level * SHU_GRP_DRAMC_OFFSET), SHU_DRVING2_DQDRV1_DRVP);
DQ_ODTN_2 = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_DRVING3 + shu_level * SHU_GRP_DRAMC_OFFSET), SHU_DRVING3_DQODT2_ODTN);
DQ_ODTN = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_DRVING4 + shu_level * SHU_GRP_DRAMC_OFFSET), SHU_DRVING4_DQODT1_ODTN);
//DQS
DQS_DRVP_2 = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_DRVING1 + shu_level * SHU_GRP_DRAMC_OFFSET), SHU_DRVING1_DQSDRV2_DRVP);
DQS_DRVP = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_DRVING1 + shu_level * SHU_GRP_DRAMC_OFFSET), SHU_DRVING1_DQSDRV1_DRVP);
DQS_ODTN_2 = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_DRVING3 + shu_level * SHU_GRP_DRAMC_OFFSET), SHU_DRVING3_DQSODT2_ODTN);
DQS_ODTN = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_DRVING3 + shu_level * SHU_GRP_DRAMC_OFFSET), SHU_DRVING3_DQSODT1_ODTN);
//CMD
CMD_DRVP_2 = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_DRVING2 + shu_level * SHU_GRP_DRAMC_OFFSET), SHU_DRVING2_CMDDRV2_DRVP);
CMD_DRVP = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_DRVING2 + shu_level * SHU_GRP_DRAMC_OFFSET), SHU_DRVING2_CMDDRV1_DRVP);
CMD_ODTN_2 = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_DRVING4 + shu_level * SHU_GRP_DRAMC_OFFSET), SHU_DRVING4_CMDODT2_ODTN);
@ -1232,9 +1207,7 @@ void DramcPrintIMPTrackingStatus(DRAMC_CTX_T *p, U8 u1Channel)
#endif
}
#endif
/* divRoundClosest() - to round up to the nearest integer
* discard four, but treat five as whole (of decimal points)
*/
int divRoundClosest(const int n, const int d)
{
return ((n < 0) ^ (d < 0))? ((n - d / 2) / d): ((n + d / 2) / d);
@ -1245,10 +1218,10 @@ int divRoundClosest(const int n, const int d)
void FreqJumpRatioCalculation(DRAMC_CTX_T *p)
{
U32 shuffle_src_freq, shuffle_dst_index, jump_ratio_index;
U16 u2JumpRatio[12] = {0}; /* Used to record __DBQUOTE_ANCHOR__ calulation results */
U16 u2JumpRatio[12] = {0};
U16 u2Freq = 0;
/* Calculate jump ratios and save to u2JumpRatio array */
jump_ratio_index = 0;
if (vGet_DDR_Loop_Mode(p) == CLOSE_LOOP_MODE)
@ -1264,7 +1237,7 @@ void FreqJumpRatioCalculation(DRAMC_CTX_T *p)
while (1);
#endif
}
#if 0 //cc mark since been removed in new flow
#if 0
if (pDstFreqTbl->freq_sel == LP4_DDR800)
{
u2JumpRatio[jump_ratio_index] = 0;
@ -1287,7 +1260,7 @@ void FreqJumpRatioCalculation(DRAMC_CTX_T *p)
}
}
/* Save jumpRatios into corresponding register fields */
vIO32WriteFldMulti_All(DRAMC_REG_SHU_FREQ_RATIO_SET0, P_Fld(u2JumpRatio[0], SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO0)
| P_Fld(u2JumpRatio[1], SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO1)
| P_Fld(u2JumpRatio[2], SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO2)
@ -1318,13 +1291,13 @@ void DramcDQSPrecalculation_preset(DRAMC_CTX_T *p)
#if 1//(fcFOR_CHIP_ID == fc8195)
mck2ui = 4;
#else
///TODO: use vGet_Div_Mode() instead later
if (vGet_Div_Mode(p) == DIV16_MODE)
mck2ui = 4; /* 1:16 mode */
mck2ui = 4;
else if (vGet_Div_Mode(p) == DIV8_MODE)
mck2ui = 3; /* 1: 8 mode */
mck2ui = 3;
else
mck2ui = 2; /* 1: 4 mode */
mck2ui = 2;
#endif
mcSHOW_DBG_MSG2(("Pre-setting of DQS Precalculation\n"));
@ -1381,7 +1354,7 @@ void DramcDQSPrecalculation_preset(DRAMC_CTX_T *p)
vSetRank(p, backup_rank);
/* Disable DDR800semi and DDR400open precal */
if (vGet_DDR_Loop_Mode(p) != CLOSE_LOOP_MODE)
{
set_value = 1;
@ -1401,7 +1374,7 @@ void DramcDQSPrecalculation_preset(DRAMC_CTX_T *p)
}
#if 0
void DramcDQSPrecalculation_preset(DRAMC_CTX_T *p)//Test tDQSCK_temp Pre-calculation
void DramcDQSPrecalculation_preset(DRAMC_CTX_T *p)
{
U8 u1ByteIdx, u1RankNum, u1RankBackup = p->rank;
U8 u1ShuLevel = vGet_Current_SRAMIdx(p);
@ -1414,28 +1387,28 @@ void DramcDQSPrecalculation_preset(DRAMC_CTX_T *p)//Test tDQSCK_temp Pre-calcula
mcDUMP_REG_MSG(("Pre-setting of DQS Precalculation\n"));
if ((u1ShuLevel >= SRAM_SHU4) && (u1ShuLevel <= SRAM_SHU7))
{ //SHU4, 5, 6, 7
u1Delay_Addr[0] = ((u1ShuLevel / 6) * 0x4) + 0x30; //Offset of phase0 UI register
u1Delay_Addr[1] = 0x38; //Offset of phase1 UI register
{
u1Delay_Addr[0] = ((u1ShuLevel / 6) * 0x4) + 0x30;
u1Delay_Addr[1] = 0x38;
u2Byte_offset = 0xc;
}
else if (u1ShuLevel >= SRAM_SHU8)
{ //SHU8, 9
u1Delay_Addr[0] = 0x260; //Offset of phase0 UI register
u1Delay_Addr[1] = 0x268; //Offset of phase1 UI register
{
u1Delay_Addr[0] = 0x260;
u1Delay_Addr[1] = 0x268;
u2Byte_offset = 0x4;
}
else //SHU0, 1, 2, 3
else
{
u1Delay_Addr[0] = ((u1ShuLevel / 2) * 0x4); //Offset of phase0 UI register
u1Delay_Addr[1] = 0x8; //Offset of phase1 UI register
u1Delay_Addr[0] = ((u1ShuLevel / 2) * 0x4);
u1Delay_Addr[1] = 0x8;
u2Byte_offset = 0xc;
}
u1Delay_Fld[0] = u1ShuLevel % 2; //Field of phase0 PI and UI
u1Delay_Fld[1] = u1ShuLevel % 4; //Field of phase1 UI
u1Delay_Fld[0] = u1ShuLevel % 2;
u1Delay_Fld[1] = u1ShuLevel % 4;
switch (u1Delay_Fld[0]) //Phase0 UI and PI
switch (u1Delay_Fld[0])
{
case 0:
TransferReg.u4UI_Fld = RK0_PRE_TDQSCK1_TDQSCK_UIFREQ1_B0R0;
@ -1451,17 +1424,17 @@ void DramcDQSPrecalculation_preset(DRAMC_CTX_T *p)//Test tDQSCK_temp Pre-calcula
if (u1ShuLevel == SRAM_SHU8)
{
TransferReg.u4UI_Fld_P1[0] = RK0_PRE_TDQSCK27_TDQSCK_UIFREQ9_P1_B0R0; //Byte0
TransferReg.u4UI_Fld_P1[1] = RK0_PRE_TDQSCK27_TDQSCK_UIFREQ9_P1_B1R0; //Byte1
TransferReg.u4UI_Fld_P1[0] = RK0_PRE_TDQSCK27_TDQSCK_UIFREQ9_P1_B0R0;
TransferReg.u4UI_Fld_P1[1] = RK0_PRE_TDQSCK27_TDQSCK_UIFREQ9_P1_B1R0;
}
else if (u1ShuLevel == SRAM_SHU9)
{
TransferReg.u4UI_Fld_P1[0] = RK0_PRE_TDQSCK27_TDQSCK_UIFREQ10_P1_B0R0; //Byte0
TransferReg.u4UI_Fld_P1[1] = RK0_PRE_TDQSCK27_TDQSCK_UIFREQ10_P1_B1R0; //Byte1
TransferReg.u4UI_Fld_P1[0] = RK0_PRE_TDQSCK27_TDQSCK_UIFREQ10_P1_B0R0;
TransferReg.u4UI_Fld_P1[1] = RK0_PRE_TDQSCK27_TDQSCK_UIFREQ10_P1_B1R0;
}
else //(u1ShuLevel < SRAM_SHU8)
else
{
switch (u1Delay_Fld[1]) //Phase1 UI
switch (u1Delay_Fld[1])
{
case 0:
TransferReg.u4UI_Fld_P1[0] = RK0_PRE_TDQSCK3_TDQSCK_UIFREQ1_P1_B0R0;
@ -1492,31 +1465,31 @@ void DramcDQSPrecalculation_preset(DRAMC_CTX_T *p)//Test tDQSCK_temp Pre-calcula
u1UI_value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK0_SELPH_DQSG1), SHURK0_SELPH_DQSG1_REG_DLY_DQS0_GATED);
u1PI_value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK0_DQSIEN), SHURK0_DQSIEN_R0DQS0IEN);
}
else //Byte1
else
{
u1MCK_value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK0_SELPH_DQSG0), SHURK0_SELPH_DQSG0_TX_DLY_DQS1_GATED);
u1UI_value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK0_SELPH_DQSG1), SHURK0_SELPH_DQSG1_REG_DLY_DQS1_GATED);
u1PI_value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK0_DQSIEN), SHURK0_DQSIEN_R0DQS1IEN);
}
vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_RK0_PRE_TDQSCK1 + u1Delay_Addr[0] + (u1ByteIdx * u2Byte_offset)), (u1MCK_value << 3) | u1UI_value, TransferReg.u4UI_Fld);//UI
vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_RK0_PRE_TDQSCK1 + u1Delay_Addr[0] + (u1ByteIdx * u2Byte_offset)), u1PI_value, TransferReg.u4PI_Fld); //PI
vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_RK0_PRE_TDQSCK1 + u1Delay_Addr[0] + (u1ByteIdx * u2Byte_offset)), (u1MCK_value << 3) | u1UI_value, TransferReg.u4UI_Fld);
vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_RK0_PRE_TDQSCK1 + u1Delay_Addr[0] + (u1ByteIdx * u2Byte_offset)), u1PI_value, TransferReg.u4PI_Fld);
if (u1ByteIdx == 0)
{
u1MCK_value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK0_SELPH_DQSG0), SHURK0_SELPH_DQSG0_TX_DLY_DQS0_GATED_P1);
u1UI_value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK0_SELPH_DQSG1), SHURK0_SELPH_DQSG1_REG_DLY_DQS0_GATED_P1);
}
else //Byte1
else
{
u1MCK_value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK0_SELPH_DQSG0), SHURK0_SELPH_DQSG0_TX_DLY_DQS1_GATED_P1);
u1UI_value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK0_SELPH_DQSG1), SHURK0_SELPH_DQSG1_REG_DLY_DQS1_GATED_P1);
}
if ((u1ShuLevel == SRAM_SHU8) || (u1ShuLevel == SRAM_SHU9))
vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_RK0_PRE_TDQSCK1 + u1Delay_Addr[1]), (u1MCK_value << 3) | u1UI_value, TransferReg.u4UI_Fld_P1[u1ByteIdx]); //phase1 UI
vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_RK0_PRE_TDQSCK1 + u1Delay_Addr[1]), (u1MCK_value << 3) | u1UI_value, TransferReg.u4UI_Fld_P1[u1ByteIdx]);
else
vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_RK0_PRE_TDQSCK1 + u1Delay_Addr[1] + (u1ByteIdx * u2Byte_offset)), (u1MCK_value << 3) | u1UI_value, TransferReg.u4UI_Fld_P1[0]); //phase1 UI
vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_RK0_PRE_TDQSCK1 + u1Delay_Addr[1] + (u1ByteIdx * u2Byte_offset)), (u1MCK_value << 3) | u1UI_value, TransferReg.u4UI_Fld_P1[0]);
}
}
vSetRank(p, u1RankBackup);
@ -1527,18 +1500,16 @@ void DramcDQSPrecalculation_preset(DRAMC_CTX_T *p)//Test tDQSCK_temp Pre-calcula
void DramcDQSPrecalculation_enable(DRAMC_CTX_T *p)
{
//DQS pre-K new mode
//cc mark removed vIO32WriteFldAlign_All(DRAMC_REG_RK0_PRE_TDQSCK15, 0x1, RK0_PRE_TDQSCK15_SHUFFLE_LEVEL_MODE_SELECT);
//Enable pre-K HW
vIO32WriteFldAlign_All(DDRPHY_REG_MISC_PRE_TDQSCK1, 0x1, MISC_PRE_TDQSCK1_TDQSCK_PRECAL_HW);
//Select HW flow
vIO32WriteFldAlign_All(DDRPHY_REG_MISC_PRE_TDQSCK1, 0x1, MISC_PRE_TDQSCK1_TDQSCK_REG_DVFS);
//Set Auto save to RG
vIO32WriteFldAlign_All(DDRPHY_REG_MISC_PRE_TDQSCK1, 0x1, MISC_PRE_TDQSCK1_TDQSCK_HW_SW_UP_SEL);
}
#endif
#if 0 /* CC mark to use DV initial setting */
#if 0
void DramcHWGatingInit(DRAMC_CTX_T *p)
{
#ifdef HW_GATING
@ -1546,7 +1517,7 @@ void DramcHWGatingInit(DRAMC_CTX_T *p)
0, MISC_SHU_STBCAL_STBCALEN);
vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL),
P_Fld(0, MISC_STBCAL_STBCAL2R) |
//cc mark P_Fld(0,STBCAL_STB_SELPHYCALEN) |
//P_Fld(0,STBCAL_STB_SELPHYCALEN) |
P_Fld(0, MISC_STBCAL_STBSTATE_OPT) |
P_Fld(0, MISC_STBCAL_RKCHGMASKDIS) |
P_Fld(0, MISC_STBCAL_REFUICHG) |
@ -1585,7 +1556,7 @@ void DramcHWGatingOnOff(DRAMC_CTX_T *p, U8 u1OnOff)
void DramcHWGatingDebugOnOff(DRAMC_CTX_T *p, U8 u1OnOff)
{
#ifdef HW_GATING
// STBCAL2_STB_DBG_EN = 0x3, byte0/1 enable
U8 u1EnB0B1 = (u1OnOff == ENABLE)? 0x3: 0x0;
vIO32WriteFldMulti_All(DDRPHY_REG_MISC_STBCAL2,
@ -1605,7 +1576,7 @@ void DramcHWGatingDebugOnOff(DRAMC_CTX_T *p, U8 u1OnOff)
#if (FOR_DV_SIMULATION_USED == 0 && SW_CHANGE_FOR_SIMULATION == 0)
#if (__ETT__ || CPU_RW_TEST_AFTER_K)
#if 0 // Please use memeset to initail value, due to different CHANNEL_NUM
#if 0
U16 u2MaxGatingPos[CHANNEL_NUM][RANK_MAX][DQS_NUMBER] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
U16 u2MinGatingPos[CHANNEL_NUM][RANK_MAX][DQS_NUMBER] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
#endif
@ -1692,7 +1663,7 @@ static void DramcHWGatingTrackingRecord(DRAMC_CTX_T *p, U8 u1Channel)
else
u1RankMax = RANK_1;
//Run Time HW Gating Debug Information
//for(u1RankIdx=0; u1RankIdx<u1RankMax; u1RankIdx++)
for (u1RankIdx = 0; u1RankIdx < u1RankMax; u1RankIdx++)
{
@ -1707,11 +1678,7 @@ static void DramcHWGatingTrackingRecord(DRAMC_CTX_T *p, U8 u1Channel)
for (u1Info_NUM = 0; u1Info_NUM < u1Info_Max_MUM; u1Info_NUM++)
{
//DFS_ST(Shuffle Level): bit[15:14]
//Shift_R(Lead): bit[13]
//Shift_L(Lag) : bit[12]
//UI_DLY : bit[11:06]
//PI_DLY : bit[05:00]
u4DBG_Dqs01_Info = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_RK0_B01_STB_DBG_INFO_00 + 0x4 * u1Info_NUM));
u4DBG_Dqs0_Info = (u4DBG_Dqs01_Info >> 0) & 0xffff;
u4DBG_Dqs1_Info = (u4DBG_Dqs01_Info >> 16) & 0xffff;
@ -1742,11 +1709,7 @@ static void DramcHWGatingTrackingRecord(DRAMC_CTX_T *p, U8 u1Channel)
u1DBG_Dqs1_DFS, u1DBG_Dqs1_Lead, u1DBG_Dqs1_Lag, u1DBG_Dqs1_UI / 8, u1DBG_Dqs1_UI % 8, u1DBG_Dqs1_PI));
}
//Run Time HW Gating Max and Min Value Record
//Run Time HW Gating MAX_DLY UI : bit[27:22]
//Run Time HW Gating MAX_DLY PI : bit[21:16]
//Run Time HW Gating MIN_DLY UI : bit[11:06]
//Run Time HW Gating MIN_DLY PI : bit[05:00]
u4Dqs0_MAX_MIN_DLY = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_RK0_B0_STB_MAX_MIN_DLY));
u2Dqs0_UI_MAX_DLY = (u4Dqs0_MAX_MIN_DLY >> 22) & 0x3f;
u2Dqs0_PI_MAX_DLY = (u4Dqs0_MAX_MIN_DLY >> 16) & 0x3f;
@ -1779,8 +1742,7 @@ static void DramcHWGatingTrackingRecord(DRAMC_CTX_T *p, U8 u1Channel)
void DramcPrintRXFIFODebugStatus(DRAMC_CTX_T *p)
{
#if RX_PICG_NEW_MODE
//RX FIFO debug feature, MP setting should enable debug function for Gating error information
//APHY control new mode
U32 u1ChannelBak, u4value;
U8 u1ChannelIdx;
@ -1790,7 +1752,7 @@ void DramcPrintRXFIFODebugStatus(DRAMC_CTX_T *p)
{
p->channel = u1ChannelIdx;
u4value = u4IO32Read4B(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBERR_RK0_R)) & (0xf << 24); //DDRPHY NAO bit24~27
u4value = u4IO32Read4B(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBERR_RK0_R)) & (0xf << 24);
if (u4value)
{
mcSHOW_DBG_MSG2(("\n[RXFIFODebugStatus] CH_%d MISC_STBERR_RK0_R_RX_ARDQ = 0x\033[1;36m%x\033[m for Gating error information\n", u1ChannelIdx, u4value));

569
src/vendorcode/mediatek/mt8195/dramc/dramc_utility.c
View File

File diff suppressed because it is too large Load Diff

395
src/vendorcode/mediatek/mt8195/dramc/emi.c
View File

@ -39,12 +39,12 @@ static inline unsigned int mt_emi_sync_read(unsigned long long addr)
static void emi_cen_config(void) {
#ifndef ONE_CH
#ifdef RANK_512MB // => 2channel , dual rank , total=2G
#ifdef RANK_512MB
mt_emi_sync_write(EMI_APB_BASE+0x00000000,0xa053a154);
#else
#ifdef RANK_1GB //RANK_1G => 2channel , dual rank , total=4G
#ifdef RANK_1GB
mt_emi_sync_write(EMI_APB_BASE+0x00000000,0xf053f154);
#else // RANK_2G => 2channel , dual rank , total=8G
#else
#ifdef RANK_2GB
mt_emi_sync_write(EMI_APB_BASE+0x00000000,0x00530154);
#endif
@ -58,58 +58,58 @@ static void emi_cen_config(void) {
#endif
#endif
// overhead: 20190821 item1 - synced
mt_emi_sync_write(EMI_APB_BASE+0x00000004,0x182e2d33); //3733 (1:8) r4 - r1 overhead // TBD - change to 4266
mt_emi_sync_write(EMI_APB_BASE+0x00000008,0x0f251025); //3733 (1:8) r8 - r5 overhead // TBD - change to 4266
mt_emi_sync_write(EMI_APB_BASE+0x0000000c,0x122a1027); //3733 (1:8) r12 - r9 overhead // TBD - change to 4266
mt_emi_sync_write(EMI_APB_BASE+0x00000010,0x1a31162d); //3733 (1:8) r16 - r13 overhead // TBD - change to 4266
mt_emi_sync_write(EMI_APB_BASE+0x000008b0,0x182e2d33); //3200 (1:8) r4 - r1 overhead
mt_emi_sync_write(EMI_APB_BASE+0x000008b4,0x0f251025); //3200 (1:8) r8 - r5 overhead
mt_emi_sync_write(EMI_APB_BASE+0x0000001c,0x122a1027); //3200 (1:8) r12 - r9 overhead
mt_emi_sync_write(EMI_APB_BASE+0x00000024,0x1a31162d); //3200 (1:8) r16 - r13 overhead
mt_emi_sync_write(EMI_APB_BASE+0x00000034,0x1024202c); //2400 (1:8) r4 - r1 overhead
mt_emi_sync_write(EMI_APB_BASE+0x0000006c,0x0b210c21); //2400 (1:8) r8 - r5 overhead
mt_emi_sync_write(EMI_APB_BASE+0x0000013c,0x0f250d23); //2400 (1:8) r12 - r9 overhead
mt_emi_sync_write(EMI_APB_BASE+0x00000640,0x152b1228); //2400 (1:8) r16 - r13 overhead
mt_emi_sync_write(EMI_APB_BASE+0x00000044,0x0c201a28); //1866 (1:8) r4 - r1 overhead
mt_emi_sync_write(EMI_APB_BASE+0x00000074,0x0d230a20); //1866 (1:8) r8 - r5 overhead
mt_emi_sync_write(EMI_APB_BASE+0x000001e0,0x0e260d24); //1866 (1:8) r12 - r9 overhead
mt_emi_sync_write(EMI_APB_BASE+0x00000644,0x132d1229); //1866 (1:8) r16 - r13 overhead
mt_emi_sync_write(EMI_APB_BASE+0x0000004c,0x0c201a28); //1600 (1:8) r4 - r1 overhead
mt_emi_sync_write(EMI_APB_BASE+0x00000084,0x0d230a20); //1600 (1:8) r8 - r5 overhead
mt_emi_sync_write(EMI_APB_BASE+0x000001e4,0x0e260d24); //1600 (1:8) r12 - r9 overhead
mt_emi_sync_write(EMI_APB_BASE+0x00000648,0x132d1229); //1600 (1:8) r16 - r13 overhead
mt_emi_sync_write(EMI_APB_BASE+0x00000054,0x0c201a28); //1200 (1:8) r4 - r1 overhead
mt_emi_sync_write(EMI_APB_BASE+0x0000008c,0x0d230a20); //1200 (1:8) r8 - r5 overhead
mt_emi_sync_write(EMI_APB_BASE+0x000001e8,0x0e260d24); //1200 (1:8) r12 - r9 overhead
mt_emi_sync_write(EMI_APB_BASE+0x0000064c,0x132d1229); //1200 (1:8) r16 - r13 overhead
mt_emi_sync_write(EMI_APB_BASE+0x0000005c,0x0e290e28); //800 (1:4) r12 - r9 overhead
mt_emi_sync_write(EMI_APB_BASE+0x00000094,0x091e1322); //800 (1:4) r4 - r1 overhead
mt_emi_sync_write(EMI_APB_BASE+0x000001c8,0x0f29112a); //800 (1:4) r16 - r13 overhead
mt_emi_sync_write(EMI_APB_BASE+0x00000660,0x0c240a1f); //800 (1:4) r8 - r5 overhead
mt_emi_sync_write(EMI_APB_BASE+0x00000064,0x0e290e28); //800 (1:4) r12 - r9 overhead
mt_emi_sync_write(EMI_APB_BASE+0x0000009c,0x091e1322); //800 (1:4) r4 - r1 overhead
mt_emi_sync_write(EMI_APB_BASE+0x000001f4,0x0f29112a); //800 (1:4) r16 - r13 overhead
mt_emi_sync_write(EMI_APB_BASE+0x00000664,0x0c240a1f); //800 (1:4) r8 - r5 overhead
mt_emi_sync_write(EMI_APB_BASE+0x00000030,0x37373a57); //3733 (1:8) r8 - r2 non-align overhead // TBD - change to 4266
mt_emi_sync_write(EMI_APB_BASE+0x00000014,0x3f3f3c39); //3733 (1:8) r16 - r10 non-align overhead // TBD - change to 4266
mt_emi_sync_write(EMI_APB_BASE+0x000008b8,0x3836374e); //3200 (1:8) r8 - r2 non-align overhead
mt_emi_sync_write(EMI_APB_BASE+0x0000002c,0x41413d3a); //3200 (1:8) r16 - r10 non-align overhead
mt_emi_sync_write(EMI_APB_BASE+0x000000c4,0x33313241); //2400 (1:8) r8 - r2 non-align overhead
mt_emi_sync_write(EMI_APB_BASE+0x00000668,0x3a3a3835); //2400 (1:8) r16 - r10 non-align overhead
mt_emi_sync_write(EMI_APB_BASE+0x000000c8,0x34343542); //1866 (1:8) r8 - r2 non-align overhead
mt_emi_sync_write(EMI_APB_BASE+0x0000066c,0x3b3b3835); //1866 (1:8) r16 - r10 non-align overhead
mt_emi_sync_write(EMI_APB_BASE+0x000000cc,0x34343542); //1600 (1:8) r8 - r2 non-align overhead
mt_emi_sync_write(EMI_APB_BASE+0x00000694,0x3b3b3835); //1600 (1:8) r16 - r10 non-align overhead
mt_emi_sync_write(EMI_APB_BASE+0x000000e4,0x34343542); //1200 (1:8) r8 - r2 non-align overhead
mt_emi_sync_write(EMI_APB_BASE+0x00000708,0x3b3b3835); //1200 (1:8) r16 - r10 non-align overhead
mt_emi_sync_write(EMI_APB_BASE+0x000000f4,0x37333034); //800 (1:4) r8 - r2 non-align overhead
mt_emi_sync_write(EMI_APB_BASE+0x0000070c,0x39393a39); //800 (1:4) r16 - r10 non-align overhead
mt_emi_sync_write(EMI_APB_BASE+0x0000012c,0x37333034); //800 (1:4) r8 - r2 non-align overhead
mt_emi_sync_write(EMI_APB_BASE+0x00000748,0x39393a39); //800 (1:4) r16 - r10 non-align overhead
mt_emi_sync_write(EMI_APB_BASE+0x00000004,0x182e2d33);
mt_emi_sync_write(EMI_APB_BASE+0x00000008,0x0f251025);
mt_emi_sync_write(EMI_APB_BASE+0x0000000c,0x122a1027);
mt_emi_sync_write(EMI_APB_BASE+0x00000010,0x1a31162d);
mt_emi_sync_write(EMI_APB_BASE+0x000008b0,0x182e2d33);
mt_emi_sync_write(EMI_APB_BASE+0x000008b4,0x0f251025);
mt_emi_sync_write(EMI_APB_BASE+0x0000001c,0x122a1027);
mt_emi_sync_write(EMI_APB_BASE+0x00000024,0x1a31162d);
mt_emi_sync_write(EMI_APB_BASE+0x00000034,0x1024202c);
mt_emi_sync_write(EMI_APB_BASE+0x0000006c,0x0b210c21);
mt_emi_sync_write(EMI_APB_BASE+0x0000013c,0x0f250d23);
mt_emi_sync_write(EMI_APB_BASE+0x00000640,0x152b1228);
mt_emi_sync_write(EMI_APB_BASE+0x00000044,0x0c201a28);
mt_emi_sync_write(EMI_APB_BASE+0x00000074,0x0d230a20);
mt_emi_sync_write(EMI_APB_BASE+0x000001e0,0x0e260d24);
mt_emi_sync_write(EMI_APB_BASE+0x00000644,0x132d1229);
mt_emi_sync_write(EMI_APB_BASE+0x0000004c,0x0c201a28);
mt_emi_sync_write(EMI_APB_BASE+0x00000084,0x0d230a20);
mt_emi_sync_write(EMI_APB_BASE+0x000001e4,0x0e260d24);
mt_emi_sync_write(EMI_APB_BASE+0x00000648,0x132d1229);
mt_emi_sync_write(EMI_APB_BASE+0x00000054,0x0c201a28);
mt_emi_sync_write(EMI_APB_BASE+0x0000008c,0x0d230a20);
mt_emi_sync_write(EMI_APB_BASE+0x000001e8,0x0e260d24);
mt_emi_sync_write(EMI_APB_BASE+0x0000064c,0x132d1229);
mt_emi_sync_write(EMI_APB_BASE+0x0000005c,0x0e290e28);
mt_emi_sync_write(EMI_APB_BASE+0x00000094,0x091e1322);
mt_emi_sync_write(EMI_APB_BASE+0x000001c8,0x0f29112a);
mt_emi_sync_write(EMI_APB_BASE+0x00000660,0x0c240a1f);
mt_emi_sync_write(EMI_APB_BASE+0x00000064,0x0e290e28);
mt_emi_sync_write(EMI_APB_BASE+0x0000009c,0x091e1322);
mt_emi_sync_write(EMI_APB_BASE+0x000001f4,0x0f29112a);
mt_emi_sync_write(EMI_APB_BASE+0x00000664,0x0c240a1f);
mt_emi_sync_write(EMI_APB_BASE+0x00000030,0x37373a57);
mt_emi_sync_write(EMI_APB_BASE+0x00000014,0x3f3f3c39);
mt_emi_sync_write(EMI_APB_BASE+0x000008b8,0x3836374e);
mt_emi_sync_write(EMI_APB_BASE+0x0000002c,0x41413d3a);
mt_emi_sync_write(EMI_APB_BASE+0x000000c4,0x33313241);
mt_emi_sync_write(EMI_APB_BASE+0x00000668,0x3a3a3835);
mt_emi_sync_write(EMI_APB_BASE+0x000000c8,0x34343542);
mt_emi_sync_write(EMI_APB_BASE+0x0000066c,0x3b3b3835);
mt_emi_sync_write(EMI_APB_BASE+0x000000cc,0x34343542);
mt_emi_sync_write(EMI_APB_BASE+0x00000694,0x3b3b3835);
mt_emi_sync_write(EMI_APB_BASE+0x000000e4,0x34343542);
mt_emi_sync_write(EMI_APB_BASE+0x00000708,0x3b3b3835);
mt_emi_sync_write(EMI_APB_BASE+0x000000f4,0x37333034);
mt_emi_sync_write(EMI_APB_BASE+0x0000070c,0x39393a39);
mt_emi_sync_write(EMI_APB_BASE+0x0000012c,0x37333034);
mt_emi_sync_write(EMI_APB_BASE+0x00000748,0x39393a39);
//
mt_emi_sync_write(EMI_APB_BASE+0x00000018,0x3657587a);
mt_emi_sync_write(EMI_APB_BASE+0x00000020,0x0000c042);
mt_emi_sync_write(EMI_APB_BASE+0x00000028,0x08421000);
@ -121,17 +121,17 @@ static void emi_cen_config(void) {
mt_emi_sync_write(EMI_APB_BASE+0x0000003c,0x00073210);
mt_emi_sync_write(EMI_APB_BASE+0x00000040,0x00008802);
mt_emi_sync_write(EMI_APB_BASE+0x00000048,0x00000000);
mt_emi_sync_write(EMI_APB_BASE+0x00000060,0x007812ff); // reserved buffer to normal read/write :8/7
mt_emi_sync_write(EMI_APB_BASE+0x00000060,0x007812ff);
mt_emi_sync_write(EMI_APB_BASE+0x00000068,0x00000000);
mt_emi_sync_write(EMI_APB_BASE+0x00000078,0x11120c1f); //22:20=ultra_w=1
mt_emi_sync_write(EMI_APB_BASE+0x00000710,0x11120c1f); //22:20=ultra_w=1
mt_emi_sync_write(EMI_APB_BASE+0x00000078,0x11120c1f);
mt_emi_sync_write(EMI_APB_BASE+0x00000710,0x11120c1f);
mt_emi_sync_write(EMI_APB_BASE+0x0000007c,0x00001123);
mt_emi_sync_write(EMI_APB_BASE+0x00000718,0x00001123);
mt_emi_sync_write(EMI_APB_BASE+0x000000d0,0xa8a8a8a8);
mt_emi_sync_write(EMI_APB_BASE+0x000000d4,0x25252525);
mt_emi_sync_write(EMI_APB_BASE+0x000000d8,0xa8a8a8a8);
mt_emi_sync_write(EMI_APB_BASE+0x000000dc,0x25252525);
mt_emi_sync_write(EMI_APB_BASE+0x000000e8,0x00060037); // initial starvation counter div2, [4]=1
mt_emi_sync_write(EMI_APB_BASE+0x000000e8,0x00060037);
mt_emi_sync_write(EMI_APB_BASE+0x000000f0,0x384a0014);
mt_emi_sync_write(EMI_APB_BASE+0x000000f8,0xa0000000);
mt_emi_sync_write(EMI_APB_BASE+0x00000100,0x20107244);
@ -146,38 +146,38 @@ static void emi_cen_config(void) {
mt_emi_sync_write(EMI_APB_BASE+0x00000144,0x00007108);
mt_emi_sync_write(EMI_APB_BASE+0x00000150,0x090a0000);
mt_emi_sync_write(EMI_APB_BASE+0x00000158,0xff0bff00);
mt_emi_sync_write(EMI_APB_BASE+0x00000400,0x00ff0001); //[27:20] enable monitor
mt_emi_sync_write(EMI_APB_BASE+0x00000400,0x00ff0001);
mt_emi_sync_write(EMI_APB_BASE+0x0000071c,0x10000008);
mt_emi_sync_write(EMI_APB_BASE+0x00000800,0xffffffff);
mt_emi_sync_write(EMI_APB_BASE+0x00000820,0x24240101);
mt_emi_sync_write(EMI_APB_BASE+0x00000824,0x01012424);
mt_emi_sync_write(EMI_APB_BASE+0x00000828,0x50500101);
mt_emi_sync_write(EMI_APB_BASE+0x0000082c,0x01015050);
mt_emi_sync_write(EMI_APB_BASE+0x00000830,0x0fc39a30); // [6] MD_HRT_URGENT_MASK, if 1 -> mask MD_HRT_URGENT,
mt_emi_sync_write(EMI_APB_BASE+0x00000830,0x0fc39a30);
mt_emi_sync_write(EMI_APB_BASE+0x00000834,0x05050003);
mt_emi_sync_write(EMI_APB_BASE+0x00000838,0x254dffff);
mt_emi_sync_write(EMI_APB_BASE+0x0000083c,0x465a788c); //update
mt_emi_sync_write(EMI_APB_BASE+0x0000083c,0x465a788c);
mt_emi_sync_write(EMI_APB_BASE+0x00000840,0x000003e8);
mt_emi_sync_write(EMI_APB_BASE+0x00000844,0x0000036b);
mt_emi_sync_write(EMI_APB_BASE+0x00000848,0x00000290);
mt_emi_sync_write(EMI_APB_BASE+0x0000084c,0x00000200);
mt_emi_sync_write(EMI_APB_BASE+0x00000850,0x00000000);
mt_emi_sync_write(EMI_APB_BASE+0x00000854,0x00000000);
mt_emi_sync_write(EMI_APB_BASE+0x00000858,0x02531cff); //ignore rff threshold
mt_emi_sync_write(EMI_APB_BASE+0x0000085c,0x00002785); //disable internal MD latency urgent mask
mt_emi_sync_write(EMI_APB_BASE+0x00000858,0x02531cff);
mt_emi_sync_write(EMI_APB_BASE+0x0000085c,0x00002785);
mt_emi_sync_write(EMI_APB_BASE+0x00000874,0x000001b5);
mt_emi_sync_write(EMI_APB_BASE+0x00000878,0x003c0000); //update
mt_emi_sync_write(EMI_APB_BASE+0x00000878,0x003c0000);
mt_emi_sync_write(EMI_APB_BASE+0x0000087c,0x0255250d);
mt_emi_sync_write(EMI_APB_BASE+0x00000890,0xffff3c59);
mt_emi_sync_write(EMI_APB_BASE+0x00000894,0xffff00ff);
mt_emi_sync_write(EMI_APB_BASE+0x000008a0,0xffffffff);
mt_emi_sync_write(EMI_APB_BASE+0x000008a4,0x0000ffff);
mt_emi_sync_write(EMI_APB_BASE+0x000008c0,0x0000014b);
mt_emi_sync_write(EMI_APB_BASE+0x000008c4,0x002d0000); //update
mt_emi_sync_write(EMI_APB_BASE+0x000008c4,0x002d0000);
mt_emi_sync_write(EMI_APB_BASE+0x000008c8,0x00000185);
mt_emi_sync_write(EMI_APB_BASE+0x000008cc,0x003c0000); //update
mt_emi_sync_write(EMI_APB_BASE+0x000008cc,0x003c0000);
mt_emi_sync_write(EMI_APB_BASE+0x000008d0,0x00000185);
mt_emi_sync_write(EMI_APB_BASE+0x000008d4,0x003c0000); //update
mt_emi_sync_write(EMI_APB_BASE+0x000008d4,0x003c0000);
mt_emi_sync_write(EMI_APB_BASE+0x000008e0,0xffffffff);
mt_emi_sync_write(EMI_APB_BASE+0x000008e4,0xffffffff);
mt_emi_sync_write(EMI_APB_BASE+0x000008e8,0xffffffff);
@ -209,7 +209,7 @@ static void emi_cen_config(void) {
mt_emi_sync_write(EMI_APB_BASE+0x00000c0c,0x64644b64);
mt_emi_sync_write(EMI_APB_BASE+0x00000c40,0x01010101);
mt_emi_sync_write(EMI_APB_BASE+0x00000c44,0x01010101);
mt_emi_sync_write(EMI_APB_BASE+0x00000c4c,0x300ff025); //ignore wff threshold
mt_emi_sync_write(EMI_APB_BASE+0x00000c4c,0x300ff025);
mt_emi_sync_write(EMI_APB_BASE+0x00000c80,0x000003e8);
mt_emi_sync_write(EMI_APB_BASE+0x00000c84,0x0000036b);
mt_emi_sync_write(EMI_APB_BASE+0x00000c88,0x00000290);
@ -223,47 +223,47 @@ static void emi_cen_config(void) {
mt_emi_sync_write(EMI_APB_BASE+0x00000cf8,0x01010101);
mt_emi_sync_write(EMI_APB_BASE+0x00000cfc,0x01010101);
mt_emi_sync_write(EMI_APB_BASE+0x00000d04,0x00000009); //MDR shf0 event selet
mt_emi_sync_write(EMI_APB_BASE+0x00000d0c,0x00000000); //MDR shf1 event selet
mt_emi_sync_write(EMI_APB_BASE+0x00000d14,0x00730000); //MDR shf0
mt_emi_sync_write(EMI_APB_BASE+0x00000d18,0x00000808); //MDR shf1
mt_emi_sync_write(EMI_APB_BASE+0x00000d1c,0x00000028); //MDW shf0 event selet
mt_emi_sync_write(EMI_APB_BASE+0x00000d24,0x00000000); //MDW shf1 event selet
mt_emi_sync_write(EMI_APB_BASE+0x00000d2c,0x00730000); //MDW shf0
mt_emi_sync_write(EMI_APB_BASE+0x00000d30,0x00000808); //MDW shf1
mt_emi_sync_write(EMI_APB_BASE+0x00000d34,0x00000080); //APR shf0 event selet
mt_emi_sync_write(EMI_APB_BASE+0x00000d3c,0x00000000); //APR shf1 event selet
mt_emi_sync_write(EMI_APB_BASE+0x00000d44,0x30201008); //APR shf0/shf1
mt_emi_sync_write(EMI_APB_BASE+0x00000d48,0x00000800); //APW shf0 event selet
mt_emi_sync_write(EMI_APB_BASE+0x00000d50,0x00000000); //APW shf1 event selet
mt_emi_sync_write(EMI_APB_BASE+0x00000d58,0x00008000); //MMR shf0 event selet
mt_emi_sync_write(EMI_APB_BASE+0x00000d60,0x00020000); //MMR shf1 event selet
mt_emi_sync_write(EMI_APB_BASE+0x00000d64,0x00001000); //MMR shf1 event selet
mt_emi_sync_write(EMI_APB_BASE+0x00000d68,0x00010000); //MMR shf2 event selet
mt_emi_sync_write(EMI_APB_BASE+0x00000d6c,0x00000800); //MMR shf2 event selet
mt_emi_sync_write(EMI_APB_BASE+0x00000d70,0x08080000); //MMR shf0
mt_emi_sync_write(EMI_APB_BASE+0x00000d74,0x00073030); //MMR shf1
mt_emi_sync_write(EMI_APB_BASE+0x00000d78,0x00040000); //MMW shf0 event selet
mt_emi_sync_write(EMI_APB_BASE+0x00000d80,0x00100000); //MMW shf1 event selet
mt_emi_sync_write(EMI_APB_BASE+0x00000d84,0x00004000); //MMW shf1 event selet
mt_emi_sync_write(EMI_APB_BASE+0x00000d88,0x00080000); //MMW shf2 event selet
mt_emi_sync_write(EMI_APB_BASE+0x00000d8c,0x00002000); //MMW shf2 event selet
mt_emi_sync_write(EMI_APB_BASE+0x00000d90,0x08080000); //MMW shf0
mt_emi_sync_write(EMI_APB_BASE+0x00000d94,0x00074040); //MMW shf1
mt_emi_sync_write(EMI_APB_BASE+0x00000d98,0x00400000); //MDHWR sh0 event select
mt_emi_sync_write(EMI_APB_BASE+0x00000da0,0x00200000); //MDHWR sh1 event select
mt_emi_sync_write(EMI_APB_BASE+0x00000da8,0x10100404); //MDHWWR sh
mt_emi_sync_write(EMI_APB_BASE+0x00000dac,0x01000000); //MDHWW sh0 event select
mt_emi_sync_write(EMI_APB_BASE+0x00000db4,0x00800000); //MDHWW sh1 event select
mt_emi_sync_write(EMI_APB_BASE+0x00000dbc,0x04000000); //GPUR sh0 event select
mt_emi_sync_write(EMI_APB_BASE+0x00000dc4,0x02000000); //GPUR sh1 event select
mt_emi_sync_write(EMI_APB_BASE+0x00000dcc,0x60602010); //GPUR
mt_emi_sync_write(EMI_APB_BASE+0x00000dd0,0x10000000); //GPUW sh0 event select
mt_emi_sync_write(EMI_APB_BASE+0x00000dd8,0x08000000); //GPUW sh1 event select
mt_emi_sync_write(EMI_APB_BASE+0x00000de0,0x00000009); //ARBR sh0 event select
mt_emi_sync_write(EMI_APB_BASE+0x00000de8,0x04400080); //ARBR sh1 event select
mt_emi_sync_write(EMI_APB_BASE+0x00000df0,0x0f170f11); //ARB
mt_emi_sync_write(EMI_APB_BASE+0x00000df4,0x0303f7f7); //QOS control
mt_emi_sync_write(EMI_APB_BASE+0x00000d04,0x00000009);
mt_emi_sync_write(EMI_APB_BASE+0x00000d0c,0x00000000);
mt_emi_sync_write(EMI_APB_BASE+0x00000d14,0x00730000);
mt_emi_sync_write(EMI_APB_BASE+0x00000d18,0x00000808);
mt_emi_sync_write(EMI_APB_BASE+0x00000d1c,0x00000028);
mt_emi_sync_write(EMI_APB_BASE+0x00000d24,0x00000000);
mt_emi_sync_write(EMI_APB_BASE+0x00000d2c,0x00730000);
mt_emi_sync_write(EMI_APB_BASE+0x00000d30,0x00000808);
mt_emi_sync_write(EMI_APB_BASE+0x00000d34,0x00000080);
mt_emi_sync_write(EMI_APB_BASE+0x00000d3c,0x00000000);
mt_emi_sync_write(EMI_APB_BASE+0x00000d44,0x30201008);
mt_emi_sync_write(EMI_APB_BASE+0x00000d48,0x00000800);
mt_emi_sync_write(EMI_APB_BASE+0x00000d50,0x00000000);
mt_emi_sync_write(EMI_APB_BASE+0x00000d58,0x00008000);
mt_emi_sync_write(EMI_APB_BASE+0x00000d60,0x00020000);
mt_emi_sync_write(EMI_APB_BASE+0x00000d64,0x00001000);
mt_emi_sync_write(EMI_APB_BASE+0x00000d68,0x00010000);
mt_emi_sync_write(EMI_APB_BASE+0x00000d6c,0x00000800);
mt_emi_sync_write(EMI_APB_BASE+0x00000d70,0x08080000);
mt_emi_sync_write(EMI_APB_BASE+0x00000d74,0x00073030);
mt_emi_sync_write(EMI_APB_BASE+0x00000d78,0x00040000);
mt_emi_sync_write(EMI_APB_BASE+0x00000d80,0x00100000);
mt_emi_sync_write(EMI_APB_BASE+0x00000d84,0x00004000);
mt_emi_sync_write(EMI_APB_BASE+0x00000d88,0x00080000);
mt_emi_sync_write(EMI_APB_BASE+0x00000d8c,0x00002000);
mt_emi_sync_write(EMI_APB_BASE+0x00000d90,0x08080000);
mt_emi_sync_write(EMI_APB_BASE+0x00000d94,0x00074040);
mt_emi_sync_write(EMI_APB_BASE+0x00000d98,0x00400000);
mt_emi_sync_write(EMI_APB_BASE+0x00000da0,0x00200000);
mt_emi_sync_write(EMI_APB_BASE+0x00000da8,0x10100404);
mt_emi_sync_write(EMI_APB_BASE+0x00000dac,0x01000000);
mt_emi_sync_write(EMI_APB_BASE+0x00000db4,0x00800000);
mt_emi_sync_write(EMI_APB_BASE+0x00000dbc,0x04000000);
mt_emi_sync_write(EMI_APB_BASE+0x00000dc4,0x02000000);
mt_emi_sync_write(EMI_APB_BASE+0x00000dcc,0x60602010);
mt_emi_sync_write(EMI_APB_BASE+0x00000dd0,0x10000000);
mt_emi_sync_write(EMI_APB_BASE+0x00000dd8,0x08000000);
mt_emi_sync_write(EMI_APB_BASE+0x00000de0,0x00000009);
mt_emi_sync_write(EMI_APB_BASE+0x00000de8,0x04400080);
mt_emi_sync_write(EMI_APB_BASE+0x00000df0,0x0f170f11);
mt_emi_sync_write(EMI_APB_BASE+0x00000df4,0x0303f7f7);
mt_emi_sync_write(EMI_APB_BASE+0x00000e04,0x00000166);
mt_emi_sync_write(EMI_APB_BASE+0x00000e08,0xffffffff);
mt_emi_sync_write(EMI_APB_BASE+0x00000e0c,0xffffffff);
@ -277,51 +277,50 @@ static void emi_cen_config(void) {
mt_emi_sync_write(EMI_APB_BASE+0x00000e38,0xffffffff);
mt_emi_sync_write(EMI_APB_BASE+0x00000e3c,0xffffffff);
// Added by Wei-Lun - START
// prtcl chker - golden setting
mt_emi_sync_write(EMI_APB_BASE+0x00000304,0xffffffff); // cyc
mt_emi_sync_write(EMI_APB_BASE+0x0000030c,0x001ffc85); // ctl
mt_emi_sync_write(EMI_APB_BASE+0x00000314,0xffffffff); // msk
mt_emi_sync_write(EMI_APB_BASE+0x00000304,0xffffffff);
mt_emi_sync_write(EMI_APB_BASE+0x0000030c,0x001ffc85);
mt_emi_sync_write(EMI_APB_BASE+0x00000314,0xffffffff);
mt_emi_sync_write(EMI_APB_BASE+0x0000034c,0xffffffff);
mt_emi_sync_write(EMI_APB_BASE+0x00000354,0x001ffc85);
mt_emi_sync_write(EMI_APB_BASE+0x0000035c,0xffffffff); // msk
mt_emi_sync_write(EMI_APB_BASE+0x0000035c,0xffffffff);
mt_emi_sync_write(EMI_APB_BASE+0x00000394,0xffffffff);
mt_emi_sync_write(EMI_APB_BASE+0x0000039c,0x001ffc85);
mt_emi_sync_write(EMI_APB_BASE+0x000003a4,0xffffffff); // msk
mt_emi_sync_write(EMI_APB_BASE+0x000003a4,0xffffffff);
mt_emi_sync_write(EMI_APB_BASE+0x000003d8,0xffffffff);
mt_emi_sync_write(EMI_APB_BASE+0x000003dc,0x001ffc85);
mt_emi_sync_write(EMI_APB_BASE+0x000003e0,0xffffffff); // msk
mt_emi_sync_write(EMI_APB_BASE+0x000003e0,0xffffffff);
mt_emi_sync_write(EMI_APB_BASE+0x000003fc,0xffffffff);
mt_emi_sync_write(EMI_APB_BASE+0x0000040c,0x001ffc85);
mt_emi_sync_write(EMI_APB_BASE+0x00000414,0xffffffff); // msk
mt_emi_sync_write(EMI_APB_BASE+0x00000414,0xffffffff);
mt_emi_sync_write(EMI_APB_BASE+0x0000044c,0xffffffff);
mt_emi_sync_write(EMI_APB_BASE+0x00000454,0x001ffc85);
mt_emi_sync_write(EMI_APB_BASE+0x0000045c,0xffffffff); // msk
mt_emi_sync_write(EMI_APB_BASE+0x0000045c,0xffffffff);
mt_emi_sync_write(EMI_APB_BASE+0x0000049c,0xffffffff);
mt_emi_sync_write(EMI_APB_BASE+0x000004a4,0x001ffc85);
mt_emi_sync_write(EMI_APB_BASE+0x000004ac,0xffffffff); // msk
mt_emi_sync_write(EMI_APB_BASE+0x000004ac,0xffffffff);
mt_emi_sync_write(EMI_APB_BASE+0x0000050c,0xffffffff);
mt_emi_sync_write(EMI_APB_BASE+0x00000514,0x001ffc85);
mt_emi_sync_write(EMI_APB_BASE+0x0000051c,0xffffffff); // msk
mt_emi_sync_write(EMI_APB_BASE+0x0000051c,0xffffffff);
mt_emi_sync_write(EMI_APB_BASE+0x00000714,0x00000000);
//weilun for new feature
mt_emi_sync_write(EMI_APB_BASE+0x00000714,0x00000000); // dvfs level setting for chn_emi rw switching shf
// cen_emi timeout value
mt_emi_sync_write(EMI_APB_BASE+0x00000628,0x60606060);
mt_emi_sync_write(EMI_APB_BASE+0x0000062c,0x60606060);
// fine-grained qos
mt_emi_sync_write(EMI_APB_BASE+0x00000050,0x00000000);
// ostd->bw
mt_emi_sync_write(EMI_APB_BASE+0x0000061c,0x08ffbbff);
mt_emi_sync_write(EMI_APB_BASE+0x00000624,0xffff5b3c);
mt_emi_sync_write(EMI_APB_BASE+0x00000774,0xffff00ff);
@ -330,16 +329,16 @@ static void emi_cen_config(void) {
mt_emi_sync_write(EMI_APB_BASE+0x0000078c,0x00ffffff);
mt_emi_sync_write(EMI_APB_BASE+0x00000958,0x00000000);
// hash rule
//mt_emi_sync_write(EMI_APB_BASE+0x000007a4,0xC0000000);
}
static void emi_chn_config(void) {
#ifdef RANK_512MB // => 2channel , dual rank , total=2G
#ifdef RANK_512MB
mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x00000000,0x0400a051);
#else
#ifdef RANK_1GB //RANK_1G => 2channel , dual rank , total=4G
#ifdef RANK_1GB
mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x00000000,0x0400f051);
#else
#ifdef RANK_2GB
@ -350,26 +349,26 @@ static void emi_chn_config(void) {
mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x00000008,0x00ff6048);
mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x00000010,0x00000004);
mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x00000018,0x99f08c03);
mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x00000710,0x9a508c17); // [24:20] = 0x2 : bank throttling (default=0x01f00000)
mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x00000048,0x00038137); //RD_INORDER_THR[20:16]=2
mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x00000050,0x38460002); // [1] : MD_RD_AFT_WR_EN
mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x00000710,0x9a508c17);
mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x00000048,0x00038137);
mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x00000050,0x38460002);
mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x00000058,0x00000000);
mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x00000090,0x000002ff);
mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x00000098,0x00003111); //mw2
mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x00000098,0x00003111);
mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x00000140,0x22607188);
mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x00000144,0x22607188);
mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x00000148,0x3719595e); // chuan
mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x0000014c,0x2719595e); // chuan
mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x00000148,0x3719595e);
mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x0000014c,0x2719595e);
mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x00000150,0x64f3ff79);
mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x00000154,0x64f3ff79); // update timeout setting: bit 12~15
mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x00000154,0x64f3ff79);
mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x00000158,0x011b0868);
mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x0000015c,0xa7414222); // Stop urgent read first when write command buffer remain < 7, [31] ultra_read_first, [30:28] wr_rsv_thr_l, [27: 24] wr_rsv_thr_h,
mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x0000015c,0xa7414222);
mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x0000016c,0x0000f801);
mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x00000170,0x40000000);
mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x000001b0,0x000c802f); // Rank-Aware arbitration
mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x000001b4,0xbd3f3f7e); // Rank-Aware arbitration
mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x000001b8,0x7e003d7e); // Rank-Aware arbitration
mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x000003fc,0x00000000); // Write M17_toggle_mask = 0
mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x000001b0,0x000c802f);
mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x000001b4,0xbd3f3f7e);
mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x000001b8,0x7e003d7e);
mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x000003fc,0x00000000);
mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x00000080,0xaa0148ff);
mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x00000088,0xaa6168ff);
mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x00000404,0xaa516cff);
@ -385,10 +384,10 @@ static void emi_sw_setting(void)
enable_infra_emi_broadcast(1);
/* mpu irq settings. separate emi mpu and devmpu irq */
*((volatile unsigned int *) EMI_CONH) = *((volatile unsigned int *) EMI_CONH) | 0xC0;
/* for DVFS BW monitor */
*((volatile unsigned int *) EMI_BWCT0) = 0x05000305;
*((volatile unsigned int *) EMI_BWCT0_6TH) = 0x08FF0705;
*((volatile unsigned int *) EMI_BWCT0_3RD) = 0x0DFF0A05;
@ -423,10 +422,10 @@ static void emi_sw_setting(void)
}
#endif
/* align urgent monitor countrol to bus monitor */
*((volatile unsigned int *)0x10219858) |= 0x1 << 11;
/* EMI doeapp for DCM */
emi_dcm = 0;
emi_log("[EMI DOE] emi_dcm %d\n", emi_dcm);
if (emi_dcm == 1) {
@ -446,9 +445,9 @@ void emi_init(void)
//unsigned int domain = 0;
//char *str;
mt_emi_sync_write(EMI_BASE+0x000007a4, 0xC0000000); // config emi for 2+2CH
mt_emi_sync_write(EMI_BASE+0x000007a4, 0xC0000000);
#ifdef SUB_EMI_BASE
mt_emi_sync_write(SUB_EMI_BASE+0x000007a4, 0xD0000000); // config sub emi for 2+2CH
mt_emi_sync_write(SUB_EMI_BASE+0x000007a4, 0xD0000000);
#endif
enable_infra_emi_broadcast(1);
@ -465,27 +464,26 @@ void emi_init2(void)
enable_infra_emi_broadcast(1);
mt_emi_sync_write_or(CHN0_EMI_BASE+0x00000010, 0x00000001); // [0] EMI enable
mt_emi_sync_write_or(EMI_BASE+0x00000060, 0x00000400); //[10] EMI enable
mt_emi_sync_write_or(CHN0_EMI_BASE+0x00000010, 0x00000001);
mt_emi_sync_write_or(EMI_BASE+0x00000060, 0x00000400);
#ifdef REAL_CHIP_EMI_GOLDEN_SETTING
mt_emi_sync_write_or(EMI_MPU_BASE+0x00000000,0x00000010); // [4] Disable emi_mpu_reg interrupt
mt_emi_sync_write_or(EMI_MPU_BASE+0x00000000,0x00000010);
// Clear rank_arb_en
emi_temp_data = mt_emi_sync_read(EMI_CHANNEL_APB_BASE+0x000001b0); // read ch0
emi_temp_data = mt_emi_sync_read(EMI_CHANNEL_APB_BASE+0x000001b0);
emi_temp_data = emi_temp_data & ~(0x1);
mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x000001b0, emi_temp_data); // broadcast to all channel
// auto-config rank_arb_en according to dual_rank_en setting
// assume all channel with same configuration
emi_temp_data = mt_emi_sync_read(EMI_CHANNEL_APB_BASE+0x00000000); // read ch0
mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x000001b0, emi_temp_data);
emi_temp_data = mt_emi_sync_read(EMI_CHANNEL_APB_BASE+0x00000000);
emi_temp_data = emi_temp_data & 0x1;
mt_emi_sync_write_or(EMI_CHANNEL_APB_BASE+0x000001b0, emi_temp_data); // broadcast to all channel
mt_emi_sync_write_or(EMI_CHANNEL_APB_BASE+0x000001b0, emi_temp_data);
enable_infra_emi_broadcast(0);
// ----- from dcm_setting.c -----
mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x100, 0xFFFFFFFF);
mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x104, 0xFFFFFFFF);
mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x108, 0xFFFFFFFF);
@ -546,13 +544,13 @@ void emi_init2(void)
mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x038, 0xA00001FF);
mt_emi_sync_write_or(INFRACFG_AO_BASE+0x00000078, 0x08000000); // enable infra_local_cg
mt_emi_sync_write_or(INFRACFG_AO_BASE+0x00000078, 0x08000000);
#ifdef EMI_MP_SETTING
// Enable rdata_prty_gen & wdata_prty_chk
mt_emi_sync_write_or(EMI_APB_BASE+0x00000068,0x00400000); // enable cen_emi parity (w)
// emi bus parity workaround
mt_emi_sync_write_or(EMI_APB_BASE+0x00000068,0x00400000);
emi_temp_data = mt_emi_sync_read(0x40000000);
mt_emi_sync_write(0x40000000, emi_temp_data);
emi_temp_data = mt_emi_sync_read(0x40000100);
@ -562,61 +560,20 @@ void emi_init2(void)
emi_temp_data = mt_emi_sync_read(0x40000300);
mt_emi_sync_write(0x40000300, emi_temp_data);
mt_emi_sync_write_or(EMI_CHANNEL_APB_BASE+0x00000050,0x00000004); // enable chn_emi parity
mt_emi_sync_write_or(EMI_CHANNEL_APB_BASE+0x00000050,0x00000004);
//// Enable APMCU Early CKE
//// set reg_chn_en
//emi_temp_data = mt_emi_sync_read(EMI_APB_BASE+0x00000000);
//emi_temp_data = (emi_temp_data >> 6) & (0x1<<2);
//mt_emi_sync_write_or(EMI_APB_BASE+0x000007f4, emi_temp_data);
//// set reg_chn_pos
//emi_temp_data = mt_emi_sync_read(EMI_APB_BASE+0x00000000);
//emi_temp_data = (emi_temp_data << 2) & (0x3<<4);
//mt_emi_sync_write_or(EMI_APB_BASE+0x000007f4, emi_temp_data);
//// set reg_chn_loc
//emi_temp_data = mt_emi_sync_read(EMI_APB_BASE+0x00000000);
//emi_temp_data = (emi_temp_data >> 4) & (0x1<<6);
//mt_emi_sync_write_or(EMI_APB_BASE+0x000007f4, emi_temp_data);
//// set reg_dual_rank_en
//emi_temp_data = mt_emi_sync_read(EMI_APB_BASE+0x00000000);
//emi_temp_data = (emi_temp_data >> 10) & (0x1<<7);
//mt_emi_sync_write_or(EMI_APB_BASE+0x000007f4, emi_temp_data);
//// set reg_cas_size[1:0]
//emi_temp_data = mt_emi_sync_read(EMI_APB_BASE+0x00000000);
//emi_temp_data = (emi_temp_data >> 9) & (0x3<<9);
//mt_emi_sync_write_or(EMI_APB_BASE+0x000007f4, emi_temp_data);
//// set reg_cas_size[2]
//emi_temp_data = mt_emi_sync_read(EMI_APB_BASE+0x00000000);
//emi_temp_data = (emi_temp_data << 11) & (0x1<<11);
//mt_emi_sync_write_or(EMI_APB_BASE+0x000007f4, emi_temp_data);
//// set reg_cas_size[3]
//emi_temp_data = mt_emi_sync_read(EMI_APB_BASE+0x00000000);
//emi_temp_data = (emi_temp_data >> 14) & (0x1<<12);
//mt_emi_sync_write_or(EMI_APB_BASE+0x000007f4, emi_temp_data);
//// set reg_remap_shift
//mt_emi_sync_write_or(EMI_APB_BASE+0x000007f4, 0x00006000);
//// set reg_rank_dec0
//emi_temp_data = mt_emi_sync_read(EMI_APB_BASE+0x00000038);
//emi_temp_data = (emi_temp_data << 2) & (0x1f<<18);
//mt_emi_sync_write_or(EMI_APB_BASE+0x000007f4, emi_temp_data);
//// set reg_rank_cke_ext and reg_enable
//mt_emi_sync_write_or(EMI_APB_BASE+0x000007f4, 0x11000001);
//// set to mcusys
//emi_temp_data = mt_emi_sync_read(EMI_APB_BASE+0x000007f4);
//mt_emi_sync_write(MCUSYS_PAR_WRAP_BASE+0x0000a490, emi_temp_data);
/*TINFO="program hash rule"*/
mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x00000050, 0x00000021);
mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x00000050, 0x80000021); // set disph_chg_en = 0x1
mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x00000050, 0x80000021);
/*TINFO="read emi_reg_pd then write apmcu config reg"*/
emi_temp_data = mt_emi_sync_read(INFRACFG_AO_MEM_BASE+0x050);
emi_temp_data = emi_temp_data & 0xf;
mt_emi_sync_write_or(EMI_BASE+0x07A4, emi_temp_data);
/*TINFO="Enable EMI wdata bus encode function"*/
mt_emi_sync_write_or(EMI_APB_BASE+0x00000068,0x00200000); // enable cen_emi wdata bus encode // *EMI_CONN |= (0x1 << 21);
mt_emi_sync_write_or(EMI_CHANNEL_APB_BASE+0x00000050,0x00000010); // enable chn_emi wdata bus encode // *CHN0_EMI_CHN_EMI_DFTC |= (0x1 <<4);
mt_emi_sync_write_or(EMI_APB_BASE+0x00000068,0x00200000);
mt_emi_sync_write_or(EMI_CHANNEL_APB_BASE+0x00000050,0x00000010);
#else
// MP_dsim_v02 test (from v01) - all fr
//mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x028, 0x003F0000);
@ -626,27 +583,27 @@ void emi_init2(void)
#endif
/*TINFO="program hash rule"*/
if (channel_num_auxadc == CHANNEL_FOURTH)
{
mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x00000050, 0x00000021);
mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x00000050, 0x80000021); // set disph_chg_en = 0x1
mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x00000050, 0x80000021);
}
else /* CHANNEL_DUAL */
else
{
mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x00000050, 0x00000007);
mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x00000050, 0x80000007); // set disph_chg_en = 0x1
mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x00000050, 0x80000007);
}
/*TINFO="read emi_reg_pd then write apmcu config reg"*/
emi_temp_data = mt_emi_sync_read(INFRACFG_AO_MEM_BASE+0x050);
emi_temp_data = emi_temp_data & 0xf;
enable_infra_emi_broadcast(1);
mt_emi_sync_write_or(EMI_BASE+0x07A4, emi_temp_data);
mt_emi_sync_write(CHN0_EMI_BASE+0x0020, 0x00000040); // disable EBG
mt_emi_sync_write(CHN0_EMI_BASE+0x0020, 0x00000040);
enable_infra_emi_broadcast(0);
emi_sw_setting();
@ -809,7 +766,7 @@ unsigned int get_cen_emi_cona(void)
return mt_emi_sync_read(EMI_CONA);
}
/* assume all chn emi setting are the same */
unsigned int get_chn_emi_cona(void)
{
unsigned int ch0_emi_cona;
@ -897,7 +854,7 @@ void phy_addr_to_dram_addr(dram_addr_t *dram_addr, unsigned long long phy_addr)
static unsigned int cen_emi_conh_backup = 0;
static unsigned int chn_emi_cona_backup = 0;
/* return the start address of rank1 */
unsigned int set_emi_before_rank1_mem_test(void)
{
cen_emi_conh_backup = mt_emi_sync_read(EMI_CONH);
@ -905,13 +862,13 @@ unsigned int set_emi_before_rank1_mem_test(void)
enable_infra_emi_broadcast(1);
if (get_rank_nr_by_emi() == 2) {
/* set the rank size to 1GB for 2 channels */
mt_emi_sync_write(EMI_CONH,
(cen_emi_conh_backup & 0x0000ffff) | 0x22220000);
set_chn_emi_cona(
(chn_emi_cona_backup & 0xff00ffff) | 0x00220000);
} else {
/* set the rank size to 1GB for 1 channel */
mt_emi_sync_write(EMI_CONH,
(cen_emi_conh_backup & 0x0000ffff) | 0x44440000);
set_chn_emi_cona(
@ -1053,7 +1010,7 @@ void record_emi_snst(void)
last_emi_info_ptr->snst_last = mt_emi_sync_read(EMI_SNST);
emi_log("[EMI] SNST: 0x%x\n", last_emi_info_ptr->snst_last);
/* clear EMI_SNST and set target master to M5 */
mt_emi_sync_write(EMI_SNST, 0x85000000);
#endif
}

40
src/vendorcode/mediatek/mt8195/include/dramc_int_slt.h
View File

@ -12,24 +12,20 @@
#define ENABLE_EMI_LPBK_TEST 0
#endif
#define EMI_LPBK_DRAM_USED !ENABLE_EMI_LPBK_TEST // 0: EMI LPBK test, 1: normal K, dram used
#define EMI_LPBK_DRAM_USED !ENABLE_EMI_LPBK_TEST
#define EMI_LPBK_USE_THROUGH_IO 0 //test through IO
#define EMI_INT_LPBK_WL_DQS_RINGCNT 0 //DQS Ring cnt: through io @ 800,1600,2400,3200, emi intlpbk wo rx/tx K window
#define EMI_LPBK_ADDRESS_DEFECT 0 //test address defect, MUST use CPU WRITE mode
#define EMI_LPBK_USE_THROUGH_IO 0
#define EMI_INT_LPBK_WL_DQS_RINGCNT 0
#define EMI_LPBK_ADDRESS_DEFECT 0
#if ENABLE_EMI_LPBK_TEST
#define EMI_USE_TA2 0 // 0:CPU write, 1:TA2, DVsim/Dsim use TA2, but 1:4 mode must use cpu write(because TA2 not support 1:4 mode)
#define EMI_USE_TA2 0
#else
#define EMI_USE_TA2 0
#endif
/****************************
Summary:
1W1R: address offset : 0, 4, 8, c (1:8 mode only), no support 1:4 mode
8W1R: address offset 0x0 ~ 0xC (8W1R), 0x10 ~ 0x1C, (10W1R) (1:8 & 1:4 mode)
****************************/
#define EMI_LPBK_1W1R 0 //CPU mode 0:8W1R, 1:1W1R
#define EMI_LPBK_1W1R 0
#define EMI_LPBK_S1 0
@ -40,12 +36,12 @@ Summary:
#define ADJUST_TXDLY_SCAN_RX_WIN 0
#define EMI_LPBK_K_TX 0
#define ENABLE_PRE_POSTAMBLE !EMI_USE_TA2 //0: no pre/post-amble for TA2, 1: need pre/post-amble for cpu write
#define ENABLE_PRE_POSTAMBLE !EMI_USE_TA2
#define EMI_LPBK_DFS_32 0 //DFS 32<->32<->32
#define EMI_LPBK_DFS_24 0 //DFS 24<->24<->24
#define EMI_LPBK_DFS_16 0 //DFS 16<->16<->16
#define EMI_LPBK_DFS_32 0
#define EMI_LPBK_DFS_24 0
#define EMI_LPBK_DFS_16 0
#define EMI_LPBK_USE_LP3_PINMUX 0
#define EMI_LPBK_8W1R 1
#if EMI_LPBK_1W1R
@ -60,13 +56,13 @@ Summary:
#endif
//#define K_TX_DQS_DLY 0
#define LP4_4266_freq_meter 533 // //shu0 533
#define LP4_3733_freq_meter 464 // //shu0 464
#define LP4_3200_freq_meter 386 // //shu8 386 //shu9 386
#define LP4_2400_freq_meter 299 //shu6 299 shu5 299
#define LP4_1600_freq_meter 191 //199 //shu4 383 shu3 191
#define LP4_1200_freq_meter 299 //shu2 299 shu1 299
#define LP4_800_freq_meter 199 //shu7 199
#define LP4_4266_freq_meter 533
#define LP4_3733_freq_meter 464
#define LP4_3200_freq_meter 386
#define LP4_2400_freq_meter 299
#define LP4_1600_freq_meter 191
#define LP4_1200_freq_meter 299
#define LP4_800_freq_meter 199
#if ENABLE_EMI_LPBK_TEST //EMI_LPBK_DRAM_USED==0

330
src/vendorcode/mediatek/mt8195/include/dramc_pi_api.h
View File

@ -16,9 +16,9 @@
#include <soc/dramc_soc.h>
#include <soc/dramc_param.h>
#define SW_CHANGE_FOR_SIMULATION 0 //calibration funciton for whole chip simulation. Code changed due to different compiler
#define SW_CHANGE_FOR_SIMULATION 0
#ifndef FOR_DV_SIMULATION_USED
#define FOR_DV_SIMULATION_USED (FALSE) ////calibration funciton for DV simulation. Code changed due to different compiler#define FT_DSIM_USED 0
#define FOR_DV_SIMULATION_USED (FALSE)
#endif
#define DV_SIMULATION_LP4 1
#define BYPASS_CALIBRATION 0
@ -52,13 +52,13 @@
#define EYESCAN_K (0)
//Read Chip QT Tool
#ifndef QT_GUI_Tool
#define QT_GUI_Tool 0 //Setting 1 when using QT GUI Tool Compiler.
#define HAPS_FPFG_A60868 0 //Setting 1 when testing HAPS FPGA
#define QT_GUI_Tool 0
#define HAPS_FPFG_A60868 0
#endif
//DRAMC Chip
#define fcA60868 1
#define fcPetrus 2
#define fcIPM 3
@ -78,7 +78,7 @@
#define __LP5_COMBO__ (FALSE)
#define FEATURE_RDDQC_K_DMI (FALSE) // This feature is not supported at A60868 test chip
#define FEATURE_RDDQC_K_DMI (FALSE)
#if FOR_DV_SIMULATION_USED
#undef __ETT__
@ -97,41 +97,41 @@
#endif
#if FOR_DV_SIMULATION_USED
#define CHANNEL_NUM 2 // 1 single channel, 2 dual channel, 4 channel
#define CHANNEL_NUM 2
#else
#define CHANNEL_NUM 4 // 1 single channel, 2 dual channel, 4 channel
#define CHANNEL_NUM 4
#endif
#define DPM_CH_NUM 2 // CH0/1 is Master, CH2/3 is Slave
#define DPM_CH_NUM 2
//ZQ calibration
#define ENABLE_LP4_ZQ_CAL 1
#if ENABLE_LP4_ZQ_CAL //choose one mode to do ZQ calibration
#define ZQ_SWCMD_MODE 1 //suggested SW CMD mode
#define ZQ_RTSWCMD_MODE 0 //run time SW mode
#define ZQ_SCSM_MODE 0 //old mode
#if ENABLE_LP4_ZQ_CAL
#define ZQ_SWCMD_MODE 1
#define ZQ_RTSWCMD_MODE 0
#define ZQ_SCSM_MODE 0
#endif
#define CODE_SIZE_REDUCE 0
#define CALIBRATION_SPEED_UP_DEBUG 0
#define VENDER_JV_LOG 0
//SW option
#define DUAL_FREQ_K 1 //0 : only K 1 freq(1600), 1: K multi freq
#define DUAL_FREQ_K 1
#define SCRAMBLE_EN 1
#if 1 //[FOR_CHROMEOS]
#define ENABLE_EYESCAN_GRAPH 0 //__ETT__ //draw eye diagram after calibration, if enable, need to fix code size problem.
#else
#define ENABLE_EYESCAN_GRAPH 1
#endif
#define EYESCAN_GRAPH_CATX_VREF_STEP 0x1U // 1 (origin), 2 (div 2)(save 9K size), 5 for A60868
#define EYESCAN_GRAPH_CATX_VREF_STEP 0x1U
#define EYESCAN_GRAPH_RX_VREF_STEP 2
#define EYESCAN_RX_VREF_RANGE_END 128 //field is 6 bit, but can only use 0~63,7bit ->127
#define EYESCAN_RX_VREF_RANGE_END 128
#define EYESCAN_SKIP_UNTERM_CBT_EYESCAN_VREF 10
#if (fcFOR_CHIP_ID == fcA60868)
#define ENABLE_EYESCAN_CBT 0 //TO DO:Forece to draw CBT eye diagram after calibration
#define ENABLE_EYESCAN_RX 0 //TO DO:Forece to draw RX eye diagram after calibration
#define ENABLE_EYESCAN_TX 0 //TO DO:Forece to draw TX eye diagram after calibration
#define ENABLE_VREFSCAN 0 //TO DO:Forece to Vref Scan for calibration
#define ENABLE_EYESCAN_CBT 0
#define ENABLE_EYESCAN_RX 0
#define ENABLE_EYESCAN_TX 0
#define ENABLE_VREFSCAN 0
#endif
#define CHECK_HQA_CRITERIA 0
@ -148,7 +148,7 @@
#define ETT_MINI_STRESS_USE_TA2_LOOP_MODE 1
#define DUMP_TA2_WINDOW_SIZE_RX_TX 0
#if ENABLE_TX_TRACKING
#define ENABLE_SW_TX_TRACKING 0 //if SW_TX_TRACKING is 0, using HW_TX_TRACKING
#define ENABLE_SW_TX_TRACKING 0
//can only choose 1 to set as 1 in the following 3 define
#define DQSOSC_SWCMD 1
#define DQSOSC_RTSWCMD 0
@ -164,15 +164,15 @@
#define ENABLE_TMRRI_NEW_MODE 1
#define ENABLE_8PHASE_CALIBRATION 1
#define ENABLE_DUTY_SCAN_V2 1
#define DUTY_SCAN_V2_ONLY_K_HIGHEST_FREQ 0 //0: K all Freq 1: K highest Freq
#define DUTY_SCAN_V2_ONLY_K_HIGHEST_FREQ 0
#define APPLY_DQDQM_DUTY_CALIBRATION 1
#define IMPEDANCE_TRACKING_ENABLE //Impendence tracking
#define IMPEDANCE_TRACKING_ENABLE
#ifdef IMPEDANCE_TRACKING_ENABLE
#define IMPEDANCE_HW_CALIBRATION 0
#else
#define IMPEDANCE_HW_CALIBRATION 0
#endif
#define IMPEDANCE_HW_SAVING //mask because function fail, it lets clk swing change larger before DVFS occurs
#define IMPEDANCE_HW_SAVING
#define IMP_DEBUG_ENABLE
#define ENABLE_MIOCK_JMETER
#define MIOCK_JMETER_CNT_WA 1
@ -182,8 +182,8 @@
#define TDQSCK_PRECALCULATION_FOR_DVFS 1
#define HW_GATING
#define ENABLE_RX_FIFO_MISMATCH_DEBUG 1
#define VERIFY_CKE_PWR_DOWN_FLOW 0 //Lewis add for DVT
#define CBT_MOVE_CA_INSTEAD_OF_CLK 1 // need to check on LP5
#define VERIFY_CKE_PWR_DOWN_FLOW 0
#define CBT_MOVE_CA_INSTEAD_OF_CLK 1
#define MRW_CHECK_ONLY 0
#define MRW_BACKUP 0
#define ENABLE_SAMSUNG_NT_ODT 0
@ -196,31 +196,31 @@
#define DUMP_ALLSUH_RG 0
#define PIN_CHECK_TOOL 0
#define ENABLE_DATLAT_BY_FORMULA 1
#define ENABLE_RX_AUTOK_MISS_FIRSTPASS_WA 1 //TOBE remove at IPMv2.2
#define ENABLE_RX_AUTOK_MISS_FIRSTPASS_WA 1
//Debug option
#define GATING_ONLY_FOR_DEBUG 0
#define ENABLE_RX_AUTOK_DEBUG_MODE 0
#define RX_DLY_TRACK_ONLY_FOR_DEBUG 0 // LP4 only, LP3 not support
#define RX_DLY_TRACK_ONLY_FOR_DEBUG 0
#if CODE_SIZE_REDUCE || FOR_DV_SIMULATION_USED
#define CPU_RW_TEST_AFTER_K 0 // need to enable GATING_ONLY_FOR_DEBUG at the same time for gating debug log
#define CPU_RW_TEST_AFTER_K 0
#define TA2_RW_TEST_AFTER_K 0
#else
#define CPU_RW_TEST_AFTER_K 1 // need to enable GATING_ONLY_FOR_DEBUG at the same time for gating debug log
#define CPU_RW_TEST_AFTER_K 1
#define TA2_RW_TEST_AFTER_K 1
#endif
//PINMUX auto test per bit related
#define PINMUX_AUTO_TEST_PER_BIT_CA 0
#define PINMUX_AUTO_TEST_PER_BIT_RX 0
#define PINMUX_AUTO_TEST_PER_BIT_TX 0
#define CA_PER_BIT_DELAY_CELL 1//LP4
#define CA_PER_BIT_DELAY_CELL 1
#if PINMUX_AUTO_TEST_PER_BIT_CA
#undef CA_PER_BIT_DELAY_CELL
#define CA_PER_BIT_DELAY_CELL 0
#endif
//Gating calibration
#define GATING_LEADLAG_LOW_LEVEL_CHECK 0
#if CODE_SIZE_REDUCE
@ -258,7 +258,7 @@
#define EYESCAN_LOG 0
#define FSP1_CLKCA_TERM 1
#define CBT_FSP1_MATCH_FSP0_UNTERM_WA 1
#define MR_CBT_SWITCH_FREQ !FOR_DV_SIMULATION_USED //@Darren, Wait DFS ready
#define MR_CBT_SWITCH_FREQ !FOR_DV_SIMULATION_USED
#define FT_DSIM_USED 0
#define GATING_ONLY_FOR_DEBUG 0
#define MEASURE_DRAM_POWER_INDEX 0
@ -274,11 +274,11 @@
#define APPLY_SIGNAL_WAVEFORM_SETTINGS_ADJUST 0
#define SUPPORT_HYNIX_RX_DQS_WEAK_PULL 0
#define RX_DLY_TRACK_ONLY_FOR_DEBUG 0
//Run time config
#define TEMP_SENSOR_ENABLE // Enable rumtime HMR4
#define TEMP_SENSOR_ENABLE
#define ENABLE_REFRESH_RATE_DEBOUNCE 1
#define ENABLE_PER_BANK_REFRESH 1
#define PER_BANK_REFRESH_USE_MODE 1 // 0: original mode, 1: hybrid mode, 2: always pb mode
#define PER_BANK_REFRESH_USE_MODE 1
#define IMP_TRACKING_PB_TO_AB_REFRESH_WA 1
#define DRAMC_MODIFIED_REFRESH_MODE 1
#define DRAMC_CKE_DEBOUNCE 1
@ -286,14 +286,14 @@
#define SAMSUNG_LP4_NWR_WORKAROUND 1
#define AC_TIMING_DERATE_ENABLE 1
#define ENABLE_EARLY_BG_CMD 0 // 0: Disable 1: Enable, Reduce the CMD latency by CTO_EBG request
#define ENABLE_EARLY_BG_CMD 0
//////////////////////////////////// DVFS //////////////////////////////
#define ENABLE_DVS 1 //DVS need tracking enable
#define DRAMC_DFS_MODE 1 // 0:Legacy, 1:DPM RG, 2: PHY RG
#define ENABLE_DVS 1
#define DRAMC_DFS_MODE 1
#define ENABLE_RTMRW_DEBUG_LOG 0
#define ENABLE_TX_REBASE_ODT_WA 0 // for Pexxxs/xxx868
#define ENABLE_DDR800_SOPEN_DSC_WA 1 //Paxxer
#define ENABLE_TX_REBASE_ODT_WA 0
#define ENABLE_DDR800_SOPEN_DSC_WA 1
#if ENABLE_TX_WDQS
#define ENABLE_TX_REBASE_WDQS_DQS_PI_WA 0
#endif
@ -306,18 +306,18 @@
#define ENABLE_DFS_TIMING_ENLARGE 0
#define ENABLE_DFS_208M_CLOCK 0
#define ENABLE_DFS_HW_SAVE_MASK 0
#define REPLACE_DFS_RG_MODE 1 //Trial run Remove DFS PHY RG mode
#define REPLACE_DFS_RG_MODE 1
#define ENABLE_LP4Y_DFS 0
#if ENABLE_LP4Y_DFS
#define LP4Y_BACKUP_SOLUTION 0 // 0: Set SE after calibration, 1: Set SE before calibration
#define ENABLE_LP4Y_WA 1 //no que flush actiming extend and CBT can't train in SE
#define LP4Y_BACKUP_SOLUTION 0
#define ENABLE_LP4Y_WA 1
#define ENABLE_DFS_RUNTIME_MRW 1
#else
#define LP4Y_BACKUP_SOLUTION 0
#define ENABLE_LP4Y_WA 0
#define ENABLE_DFS_RUNTIME_MRW 0 // for LP4x
#define ENABLE_DFS_RUNTIME_MRW 0
#endif
#define ENABLE_TIMING_TXSR_DFS_WA REFRESH_OVERHEAD_REDUCTION // Wait overhead refresh enable, @Darren, Entry SREF -> EXIT SREF -> PDE Command violates tXSR time
#define ENABLE_TIMING_TXSR_DFS_WA REFRESH_OVERHEAD_REDUCTION
#define ENABLE_RANK_NUMBER_AUTO_DETECTION 1
#define DDR_HW_AUTOK_POLLING_CNT 100000
@ -325,9 +325,9 @@
//////////////////////////////////// FIXME end/////////////////////////
#if (fcFOR_CHIP_ID == fcA60868)
#define WORKAROUND_LP5_HEFF 1 //High efficiency mode
#define WORKAROUND_LP5_HEFF 1
#undef ENABLE_RUNTIME_MRW_FOR_LP5
#define ENABLE_RUNTIME_MRW_FOR_LP5 0 // DV fail in 868, use RTSWCMD_MRW
#define ENABLE_RUNTIME_MRW_FOR_LP5 0
#endif
#if ENABLE_RODT_TRACKING
@ -337,10 +337,10 @@
#endif
#define CHECK_GOLDEN_SETTING (FALSE)
#define APPLY_LOWPOWER_GOLDEN_SETTINGS 1 //0: DCM Off, 1: DCM On
#define LP5_GOLDEN_SETTING_CHECKER (FALSE) //FALSE: enable LP4 checker
#define APPLY_LOWPOWER_GOLDEN_SETTINGS 1
#define LP5_GOLDEN_SETTING_CHECKER (FALSE)
//#define CMD_PICG_NEW_MODE 1
//#define ENABLE_RX_DCM_DPHY 1 //Set 0 will lead DCM on/off error (Remove the flag, the setting will be 1)
//#define ENABLE_RX_DCM_DPHY 1
//#define CLK_FREE_FUN_FOR_DRAMC_PSEL
//#define HW_SAVE_FOR_SR
@ -352,10 +352,8 @@
#define RX_PICG_NEW_MODE 0
#endif
#define DDR_RESERVE_NEW_MODE 1 //0: old mode 1: new mode
//=============================================================================
// for D Sim sumulation used
//=============================================================================
#define DDR_RESERVE_NEW_MODE 1
#if QT_GUI_Tool || !FOR_DV_SIMULATION_USED
#define DV_SIMULATION_INIT_C 1
#define SIMULATION_LP4_ZQ 1
@ -370,7 +368,7 @@
#define SIMULATION_DATLAT 1
#define SIMULATION_RX_RDDQC 1
#define SIMULATION_RX_PERBIT 1
#define SIMULATION_TX_PERBIT 1 // Please enable with write leveling
#define SIMULATION_TX_PERBIT 1
#define SIMULATION_RX_DVS 0
#define SIMULATION_RUNTIME_CONFIG 0
#else
@ -387,11 +385,11 @@
#define SIMULATION_DATLAT 1
#define SIMULATION_RX_RDDQC 1
#define SIMULATION_RX_PERBIT 1
#define SIMULATION_TX_PERBIT 1 // Please enable with write leveling
#define SIMULATION_TX_PERBIT 1
#define SIMULATION_RX_DVS 0
#define SIMULATION_RUNTIME_CONFIG 1 // @Darren for DV sim
#define SIMULATION_RUNTIME_CONFIG 1
#endif
//Used to keep original VREF when doing Rx calibration for RX DVS
#define DVS_CAL_KEEP_VREF 0xf
//#define DDR_INIT_TIME_PROFILING
@ -405,9 +403,9 @@
// common
#define DQS_BYTE_NUMBER 2
#define DQS_BIT_NUMBER 8
#define DQ_DATA_WIDTH 16 // define max support bus width in the system (to allocate array size)
#define DQ_DATA_WIDTH 16
#define DQM_BYTE_NUM 2
#define TIME_OUT_CNT 100 //100us
#define TIME_OUT_CNT 100
#define HW_REG_SHUFFLE_MAX 4
typedef enum
@ -417,16 +415,16 @@ typedef enum
ALL_BYTES
} BYTES_T;
//Should be removed after A60868
#define LP5_DDR4266_RDBI_WORKAROUND 0
#define CBT_O1_PINMUX_WORKAROUND 0
#define WLEV_O1_PINMUX_WORKAROUND 0
#define WCK_LEVELING_FM_WORKAROUND 0
//RX input buffer offset calibration
#define ENABLE_RX_INPUT_BUFF_OFF_K 1
/* Gating window */
#define DQS_GW_COARSE_STEP 1
#define DQS_GW_FINE_START 0
#define DQS_GW_FINE_END 32
@ -435,23 +433,23 @@ typedef enum
#define DQS_GW_UI_PER_MCK 16
#define DQS_GW_PI_PER_UI 32
// DATLAT
#define DATLAT_TAP_NUMBER 32
// RX DQ/DQS
#define MAX_RX_DQSDLY_TAPS 511 // 0x018, May set back to 64 if no need.
#define MAX_RX_DQSDLY_TAPS 511
#define MAX_RX_DQDLY_TAPS 252
#define RX_VREF_NOT_SPECIFY 0xff
#define RX_VREF_DUAL_RANK_K_FREQ 1866 // if freq >=RX_VREF_DUAL_RANK_K_FREQ, Rank1 rx vref K will be enable.
#define RX_VREF_DUAL_RANK_K_FREQ 1866
#define RX_VREF_RANGE_BEGIN 0
#define RX_VREF_RANGE_BEGIN_ODT_OFF 32
#define RX_VREF_RANGE_BEGIN_ODT_ON 24
#define RX_VREF_RANGE_END 128 //field is 6 bit, but can only use 0~63
#define RX_VREF_RANGE_END 128
#define RX_VREF_RANGE_STEP 1
#define RX_PASS_WIN_CRITERIA 30
#define RDDQC_PINMUX_WORKAROUND 1
// TX DQ/DQS
#if CODE_SIZE_REDUCE
#define TX_AUTO_K_SUPPORT 0
#else
@ -462,8 +460,8 @@ typedef enum
#define TX_AUTO_K_WORKAROUND 1
#define ENABLE_PA_IMPRO_FOR_TX_AUTOK 1
#endif
#define MAX_TX_DQDLY_TAPS 31 // max DQ TAP number
#define MAX_TX_DQSDLY_TAPS 31 // max DQS TAP number
#define MAX_TX_DQDLY_TAPS 31
#define MAX_TX_DQSDLY_TAPS 31
#define TX_OE_EXTEND 0
#define TX_DQ_OE_SHIFT_LP5 5
#if TX_OE_EXTEND
@ -483,13 +481,12 @@ typedef enum
#define TX_RETRY_CONTROL_BY_SPM 0
#endif
// Sw work around options.
#define CA_TRAIN_RESULT_DO_NOT_MOVE_CLK 1 // work around for clock multi phase problem(cannot move clk or the clk will be bad)
#define CA_TRAIN_RESULT_DO_NOT_MOVE_CLK 1
#define DramcHWDQSGatingTracking_JADE_TRACKING_MODE 1
#define DramcHWDQSGatingTracking_FIFO_MODE 1
#define DONT_MOVE_CLK_DELAY // don't move clk delay
/* If defined for gFreqTbl and fastK
*/
#define DONT_MOVE_CLK_DELAY
#define LP4_SHU0_FREQ (1866)
#define LP4_SHU8_FREQ (1600)
#define LP4_SHU9_FREQ (1600)
@ -514,14 +511,14 @@ typedef enum
#define LP4_SHU7_FREQSEL (LP4_DDR800)
#if FOR_DV_SIMULATION_USED
#define DEFAULT_TEST2_1_CAL 0x55000000 // pattern0 and base address for test engine when we do calibration
#define DEFAULT_TEST2_2_CAL 0xaa000020 // pattern1 and offset address for test engine when we do calibraion
#define DEFAULT_TEST2_1_CAL 0x55000000
#define DEFAULT_TEST2_2_CAL 0xaa000020
#else
#define DEFAULT_TEST2_1_CAL 0x55000000 // pattern0 and base address for test engine when we do calibration
#define DEFAULT_TEST2_2_CAL 0xaa000100 // pattern1 and offset address for test engine when we do calibraion
#define DEFAULT_TEST2_1_CAL 0x55000000
#define DEFAULT_TEST2_2_CAL 0xaa000100
#endif
//CBT/CA training
#if CODE_SIZE_REDUCE
#define CBT_AUTO_K_SUPPORT 0
#define CBT_OLDMODE_SUPPORT 0
@ -535,13 +532,13 @@ typedef enum
#define LP4_MRFSP_TERM_FREQ 1333
#define LP5_MRFSP_TERM_FREQ 1866
//Calibration Summary
#define PRINT_CALIBRATION_SUMMARY (!SW_CHANGE_FOR_SIMULATION)
#define PRINT_CALIBRATION_SUMMARY_DETAIL 1
#define PRINT_CALIBRATION_SUMMARY_FASTK_CHECK 0
#if 1 //(FOR_DV_SIMULATION_USED==0)
#define ETT_PRINT_FORMAT // Apply for both preloader and ETT
#if 1
#define ETT_PRINT_FORMAT
#endif
#if !CODE_SIZE_REDUCE
@ -553,7 +550,7 @@ typedef enum
//Run Time Config
//#define DUMMY_READ_FOR_TRACKING
#define ZQCS_ENABLE_LP4
#if ENABLE_LP4Y_DFS // @Darren, RT-mrw to HW-zqcal tMRD Violation Report - SW workaround from Robert
#if ENABLE_LP4Y_DFS
#undef ZQCS_ENABLE_LP4
#endif
#ifndef ZQCS_ENABLE_LP4
@ -565,7 +562,7 @@ typedef enum
#define ENABLE_BLOCK_APHY_CLOCK_DFS_OPTION 1
#define ENABLE_REMOVE_MCK8X_UNCERT_LOWPOWER_OPTION 1
#define ENABLE_REMOVE_MCK8X_UNCERT_DFS_OPTION 1
#define RDSEL_TRACKING_EN 1 // @Darren, for SHU0 only (DDR3733 or DDR4266)
#define RDSEL_TRACKING_EN 1
#define RDSEL_TRACKING_TH 2133
#define ENABLE_DFS_SSC_WA 0
#define ENABLE_DDR800_OPEN_LOOP_MODE_OPTION 1
@ -587,12 +584,12 @@ typedef enum
#if !__ETT__
// Preloader: using config CFG_DRAM_CALIB_OPTIMIZATION to identify
#if (FOR_DV_SIMULATION_USED==0) && !defined(SLT)
// Preloader: using config CFG_DRAM_CALIB_OPTIMIZATION to identify
#define SUPPORT_SAVE_TIME_FOR_CALIBRATION CFG_DRAM_CALIB_OPTIMIZATION
#else
// DV simulation, use full calibration flow
#define SUPPORT_SAVE_TIME_FOR_CALIBRATION 0
#endif
#define EMMC_READY CFG_DRAM_CALIB_OPTIMIZATION
@ -632,16 +629,16 @@ typedef enum
//#define USE_CLK26M
#undef DUAL_FREQ_K
#define DUAL_FREQ_K 0 //0 : only K 1 freq(1600), 1: K multi freq
#define DUAL_FREQ_K 0
#undef TDQSCK_PRECALCULATION_FOR_DVFS
#define TDQSCK_PRECALCULATION_FOR_DVFS 0//DQS pre-calculation
#define TDQSCK_PRECALCULATION_FOR_DVFS 0
//#undef CHANNEL_NUM
//#define CHANNEL_NUM 4
#undef REPLACE_DFS_RG_MODE
#define REPLACE_DFS_RG_MODE 1 //Trial run Remove DFS PHY RG mode
#define REPLACE_DFS_RG_MODE 1
#undef ENABLE_DUTY_SCAN_V2
#define ENABLE_DUTY_SCAN_V2 0
@ -664,7 +661,7 @@ typedef enum
#define REDUCE_CALIBRATION_OLYMPUS_ONLY 0
#undef APPLY_LOWPOWER_GOLDEN_SETTINGS
#define APPLY_LOWPOWER_GOLDEN_SETTINGS 0 //Should open APPLY_LOWPOWER_GOLDEN_SETTINGS before SB + 3
#define APPLY_LOWPOWER_GOLDEN_SETTINGS 0
//#undef SPM_CONTROL_AFTERK //Should open SPM_CONTROL_AFTERK before SB + 3
@ -689,13 +686,13 @@ typedef enum
#define GATING_ADJUST_TXDLY_FOR_TRACKING 0
#undef ENABLE_PER_BANK_REFRESH
#define ENABLE_PER_BANK_REFRESH 1 //align bringup setting, Derping
#define ENABLE_PER_BANK_REFRESH 1
#undef ENABLE_TPBR2PBR_REFRESH_TIMING
#define ENABLE_TPBR2PBR_REFRESH_TIMING 1 //align bringup setting, Robert
#define ENABLE_TPBR2PBR_REFRESH_TIMING 1
#undef REFRESH_OVERHEAD_REDUCTION
#define REFRESH_OVERHEAD_REDUCTION 1 //align bringup setting, Derping
#define REFRESH_OVERHEAD_REDUCTION 1
#undef AC_TIMING_DERATE_ENABLE
#define AC_TIMING_DERATE_ENABLE 1
@ -745,18 +742,18 @@ typedef enum
#undef XRTW2W_PERFORM_ENHANCE_TX
#undef XRTR2R_PERFORM_ENHANCE_DQSG_RX_DLY
#ifdef XRTR2W_PERFORM_ENHANCE_RODTEN
#undef XRTR2W_PERFORM_ENHANCE_RODTEN //conflict with ENABLE_RODT_TRACKING, LP4 support only
#undef XRTR2W_PERFORM_ENHANCE_RODTEN
#endif
#endif
#endif
#endif //FIRST_BRING_UP
//======================== RSHMOO Definition =====================================
#define RUNTIME_SHMOO_RELEATED_FUNCTION CFG_DRAM_SAVE_FOR_RUNTIME_SHMOO
#define RUNTIME_SHMOO_RG_BACKUP_NUM (100)
#define RUNTIME_SHMOO_TX 0 //TX RX can't be opened simultaneously
#define RUNTIME_SHMOO_TX 0
#define RUNTIME_SHMOO_RX 0
#if RUNTIME_SHMOO_RELEATED_FUNCTION //if enable rshmoo, close TX OE calibration
#if RUNTIME_SHMOO_RELEATED_FUNCTION
#undef TX_OE_EXTEND
#define TX_OE_EXTEND 1
#undef TX_DQ_OE_SHIFT_LP4
@ -775,19 +772,19 @@ typedef enum
#define RUNTIME_SHMOO_FAST_K 1
#define RUNTIME_SHMOO_TEST_CHANNEL 0 // 0: CHA, 1: CHB
#define RUNTIME_SHMOO_TEST_RANK 0 // 0: RK0, 1: RK1
#define RUNTIME_SHMOO_TEST_BYTE 0 // 0: Byte0, 1: Byte1
#define RUNTIME_SHMOO_TEST_CHANNEL 0
#define RUNTIME_SHMOO_TEST_RANK 0
#define RUNTIME_SHMOO_TEST_BYTE 0
#define RUNTIME_SHMOO_TEST_PI_DELAY_START 0 // 0~63
#define RUNTIME_SHMOO_TEST_PI_DELAY_END 63 // 0~63
#define RUNTIME_SHMOO_TEST_PI_DELAY_START 0
#define RUNTIME_SHMOO_TEST_PI_DELAY_END 63
#define RUNTIME_SHMOO_TEST_PI_DELAY_STEP 1
#define RUNTIME_SHMOO_RX_VREF_RANGE_END 127 //La_fite: 63
#define RUNTIME_SHMOO_RX_TEST_MARGIN 2 //for RX Delay (start:first_pass-margin, end:last_pass +margin)
#define RUNTIME_SHMOO_RX_VREF_RANGE_END 127
#define RUNTIME_SHMOO_RX_TEST_MARGIN 2
#define RUNTIME_SHMOO_TEST_VREF_START 0 // 0~81 : 0~50 is range 0, 51~81 is range 1
#define RUNTIME_SHMOO_TEST_VREF_END 81 // 0~81 : 0~50 is range 0, 51~81 is range 1
#define RUNTIME_SHMOO_TEST_VREF_START 0
#define RUNTIME_SHMOO_TEST_VREF_END 81
#define RUNTIME_SHMOO_TEST_VREF_STEP 1
#endif
//=============================================================================
@ -850,7 +847,7 @@ typedef enum
{
IMP_LOW_FREQ = 0,
IMP_HIGH_FREQ,
IMP_NT_ODTN, // Samsung support only for LP4X
IMP_NT_ODTN,
IMP_VREF_MAX
} DRAMC_IMP_T;
@ -869,11 +866,11 @@ typedef enum
typedef enum
{
DRAM_OK = 0, // OK
DRAM_FAIL, // FAIL
DRAM_OK = 0,
DRAM_FAIL,
DRAM_FAST_K,
DRAM_NO_K,
} DRAM_STATUS_T; // DRAM status type
} DRAM_STATUS_T;
typedef enum
{
@ -888,7 +885,7 @@ typedef enum
{
CKE_FIXOFF = 0,
CKE_FIXON,
CKE_DYNAMIC //After CKE FIX on/off, CKE should be returned to dynamic (control by HW)
CKE_DYNAMIC
} CKE_FIX_OPTION;
typedef enum
@ -930,7 +927,7 @@ typedef enum
LP4_DDR400,
PLL_FREQ_SEL_MAX
} DRAM_PLL_FREQ_SEL_T; // DRAM DFS type
} DRAM_PLL_FREQ_SEL_T;
typedef enum
{
@ -974,14 +971,14 @@ typedef enum
SRAM_SHU7,
#endif
DRAM_DFS_SRAM_MAX
} DRAM_DFS_SRAM_SHU_T; // DRAM SRAM RG type
} DRAM_DFS_SRAM_SHU_T;
typedef enum
{
SHUFFLE_RG = 0,
NONSHUFFLE_RG,
BOTH_SHU_NONSHU_RG,
} RG_SHU_TYPE_T; // RG SHUFFLE type
} RG_SHU_TYPE_T;
typedef enum
{
@ -1037,7 +1034,7 @@ typedef struct _DRAM_DFS_FREQUENCY_TABLE_T
DIV_MODE_T divmode;
DRAM_DFS_SRAM_SHU_T SRAMIdx;
DUTY_CALIBRATION_T duty_calibration_mode;
VREF_CALIBRATION_ENABLE_T vref_calibartion_enable; // CBT/RX/TX vref calibration enable or not
VREF_CALIBRATION_ENABLE_T vref_calibartion_enable;
DDR800_MODE_T ddr_loop_mode;
} DRAM_DFS_FREQUENCY_TABLE_T;
@ -1060,13 +1057,7 @@ typedef enum
RANK_MAX
} DRAM_RANK_T;
/*
* Internal CBT mode enum
* 1. Calibration flow uses vGet_Dram_CBT_Mode to
* differentiate between mixed vs non-mixed LP4
* 2. Declared as dram_cbt_mode[RANK_MAX] internally to
* store each rank's CBT mode type
*/
typedef enum
{
CBT_NORMAL_MODE = 0,
@ -1112,10 +1103,7 @@ typedef enum
PINMUX_MAX
} DRAM_PINMUX;
/* For faster switching between term and un-term operation
* FSP_0: For un-terminated freq.
* FSP_1: For terminated freq.
*/
typedef enum
{
FSP_0 = 0,
@ -1151,17 +1139,13 @@ typedef enum
CBT_PHASE_FALLING
} lp5_cbt_phase_t;
/*
* External CBT mode enum
* Due to MDL structure compatibility (single field for dram CBT mode),
* the below enum is used in preloader to differentiate between dram cbt modes
*/
typedef enum
{
CBT_R0_R1_NORMAL = 0, // Normal mode
CBT_R0_R1_BYTE, // Byte mode
CBT_R0_NORMAL_R1_BYTE, // Mixed mode R0: Normal R1: Byte
CBT_R0_BYTE_R1_NORMAL // Mixed mode R0: Byte R1: Normal
CBT_R0_R1_NORMAL = 0,
CBT_R0_R1_BYTE,
CBT_R0_NORMAL_R1_BYTE,
CBT_R0_BYTE_R1_NORMAL
} DRAM_CBT_MODE_EXTERN_T;
typedef enum
@ -1197,9 +1181,9 @@ typedef enum
typedef enum
{
TEST_ISI_PATTERN = 0, //don't change
TEST_AUDIO_PATTERN = 1, //don't change
TEST_XTALK_PATTERN = 2, //don't change
TEST_ISI_PATTERN = 0,
TEST_AUDIO_PATTERN = 1,
TEST_XTALK_PATTERN = 2,
TEST_WORST_SI_PATTERN,
TEST_TA1_SIMPLE,
TEST_TESTPAT4,
@ -1228,7 +1212,7 @@ typedef enum
TX_DQM_WINDOW_SPEC_OUT = 0xff
} DRAM_TX_PER_BIT_DQM_WINDOW_RESULT_TYPE_T;
// enum for CKE toggle mode (toggle both ranks 1. at the same time (CKE_RANK_DEPENDENT) 2. individually (CKE_RANK_INDEPENDENT))
typedef enum
{
CKE_RANK_INDEPENDENT = 0,
@ -1274,7 +1258,7 @@ enum lpddr5_rpre_mode {
LPDDR5_RPRE_4S_0T = 0,
LPDDR5_RPRE_2S_2T,
LPDDR5_RPRE_0S_4T,
LPDDR5_RPRE_XS_4T, /* X = 2~4tWCK */
LPDDR5_RPRE_XS_4T,
};
enum rxdqs_autok_burst_len {
@ -1313,7 +1297,7 @@ typedef enum
Deviation_RX,
Deviation_TX,
Deviation_MAX
} DRAM_DEVIATION_TYPE_T; // DRAM SHUFFLE RG type
} DRAM_DEVIATION_TYPE_T;
#endif
#if SUPPORT_SAVE_TIME_FOR_CALIBRATION
@ -1367,7 +1351,7 @@ typedef struct _SAVE_TIME_FOR_CALIBRATION_T
#endif
// Write leveling
U8 u1WriteLeveling_bypass_Save[CHANNEL_NUM][RANK_MAX][DQS_BYTE_NUMBER]; //for bypass writeleveling
U8 u1WriteLeveling_bypass_Save[CHANNEL_NUM][RANK_MAX][DQS_BYTE_NUMBER];
// Gating
U8 u1Gating_MCK_Save[CHANNEL_NUM][RANK_MAX][DQS_BYTE_NUMBER];
@ -1399,15 +1383,15 @@ typedef struct _SAVE_TIME_FOR_CALIBRATION_T
#if RUNTIME_SHMOO_RELEATED_FUNCTION
S16 u1RxWinPerbitDQ_firsbypass_Save[CHANNEL_NUM][RANK_MAX][DQ_DATA_WIDTH]; //for bypass rxwindow
U8 u1RxWinPerbitDQ_lastbypass_Save[CHANNEL_NUM][RANK_MAX][DQ_DATA_WIDTH]; //for bypass rxwindow
S16 u1RxWinPerbitDQ_firsbypass_Save[CHANNEL_NUM][RANK_MAX][DQ_DATA_WIDTH];
U8 u1RxWinPerbitDQ_lastbypass_Save[CHANNEL_NUM][RANK_MAX][DQ_DATA_WIDTH];
U8 u1SwImpedanceResule[2][4];
U32 u4RG_Backup[CHANNEL_NUM][RUNTIME_SHMOO_RG_BACKUP_NUM];
RUNTIME_SHMOO_SAVE_PARAMETER_T Runtime_Shmoo_para;
#endif
}SAVE_TIME_FOR_CALIBRATION_T;
#endif // SUPPORT_SAVE_TIME_FOR_CALIBRATION
#endif
#if MRW_CHECK_ONLY
#define MR_NUM 64
@ -1423,18 +1407,18 @@ typedef struct _DRAMC_CTX_T
DRAM_RANK_T rank;
DRAM_PLL_FREQ_SEL_T freq_sel;
DRAM_DRAM_TYPE_T dram_type;
DRAM_FAST_SWITH_POINT_T dram_fsp; // only for LP4, uesless in LP3
DRAM_FAST_SWITH_POINT_T boot_fsp; // for RTMRW DFS
DRAM_ODT_MODE_T odt_onoff;/// only for LP4, uesless in LP3
DRAM_CBT_MODE_T dram_cbt_mode[RANK_MAX]; //only for LP4, useless in LP3
DRAM_DBI_MODE_T DBI_R_onoff[FSP_MAX]; // only for LP4, uesless in LP3
DRAM_DBI_MODE_T DBI_W_onoff[FSP_MAX]; // only for LP4, uesless in LP3
DRAM_FAST_SWITH_POINT_T dram_fsp;
DRAM_FAST_SWITH_POINT_T boot_fsp;
DRAM_ODT_MODE_T odt_onoff;
DRAM_CBT_MODE_T dram_cbt_mode[RANK_MAX];
DRAM_DBI_MODE_T DBI_R_onoff[FSP_MAX];
DRAM_DBI_MODE_T DBI_W_onoff[FSP_MAX];
DRAM_DATA_WIDTH_T data_width;
U32 test2_1;
U32 test2_2;
DRAM_TEST_PATTERN_T test_pattern;
U16 frequency;
U16 freqGroup; /* Used to support freq's that are not in ACTimingTable */
U16 freqGroup;
U16 vendor_id;
U16 revision_id;
U16 density;
@ -1445,13 +1429,13 @@ typedef struct _DRAMC_CTX_T
//U8 enable_tx_scan_vref;
#if PRINT_CALIBRATION_SUMMARY
U32 aru4CalResultFlag[CHANNEL_NUM][RANK_MAX];// record the calibration is fail or success, 0:success, 1: fail
U32 aru4CalExecuteFlag[CHANNEL_NUM][RANK_MAX]; // record the calibration is execute or not, 0:no operate, 1: done
U32 aru4CalResultFlag[CHANNEL_NUM][RANK_MAX];
U32 aru4CalExecuteFlag[CHANNEL_NUM][RANK_MAX];
U32 SWImpCalResult;
U32 SWImpCalExecute;
#if PRINT_CALIBRATION_SUMMARY_FASTK_CHECK
U32 FastKResultFlag[2][RANK_MAX];// record the calibration is fail or success, 0:success, 1: fail
U32 FastKExecuteFlag[2][RANK_MAX]; // record the calibration is execute or not, 0:no operate, 1: done
U32 FastKResultFlag[2][RANK_MAX];
U32 FastKExecuteFlag[2][RANK_MAX];
#endif
#endif
@ -1467,8 +1451,8 @@ typedef struct _DRAMC_CTX_T
#endif
DRAM_DFS_FREQUENCY_TABLE_T *pDFSTable;
DRAM_DFS_REG_SHU_T ShuRGAccessIdx;
lp5_training_mode_t lp5_training_mode; //only for LP5
lp5_cbt_phase_t lp5_cbt_phase; //only for LP5
lp5_training_mode_t lp5_training_mode;
lp5_cbt_phase_t lp5_cbt_phase;
u8 new_cbt_mode;
U8 u1PLLMode;
DRAM_DBI_MODE_T curDBIState;
@ -1524,9 +1508,9 @@ typedef struct _JMETER_DELAYCELL_T
#if PIN_CHECK_TOOL
typedef struct _DEBUG_PIN_INF_FOR_FLASHTOOL_T
{
U16 TOTAL_ERR;//DQ,CA
U16 TOTAL_ERR;
U16 IMP_ERR_FLAG;
U8 WL_ERR_FLAG;//DQS
U8 WL_ERR_FLAG;
U8 CA_ERR_FLAG[CHANNEL_MAX][RANK_MAX];
U8 CA_WIN_SIZE[CHANNEL_MAX][RANK_MAX][CATRAINING_NUM_LP4];
U8 DRAM_PIN_RX_ERR_FLAG[CHANNEL_MAX][RANK_MAX][DQS_BYTE_NUMBER];
@ -1610,11 +1594,11 @@ typedef struct _PROFILING_TIME_T
#define JUST_TO_GLOBAL_VALUE (0)
#define TO_MR (1)
// LP5 MR30
#define MR30_DCAU (Fld(4, 4)) // DCA for upper byte
#define MR30_DCAL (Fld(4, 0)) // DCA for lower byte
// LP5 MR26
#define MR30_DCAU (Fld(4, 4))
#define MR30_DCAL (Fld(4, 0))
#define MR26_DCMU1 (Fld(1, 5))
#define MR26_DCMU0 (Fld(1, 4))
#define MR26_DCML1 (Fld(1, 3))
@ -1622,7 +1606,7 @@ typedef struct _PROFILING_TIME_T
#define MR26_DCM_FLIP (Fld(1, 1))
#define MR26_DCM_START_STOP (Fld(1, 0))
// LP4 MR13
#define MR13_FSP_OP (Fld(1, 7))
#define MR13_FSP_WR (Fld(1, 6))
#define MR13_DMD (Fld(1, 5))

2
src/vendorcode/mediatek/mt8195/include/dramc_register.h
View File

@ -189,7 +189,7 @@
#define Channel_D_DDRPHY_NAO_BASE_ADDRESS 0x0
#undef Channel_A_DDRPHY_DPM_BASE_ADDRESS
#define Channel_A_DDRPHY_DPM_BASE_ADDRESS 0xD0000 //@Darren, 0x90000 + 0x40000 for DV sim
#define Channel_A_DDRPHY_DPM_BASE_ADDRESS 0xD0000
#elif(HAPS_FPFG_A60868 ==0)
#undef Channel_A_DRAMC_AO_BASE_ADDRESS
#define Channel_A_DRAMC_AO_BASE_ADDRESS 0x10230000

46
src/vendorcode/mediatek/mt8195/include/dramc_top.h
View File

@ -96,16 +96,16 @@ typedef struct _AC_TIMING_EXTERNAL_T
U32 AC_TIME_EMI_TRTW_ODT_ON :4;
// U 04
U32 AC_TIME_EMI_REFCNT :8; //(REFFRERUN = 0)
U32 AC_TIME_EMI_REFCNT_FR_CLK :8; //(REFFRERUN = 1)
U32 AC_TIME_EMI_REFCNT :8;
U32 AC_TIME_EMI_REFCNT_FR_CLK :8;
U32 AC_TIME_EMI_TXREFCNT :8;
U32 AC_TIME_EMI_TZQCS :8;
// U 05
U32 AC_TIME_EMI_TRTPD :8; // LP4/LP3, // Olymp_us new
U32 AC_TIME_EMI_TWTPD :8; // LP4/LP3, // Olymp_us new
U32 AC_TIME_EMI_TMRR2W_ODT_OFF :8; // LP4 // Olymp_us new
U32 AC_TIME_EMI_TMRR2W_ODT_ON :8; // LP4 // Olymp_us new
U32 AC_TIME_EMI_TRTPD :8;
U32 AC_TIME_EMI_TWTPD :8;
U32 AC_TIME_EMI_TMRR2W_ODT_OFF :8;
U32 AC_TIME_EMI_TMRR2W_ODT_ON :8;
// U 06
// Byte0
@ -121,19 +121,19 @@ typedef struct _AC_TIMING_EXTERNAL_T
// Byte2
U32 AC_TIME_EMI_TRCD_05T :2;
U32 AC_TIME_EMI_TWR_05T :2;
U32 AC_TIME_EMI_TWTR_05T :2; // Olymp_us modified
U32 AC_TIME_EMI_TWTR_05T :2;
U32 AC_TIME_EMI_TRRD_05T :2;
// Byte3
U32 AC_TIME_EMI_TFAW_05T :2;
U32 AC_TIME_EMI_TRTW_ODT_OFF_05T :2;
U32 AC_TIME_EMI_TRTW_ODT_ON_05T :2;
U32 AC_TIME_EMI_TRTPD_05T :2; // LP4/LP3 // Olymp_us new
U32 AC_TIME_EMI_TRTPD_05T :2;
// U 07
// Byte0
U32 AC_TIME_EMI_TWTPD_05T :2; // LP4/LP3 // Olymp_us new
U32 AC_TIME_EMI_TMRR2W_ODT_OFF_05T :2; // Useless, no 0.5T in Olymp_us and Elbr_us
U32 AC_TIME_EMI_TMRR2W_ODT_ON_05T :2; // Useless, no 0.5T in Olymp_us and Elbr_us
U32 AC_TIME_EMI_TWTPD_05T :2;
U32 AC_TIME_EMI_TMRR2W_ODT_OFF_05T :2;
U32 AC_TIME_EMI_TMRR2W_ODT_ON_05T :2;
}AC_TIMING_EXTERNAL_T;
@ -171,8 +171,8 @@ typedef struct {
typedef struct {
unsigned int type;
unsigned int id_length; /* storage ID lengty */
unsigned char ID[16]; /* storage ID */
unsigned int id_length;
unsigned char ID[16];
u64 DRAM_RANK_SIZE[4];
unsigned int reserved[6];
unsigned int iLPDDR3_MODE_REG_5;
@ -183,7 +183,7 @@ typedef struct {
void setup_dramc_voltage_by_pmic(void);
void switch_dramc_voltage_to_auto_mode(void);
#if ! __ETT__
uint32 mt_set_emis(uint8* emi, uint32 len, bool use_default); //array of emi setting.
uint32 mt_set_emis(uint8* emi, uint32 len, bool use_default);
#endif
#endif
@ -210,8 +210,8 @@ typedef struct {
volatile unsigned int last_fatal_err_flag;
volatile unsigned int fatal_err_flag;
volatile unsigned int storage_api_err_flag;
volatile unsigned int last_gating_err[4][2]; // [channel][rank]
volatile unsigned int gating_err[4][2]; // [channel][rank]
volatile unsigned int last_gating_err[4][2];
volatile unsigned int gating_err[4][2];
unsigned short mr5;
unsigned short mr6;
unsigned short mr7;
@ -240,7 +240,7 @@ typedef struct {
#define ERR_CPU_RW_RK0 (1 << 0)
#define ERR_CPU_RW_RK1 (1 << 1)
/* 0x1f -> bit[4:0] is for DDR reserve mode */
#define DDR_RSV_MODE_ERR_MASK (0x1f)
unsigned int check_last_dram_fatal_exception(void);
@ -254,7 +254,7 @@ void dram_fatal_set_stberr(unsigned int chn, unsigned int rk, unsigned int err_c
void dram_fatal_backup_stberr(void);
void dram_fatal_init_stberr(void);
void dram_fatal_set_err(unsigned int err_code, unsigned int mask, unsigned int offset);
#if 0//DRAM_AUXADC_CONFIG
#if 0
unsigned int get_ch_num_by_auxadc(void);
#endif
@ -288,7 +288,7 @@ unsigned int get_ch_num_by_auxadc(void);
dram_fatal_set_err(0x1, 0x1, OFFSET_DDR_RSV_MODE_FLOW);\
} while(0)
#endif //LAST_DRAMC
#endif
typedef enum {
KSHU0 = 0,
@ -517,13 +517,7 @@ typedef struct _DRAM_CALIBRATION_DATA_T
DRAM_CALIBRATION_SHU_DATA_T data[DRAM_DFS_SRAM_MAX];
} DRAM_CALIBRATION_DATA_T;
/*
* g_dram_storage_api_err_code:
* bit[0:3] -> read api
* bit[4:7] -> write api
* bit[8:11] -> clean api
* bit[12:12] -> data formatted due to fatal exception
*/
#define ERR_NULL_POINTER (0x1)
#define ERR_MAGIC_NUMBER (0x2)
#define ERR_CHECKSUM (0x3)

204
src/vendorcode/mediatek/mt8195/include/sv_c_data_traffic.h
View File

@ -15,18 +15,14 @@
mcSHOW_DBG_MSG((TOSTRING(arg) "=0x%x\n", psra->arg)); \
})
/*
* channel type from sv's view
*/
enum {
SV_CHN_A = 0,
SV_CHN_B
};
/*
* dram type from sv's view
*/
enum {
SV_LPDDR = 0,
SV_LPDDR2,
@ -36,9 +32,7 @@ enum {
SV_LPDDR5
};
/*
* data rate from sv's view
*/
enum {
SV_DDR4266 = 0,
SV_DDR3200,
@ -59,208 +53,96 @@ enum {
SV_DDR2133
};
/*
* cal_sv_rand_args is data traffic from sv to c.
* sv randomizes these arguments for c to control
* calibration.
*/
typedef struct cal_sv_rand_args {
/* >>>>>>>>>> common part begin>>>>>>>>>> */
/*
* 0x4C503435
* "LP45"
*/
int magic;
/*
* 0: channel-a
* 1: channel-b
*/
int calibration_channel;
/*
* 0: rank0
* 1: rank1
*/
int calibration_rank;
/*
* 0: LPDDR
* 1: LPDDR2
* 2: PCDDR3
* 3: LPDDR3
* 4: LPDDR4
* 5: LPDDR5
*/
int dram_type;
/*
* 0: DDR4266
* 1: DDR3200
* 2: DDR1600
* 3: DDR3733
* 4: DDR2400
* 5: DDR1866
* 6: DDR1200
* 7: DDR1333
* 8: DDR800
* 9: DDR1066
* 10: DDR2667
* 11: DDR4800
* 12: DDR5500
* 13: DDR6000
* 14: DDR6400
* 15: DDR2750
* 16: DDR2133
*/
int datarate;
/*
* Data Mask Disable
* 0: enable
* 1: disable
*/
int dmd;
int mr2_value; /* for lp4-wirteleveling*/
int mr2_value;
int mr3_value;
int mr13_value;
int mr12_value;
int mr16_value;
int mr18_value; /* lp5 writeleveling */
int mr20_value; /* lp5 rddqc */
/* ============================= */
int mr18_value;
int mr20_value;
/* >>>>>>>>>> cbt part begin>>>>>>>>>> */
/*
* 0: doesn't run cbt calibration
* 1: run cbt calibration
*/
int cbt;
/*
* 0: rising phase
* 1: falling phase
*/
int cbt_phase;
/*
* 0: training mode1
* 1: training mode2
*/
int cbt_training_mode;
/*
* 0: normal mode
* 1: byte mode
*/
int rk0_cbt_mode;
/*
* 0: normal mode
* 1: byte mode
*/
int rk1_cbt_mode;
/*
* 0: cbt does NOT use autok
* 1: cbt use autok
*/
int cbt_autok;
/*
* autok respi
* 0/1/2/3
*/
int cbt_atk_respi;
/*
* 0: cbt does NOT use new cbt mode
* 1: cbt use new cbt mode
*/
int new_cbt_mode;
/*
* cbt pat0~7v
*/
int pat_v[8];
/*
* cbt pat0~7a
*/
int pat_a[8];
/*
* cbt pat_dmv
*/
int pat_dmv;
/*
* cbt pat_dma
*/
int pat_dma;
/*
* cbt pat_cs
*/
int pat_cs;
/*
* new cbt cagolden sel
*/
int cagolden_sel;
/*
* new cbt invert num
*/
int invert_num;
/* ============================= */
/* >>>>>>>>>> wl part begin>>>>>>>>>> */
/*
* 0: doesn't run wl calibration
* 1: run wl calibration
*/
int wl;
/*
* 0: wl does NOT use autok
* 1: wl use autok
*/
int wl_autok;
/*
* autok respi
* 0/1/2/3
*/
int wl_atk_respi;
/* ============================= */
/* >>>>>>>>>> Gating part begin >>>>>> */
/*
* 0: does not run gating calibration
* 1: run gating calibration
*/
int wl_atk_respi;
int gating;
/*
* 0: SW mode calibration
* 1: HW AUTO calibration
*/
int gating_autok;
int dqsien_autok_pi_offset;
int dqsien_autok_early_break_en;
int dqsien_autok_dbg_mode_en;
/* ============================= */
/* >>>>>>>>>> RDDQC part begin >>>>>> */
/*
* 0: does not run rddq calibration
* 1: run rddq calibration
*/
int rddqc;
int low_byte_invert_golden;
@ -269,42 +151,24 @@ typedef struct cal_sv_rand_args {
int mr_dq_b_golden;
int lp5_mr20_6_golden;
int lp5_mr20_7_golden;
/* ============================= */
/* >>>>>>>>>> TX perbit part begin >>>>>> */
/*
* 0: does not run txperbit calibration
* 1: run txperbit calibration
*/
int tx_perbit;
/*
* 0: does not run txperbit auto calibration
* 1: run txperbit auto calibration
*/
int tx_auto_cal;
int tx_atk_pass_pi_thrd;
int tx_atk_early_break;
/* ============================= */
/* >>>>>>>>>> TX perbit part begin >>>>>> */
/*
* 0: does not run rxperbit calibration
* 1: run rxperbit calibration
*/
int rx_perbit;
/*
* 0: does not run rxperbit auto calibration
* 1: run rxperbit auto calibration
*/
int rx_auto_cal;
int rx_atk_cal_step;
int rx_atk_cal_out_dbg_en;
int rx_atk_cal_out_dbg_sel;
/* ============================= */
} cal_sv_rand_args_t;
void set_psra(cal_sv_rand_args_t *psra);