src/soc/intel/braswell/romstage/romstage.c: Perform RTC init in romstage
soc_rtc_init() is executed in ramstage The soc_rtc_init() needs to be executeed before FSP is called. Move the RTC init from ramstage to romstage. BUG=N/A TEST=Intel CherryHill CRB Change-Id: Ic19c768bf9d9aef7505fb9327e4eedf7212b0057 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/29397 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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@ -3,6 +3,7 @@
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*
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* Copyright (C) 2013 Google Inc.
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* Copyright (C) 2015 Intel Corp.
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* Copyright (C) 2018 Eltan B.V.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@ -43,6 +44,9 @@
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#include <soc/romstage.h>
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#include <soc/smm.h>
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#include <soc/spi.h>
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#include <build.h>
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#include <rtc.h>
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#include <pc80/mc146818rtc.h>
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void program_base_addresses(void)
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{
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@ -89,6 +93,22 @@ static void spi_init(void)
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write32(bcr, reg);
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}
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static void soc_rtc_init(void)
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{
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int rtc_failed = rtc_failure();
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if (rtc_failed) {
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printk(BIOS_ERR,
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"RTC Failure detected. Resetting date to %x/%x/%x%x\n",
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COREBOOT_BUILD_MONTH_BCD,
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COREBOOT_BUILD_DAY_BCD,
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0x20,
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COREBOOT_BUILD_YEAR_BCD);
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}
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cmos_init(rtc_failed);
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}
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static struct chipset_power_state power_state CAR_GLOBAL;
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static void migrate_power_state(int is_recovery)
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@ -172,6 +192,7 @@ void car_soc_pre_console_init(void)
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void car_soc_post_console_init(void)
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{
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/* Continue chipset initialization */
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soc_rtc_init();
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set_max_freq();
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spi_init();
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@ -26,7 +26,6 @@
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <pc80/mc146818rtc.h>
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#include <romstage_handoff.h>
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#include <soc/acpi.h>
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#include <soc/iomap.h>
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@ -149,12 +148,6 @@ static void sc_read_resources(struct device *dev)
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sc_add_io_resources(dev);
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}
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static void sc_rtc_init(void)
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{
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printk(BIOS_SPEW, "%s/%s\n", __FILE__, __func__);
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cmos_init(rtc_failure());
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}
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static void sc_init(struct device *dev)
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{
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int i;
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@ -181,8 +174,6 @@ static void sc_init(struct device *dev)
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/* Route SCI to IRQ9 */
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write32(actl, (read32(actl) & ~SCIS_MASK) | SCIS_IRQ9);
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sc_rtc_init();
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if (config->disable_slp_x_stretch_sus_fail) {
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printk(BIOS_DEBUG, "Disabling slp_x stretching.\n");
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write32(gen_pmcon1,
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