soc/qualcomm/ipq40xx: Enable USB
BUG=chrome-os-partner:49249 TEST=Compiles and Boots and detect USB storage BRANCH=none Change-Id: I9f33adccaabf436c8a8ba08033ff1221ace71aaa Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: f6b18062b7570b6aa71a72ad6185edaf00b48e2d Original-Change-Id: I86a297fc915d4886958f8490dda2c1fa00a6c9d3 Original-Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org> Original-Reviewed-on: https://chromium-review.googlesource.com/333312 Original-Commit-Ready: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: https://review.coreboot.org/14675 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Varadarajan Narayanan
Patrick Georgi
parent
fce799c1b2
commit
3939acaa77
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@ -20,203 +20,275 @@
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#include <soc/iomap.h>
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#include <soc/iomap.h>
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#include <soc/usb.h>
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#include <soc/usb.h>
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#define CRPORT_TX_OVRD_DRV_LO 0x1002
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/**
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#define CRPORT_RX_OVRD_IN_HI 0x1006
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* USB Hardware registers
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#define CRPORT_TX_ALT_BLOCK 0x102d
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*/
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#define PHY_CTRL0_ADDR 0x000
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#define PHY_CTRL1_ADDR 0x004
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#define PHY_CTRL2_ADDR 0x008
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#define PHY_CTRL3_ADDR 0x00C
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#define PHY_CTRL4_ADDR 0x010
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#define PHY_MISC_ADDR 0x024
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#define PHY_IPG_ADDR 0x030
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static u32 * const tcsr_usb_sel = (void *)0x1a4000b0;
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#define PHY_CTRL0_VAL 0xA4600015
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#define PHY_CTRL1_VAL 0x09500000
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#define PHY_CTRL2_VAL 0x00058180
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#define PHY_CTRL3_VAL 0x6DB6DCD6
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#define PHY_CTRL4_VAL 0x836DB6DB
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#define PHY_MISC_VAL 0x3803FB0C
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#define PHY_IPG_VAL 0x47323232
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struct usb_qc_phy {
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#define USB_HOST3_PHY_BASE ((void *)0x8a00000)
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u32 ipcat;
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#define USB_HOST3_BALDUR_PHY_BASE ((void *)0xa6000)
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u32 ctrl;
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#define GCC_USB3_RST_CTRL ((void *)0x0181E038)
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u32 general_cfg;
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u32 ram1;
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u32 hs_phy_ctrl;
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u32 param_ovrd;
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u32 chrg_det_ctrl;
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u32 chrg_det_output;
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u32 alt_irq_en;
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u32 hs_phy_irq_stat;
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u32 cgctl;
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u32 dbg_bus;
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u32 ss_phy_ctrl;
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u32 ss_phy_param1;
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u32 ss_phy_param2;
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u32 crport_data_in;
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u32 crport_data_out;
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u32 crport_cap_addr;
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u32 crport_cap_data;
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u32 crport_ack_read;
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u32 crport_ack_write;
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};
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check_member(usb_qc_phy, crport_ack_write, 0x50);
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static struct usb_qc_phy * const usb_host1_phy = (void *)USB_HOST1_PHY_BASE;
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#define DWC3_GCTL 0xc110
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static struct usb_qc_phy * const usb_host2_phy = (void *)USB_HOST2_PHY_BASE;
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#define DWC3_GUSB3PIPECTL(n) (0xc2c0 + (n * 0x04))
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#define DWC3_GUSB2PHYCFG(n) (0xc200 + (n * 0x04))
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struct usb_dwc3 {
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/* Global USB3 PIPE Control Register */
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u32 sbuscfg0;
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#define DWC3_GUSB3PIPECTL_PHYSOFTRST (1 << 31)
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u32 sbuscfg1;
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#define DWC3_GUSB3PIPECTL_SUSPHY (1 << 17)
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u32 txthrcfg;
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#define DWC3_GCTL_CORESOFTRESET (1 << 11)
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u32 rxthrcfg;
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#define DWC3_GCTL_PRTCAPDIR(n) ((n) << 12)
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u32 ctl;
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#define DWC3_GCTL_PRTCAP_OTG 3
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u32 evten;
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#define DWC3_DCTL_CSFTRST (1 << 30)
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u32 sts;
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#define DWC3_GSNPSID 0xc120
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u8 reserved0[4];
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#define DWC3_DCTL 0xc704
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u32 snpsid;
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u32 gpio;
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u32 uid;
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u32 uctl;
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u64 buserraddr;
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u64 prtbimap;
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u8 reserved1[32];
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u32 dbgfifospace;
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u32 dbgltssm;
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u32 dbglnmcc;
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u32 dbgbmu;
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u32 dbglspmux;
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u32 dbglsp;
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u32 dbgepinfo0;
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u32 dbgepinfo1;
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u64 prtbimap_hs;
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u64 prtbimap_fs;
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u8 reserved2[112];
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u32 usb2phycfg;
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u8 reserved3[60];
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u32 usb2i2cctl;
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u8 reserved4[60];
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u32 usb2phyacc;
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u8 reserved5[60];
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u32 usb3pipectl;
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u8 reserved6[60];
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};
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check_member(usb_dwc3, usb3pipectl, 0x1c0);
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static struct usb_dwc3 * const usb_host1_dwc3 = (void *)USB_HOST1_DWC3_BASE;
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static struct usb_dwc3 * const usb_host2_dwc3 = (void *)USB_HOST2_DWC3_BASE;
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static void setup_dwc3(struct usb_dwc3 *dwc3)
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/* Global USB2 PHY Configuration Register */
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#define DWC3_GUSB2PHYCFG_PHYSOFTRST (1 << 31)
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#define DWC3_GUSB2PHYCFG_SUSPHY (1 << 6)
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#define DWC3_GSNPSID_MASK 0xffff0000
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#define DWC3_GEVTEN 0xc114
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#define DWC3_GCTL_SCALEDOWN(n) ((n) << 4)
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#define DWC3_GCTL_SCALEDOWN_MASK DWC3_GCTL_SCALEDOWN(3)
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#define DWC3_GCTL_DISSCRAMBLE (1 << 3)
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#define DWC3_GCTL_DSBLCLKGTNG (1 << 0)
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#define DWC3_GCTL_U2RSTECN (1 << 16)
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#define DWC3_REVISION_190A 0x5533190a
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#define USB30_HS_PHY_CTRL 0x00000010
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#define SW_SESSVLD (0x01 << 0x1C)
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#define UTMI_OTG_VBUS_VALID (0x01 << 0x14)
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#define USB30_SS_PHY_CTRL 0x00000030
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#define LANE0_PWR_PRESENT (0x01 << 0x18)
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static void setup_dwc3(void);
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/**
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* Write register.
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*
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* @base - PHY base virtual address.
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* @offset - register offset.
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* @val - value to write.
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*/
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static inline void qscratch_write(void *base, u32 offset, u32 val)
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{
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{
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write32(&dwc3->usb3pipectl,
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write32(base + offset, val);
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0x1 << 31 | /* assert PHY soft reset */
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0x1 << 25 | /* (default) U1/U2 exit fail -> recovery? */
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0x1 << 24 | /* (default) activate PHY low power states */
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0x1 << 19 | /* (default) PHY low power delay value */
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0x1 << 18 | /* (default) activate PHY low power delay */
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0x1 << 1 | /* (default) Tx deemphasis value */
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0x1 << 0); /* (default) elastic buffer mode */
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write32(&dwc3->usb2phycfg,
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0x1 << 31 | /* assert PHY soft reset */
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0x9 << 10 | /* (default) PHY clock turnaround 8-bit UTMI+ */
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0x1 << 8 | /* (default) enable PHY sleep in L1 */
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0x1 << 6); /* (default) enable PHY suspend */
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write32(&dwc3->ctl,
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0x2 << 19 | /* (default) suspend clock scaling */
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0x1 << 16 | /* retry SS three times before HS downgrade */
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0x1 << 12 | /* port capability HOST */
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0x1 << 11 | /* assert core soft reset */
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0x1 << 10 | /* (default) sync ITP to refclk */
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0x1 << 2); /* U2 exit after 8us LFPS (instead of 248ns) */
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write32(&dwc3->uctl,
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0x32 << 22 | /* (default) reference clock period in ns */
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0x1 << 15 | /* (default) XHCI compliant device addressing */
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0x10 << 0); /* (default) devices time out after 32us */
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udelay(5);
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clrbits_le32(&dwc3->ctl, 0x1 << 11); /* deassert core soft reset */
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clrbits_le32(&dwc3->usb2phycfg, 0x1 << 31); /* PHY soft reset */
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clrbits_le32(&dwc3->usb3pipectl, 0x1 << 31); /* PHY soft reset */
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}
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}
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static void setup_phy(struct usb_qc_phy *phy)
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/**
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* Write register and read back masked value to confirm it is written
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*
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* @base - base virtual address.
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* @offset - register offset.
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* @mask - register bitmask specifying what should be updated
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* @val - value to write.
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*/
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static inline void qscratch_write_readback(void *base, u32 offset,
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const u32 mask, u32 val)
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{
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{
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write32(&phy->ss_phy_ctrl,
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u32 write_val, tmp = read32(base + offset);
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0x1 << 24 | /* Indicate VBUS power present */
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0x1 << 8 | /* Enable USB3 ref clock to prescaler */
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0x1 << 7 | /* assert SS PHY reset */
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0x19 << 0); /* (default) reference clock multiplier */
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write32(&phy->hs_phy_ctrl,
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tmp &= ~mask; /* retain other bits */
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0x1 << 26 | /* (default) unclamp DPSE/DMSE VLS */
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write_val = tmp | val;
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0x1 << 25 | /* (default) select freeclk for utmi_clk */
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0x1 << 24 | /* (default) unclamp DMSE VLS */
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0x1 << 21 | /* (default) enable UTMI clock */
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0x1 << 20 | /* set OTG VBUS as valid */
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0x1 << 18 | /* use ref clock from core */
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0x1 << 17 | /* (default) unclamp DPSE VLS */
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0x1 << 11 | /* force xo/bias/pll to stay on in suspend */
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0x1 << 9 | /* (default) unclamp IDHV */
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0x1 << 8 | /* (default) unclamp VLS (again???) */
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0x1 << 7 | /* (default) unclamp HV VLS */
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0x7 << 4 | /* select frequency (no idea which one) */
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0x1 << 1); /* (default) "retention enable" */
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write32(&phy->ss_phy_param1,
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write32(base + offset, write_val);
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0x6e << 20 | /* full TX swing amplitude */
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0x20 << 14 | /* (default) 6dB TX deemphasis */
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0x17 << 8 | /* 3.5dB TX deemphasis */
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0x9 << 3); /* (default) LoS detector level */
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write32(&phy->general_cfg, 0x1 << 2); /* set XHCI 1.00 compliance */
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/* Read back to see if val was written */
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tmp = read32(base + offset);
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tmp &= mask; /* clear other bits */
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udelay(5);
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if (tmp != val) {
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clrbits_le32(&phy->ss_phy_ctrl, 0x1 << 7); /* deassert SS PHY reset */
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printk(BIOS_INFO, "write: %x to QSCRATCH: %x FAILED\n",
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val, offset);
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}
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}
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}
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static void crport_handshake(void *capture_reg, void *acknowledge_bit, u32 data)
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static void dwc3_ipq40xx_enable_vbus_valid(void)
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{
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{
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int usec = 100;
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/* Enable VBUS valid for HS PHY*/
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qscratch_write_readback((void *)0x8af8800, USB30_HS_PHY_CTRL,
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SW_SESSVLD, SW_SESSVLD);
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qscratch_write_readback((void *)0x8af8800, USB30_HS_PHY_CTRL,
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UTMI_OTG_VBUS_VALID, UTMI_OTG_VBUS_VALID);
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if (capture_reg)
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/* Enable VBUS valid for SS PHY*/
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write32(capture_reg, data);
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qscratch_write_readback((void *)0x8af8800, USB30_SS_PHY_CTRL,
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LANE0_PWR_PRESENT, LANE0_PWR_PRESENT);
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write32(acknowledge_bit, 0x1 << 0);
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while (read32(acknowledge_bit) && --usec)
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udelay(1);
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if (!usec)
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printk(BIOS_ERR, "CRPORT handshake timed out (0x%08x)\n", data);
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}
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}
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static void crport_write(struct usb_qc_phy *phy, u16 addr, u16 data)
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static void qcom_baldur_hs_phy_init(void)
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{
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{
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crport_handshake(&phy->crport_data_in, &phy->crport_cap_addr, addr);
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u32 reg;
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crport_handshake(&phy->crport_data_in, &phy->crport_cap_data, data);
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crport_handshake(NULL, &phy->crport_ack_write, 0);
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/* assert HS PHY POR reset */
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reg = read32(GCC_USB3_RST_CTRL);
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reg = reg | 0x10;
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write32(GCC_USB3_RST_CTRL, reg);
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mdelay(10);
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/* assert HS PHY SRIF reset */
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reg = read32(GCC_USB3_RST_CTRL);
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reg = reg | 0x4;
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write32(GCC_USB3_RST_CTRL, reg);
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mdelay(10);
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/* deassert HS PHY SRIF reset and program HS PHY registers */
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reg = read32(GCC_USB3_RST_CTRL);
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reg = reg & ~0x4;
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write32(GCC_USB3_RST_CTRL, reg);
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mdelay(10);
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/* perform PHY register writes */
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write32(USB_HOST3_BALDUR_PHY_BASE + PHY_CTRL0_ADDR, PHY_CTRL0_VAL);
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write32(USB_HOST3_BALDUR_PHY_BASE + PHY_CTRL1_ADDR, PHY_CTRL1_VAL);
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write32(USB_HOST3_BALDUR_PHY_BASE + PHY_CTRL2_ADDR, PHY_CTRL2_VAL);
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write32(USB_HOST3_BALDUR_PHY_BASE + PHY_CTRL3_ADDR, PHY_CTRL3_VAL);
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write32(USB_HOST3_BALDUR_PHY_BASE + PHY_CTRL4_ADDR, PHY_CTRL4_VAL);
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write32(USB_HOST3_BALDUR_PHY_BASE + PHY_MISC_ADDR, PHY_MISC_VAL);
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write32(USB_HOST3_BALDUR_PHY_BASE + PHY_IPG_ADDR, PHY_IPG_VAL);
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mdelay(10);
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/* de-assert USB3 HS PHY POR reset */
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reg = read32(GCC_USB3_RST_CTRL);
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reg = reg & ~0x10;
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write32(GCC_USB3_RST_CTRL, reg);
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}
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}
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static void tune_phy(struct usb_qc_phy *phy)
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static void qcom_uni_ss_phy_init(void)
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{
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{
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crport_write(phy, CRPORT_RX_OVRD_IN_HI,
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u32 reg;
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0x1 << 11 | /* Set RX_EQ override? */
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0x4 << 8 | /* Set RX_EQ to 4? */
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/* assert SS PHY POR reset */
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0x1 << 7); /* Enable RX_EQ override */
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reg = read32(GCC_USB3_RST_CTRL);
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crport_write(phy, CRPORT_TX_OVRD_DRV_LO,
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reg = reg | 0x20;
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0x1 << 14 | /* Enable amplitude (override?) */
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write32(GCC_USB3_RST_CTRL, reg);
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0x17 << 7 | /* Set TX deemphasis to 23 */
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0x6e << 0); /* Set amplitude to 110 */
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mdelay(100);
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crport_write(phy, CRPORT_TX_ALT_BLOCK,
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0x1 << 7); /* ALT block? ("partial RX reset") */
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/* deassert SS PHY POR reset */
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reg = read32(GCC_USB3_RST_CTRL);
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reg = reg & ~0x20;
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write32(GCC_USB3_RST_CTRL, reg);
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}
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void setup_dwc3(void)
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{
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u32 reg;
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u32 revision;
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revision = read32(USB_HOST3_PHY_BASE + DWC3_GSNPSID);
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/* This should read as U3 followed by revision number */
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if ((revision & DWC3_GSNPSID_MASK) != 0x55330000)
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printk(BIOS_INFO, "Error in reading Version\n");
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printk(BIOS_INFO, "Version = %x\n", revision);
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/* issue device SoftReset too */
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||||||
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write32(USB_HOST3_PHY_BASE + DWC3_DCTL, DWC3_DCTL_CSFTRST);
|
||||||
|
do {
|
||||||
|
reg = read32(USB_HOST3_PHY_BASE + DWC3_DCTL);
|
||||||
|
if (!(reg & DWC3_DCTL_CSFTRST))
|
||||||
|
break;
|
||||||
|
|
||||||
|
udelay(10);
|
||||||
|
} while (true);
|
||||||
|
printk(BIOS_INFO, "software reset done\n");
|
||||||
|
|
||||||
|
/* Before Resetting PHY, put Core in Reset */
|
||||||
|
reg = read32(USB_HOST3_PHY_BASE + DWC3_GCTL);
|
||||||
|
reg |= DWC3_GCTL_CORESOFTRESET;
|
||||||
|
write32(USB_HOST3_PHY_BASE + DWC3_GCTL, reg);
|
||||||
|
|
||||||
|
/* Assert USB3 PHY reset */
|
||||||
|
reg = read32(USB_HOST3_PHY_BASE + DWC3_GUSB3PIPECTL(0));
|
||||||
|
reg |= DWC3_GUSB3PIPECTL_PHYSOFTRST;
|
||||||
|
write32(USB_HOST3_PHY_BASE + DWC3_GUSB3PIPECTL(0), reg);
|
||||||
|
|
||||||
|
/* Assert USB2 PHY reset */
|
||||||
|
reg = read32(USB_HOST3_PHY_BASE + DWC3_GUSB2PHYCFG(0));
|
||||||
|
reg |= DWC3_GUSB2PHYCFG_PHYSOFTRST;
|
||||||
|
write32(USB_HOST3_PHY_BASE + DWC3_GUSB2PHYCFG(0), reg);
|
||||||
|
|
||||||
|
qcom_baldur_hs_phy_init();
|
||||||
|
qcom_uni_ss_phy_init();
|
||||||
|
mdelay(100);
|
||||||
|
|
||||||
|
/* Clear USB3 PHY reset */
|
||||||
|
reg = read32(USB_HOST3_PHY_BASE + DWC3_GUSB3PIPECTL(0));
|
||||||
|
reg &= ~DWC3_GUSB3PIPECTL_PHYSOFTRST;
|
||||||
|
write32(USB_HOST3_PHY_BASE + DWC3_GUSB3PIPECTL(0), reg);
|
||||||
|
|
||||||
|
/* Clear USB2 PHY reset */
|
||||||
|
reg = read32(USB_HOST3_PHY_BASE + DWC3_GUSB2PHYCFG(0));
|
||||||
|
reg &= ~DWC3_GUSB2PHYCFG_PHYSOFTRST;
|
||||||
|
write32(USB_HOST3_PHY_BASE + DWC3_GUSB2PHYCFG(0), reg);
|
||||||
|
|
||||||
|
mdelay(100);
|
||||||
|
|
||||||
|
/* After PHYs are stable we can take Core out of reset state */
|
||||||
|
reg = read32(USB_HOST3_PHY_BASE + DWC3_GCTL);
|
||||||
|
reg &= ~DWC3_GCTL_CORESOFTRESET;
|
||||||
|
write32(USB_HOST3_PHY_BASE + DWC3_GCTL, reg);
|
||||||
|
|
||||||
|
#if 0
|
||||||
|
/* Enable Suspend USB2.0 HS/FS/LS PHY (SusPHY) */
|
||||||
|
reg = read32(USB_HOST3_PHY_BASE + DWC3_GUSB2PHYCFG(0));
|
||||||
|
reg |= DWC3_GUSB2PHYCFG_SUSPHY;
|
||||||
|
write32(USB_HOST3_PHY_BASE + DWC3_GUSB2PHYCFG(0), reg);
|
||||||
|
|
||||||
|
/* Enable Suspend USB3.0 SS PHY (Suspend_en) */
|
||||||
|
reg = read32(USB_HOST3_PHY_BASE + DWC3_GUSB3PIPECTL(0));
|
||||||
|
reg |= DWC3_GUSB3PIPECTL_SUSPHY;
|
||||||
|
write32(USB_HOST3_PHY_BASE + DWC3_GUSB3PIPECTL(0), reg);
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* configure controller in Host mode */
|
||||||
|
reg = read32(USB_HOST3_PHY_BASE + DWC3_GCTL);
|
||||||
|
reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
|
||||||
|
reg |= DWC3_GCTL_PRTCAPDIR(0x1); /* host mode */
|
||||||
|
write32(USB_HOST3_PHY_BASE + DWC3_GCTL, reg);
|
||||||
|
printk(BIOS_INFO, "USB Host mode reg = %x\n", reg);
|
||||||
|
|
||||||
|
reg = read32(USB_HOST3_PHY_BASE + DWC3_GCTL);
|
||||||
|
reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
|
||||||
|
reg &= ~DWC3_GCTL_DISSCRAMBLE;
|
||||||
|
|
||||||
|
reg &= ~DWC3_GCTL_DSBLCLKGTNG;
|
||||||
|
/*
|
||||||
|
* WORKAROUND: DWC3 revisions <1.90a have a bug
|
||||||
|
* where the device can fail to connect at SuperSpeed
|
||||||
|
* and falls back to high-speed mode which causes
|
||||||
|
* the device to enter a Connect/Disconnect loop
|
||||||
|
*/
|
||||||
|
if (revision < DWC3_REVISION_190A)
|
||||||
|
reg |= DWC3_GCTL_U2RSTECN;
|
||||||
|
|
||||||
|
write32(USB_HOST3_PHY_BASE + DWC3_GCTL, reg);
|
||||||
}
|
}
|
||||||
|
|
||||||
void setup_usb_host1(void)
|
void setup_usb_host1(void)
|
||||||
{
|
{
|
||||||
printk(BIOS_INFO, "Setting up USB HOST1 controller...\n");
|
printk(BIOS_INFO, "Setting up USB HOST1 controller.\n");
|
||||||
setbits_le32(tcsr_usb_sel, 1 << 0); /* Select DWC3 controller */
|
setup_dwc3();
|
||||||
setup_phy(usb_host1_phy);
|
dwc3_ipq40xx_enable_vbus_valid();
|
||||||
setup_dwc3(usb_host1_dwc3);
|
|
||||||
tune_phy(usb_host1_phy);
|
|
||||||
}
|
|
||||||
|
|
||||||
void setup_usb_host2(void)
|
|
||||||
{
|
|
||||||
printk(BIOS_INFO, "Setting up USB HOST2 controller...\n");
|
|
||||||
setbits_le32(tcsr_usb_sel, 1 << 1); /* Select DWC3 controller */
|
|
||||||
setup_phy(usb_host2_phy);
|
|
||||||
setup_dwc3(usb_host2_dwc3);
|
|
||||||
tune_phy(usb_host2_phy);
|
|
||||||
}
|
}
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue