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mb/google/brya/var/agah: Change Aux settings to TCSS port 2 

Agah USB-C port 0 is non-retimer port and it connects to TCSS port 2.

Bit[5:4] is for TCSS Port 2, so re-configure "TcssAuxOri" to 0x10 and "typec_aux_bias_pads" to 2 to correct the port.

BUG=b:210970640
BRANCH=NONE
TEST=emerge-draco coreboot chromeos-bootimage

Change-Id: I2d26777e850187aee0b676de13dff915474fed7b
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63849
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Tony Huang 2022-04-26 11:27:41 +08:00 committed by Felix Held
parent 02944888d6
commit 394057e715
1 changed files with 2 additions and 2 deletions
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4
src/mainboard/google/brya/variants/agah/overridetree.cb
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@ -31,8 +31,8 @@ chip soc/intel/alderlake
}"
register "sagv" = "SaGv_Enabled"
register "tcss_aux_ori" = "1"
register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}"
register "tcss_aux_ori" = "0x10"
register "typec_aux_bias_pads[2]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}"
register "usb2_ports[1]" = "USB2_PORT_EMPTY" # Disable USB2_C1
register "usb2_ports[3]" = "USB2_PORT_EMPTY" # Disable M.2 WWAN