hatch: Create faffy variant
Create the faffy variant of the puff reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.1.1). V.2: Manually modified to keep Kconfig sorted. BUG=b:157448038 BRANCH=None TEST=util/abuild/abuild -p none -t google/hatch -x -a make sure the build includes GOOGLE_FAFFY Signed-off-by: Edward O'Callaghan <quasisec@google.com> Change-Id: I5f14c2d6144ce3c2e48488ca81f31b3c04dc5fb9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42717 Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Edward O'Callaghan
Edward O'Callaghan
parent
cfc170b213
commit
394b5fabf4
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@ -119,6 +119,7 @@ config MAINBOARD_PART_NUMBER
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default "Dratini" if BOARD_GOOGLE_DRATINI
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default "Duffy" if BOARD_GOOGLE_DUFFY
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default "Duffy" if BOARD_GOOGLE_DUFFY_LEGACY
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default "Faffy" if BOARD_GOOGLE_FAFFY
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default "Hatch" if BOARD_GOOGLE_HATCH
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default "Helios" if BOARD_GOOGLE_HELIOS
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default "Helios_Diskswap" if BOARD_GOOGLE_HELIOS_DISKSWAP
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@ -150,6 +151,7 @@ config VARIANT_DIR
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default "dratini" if BOARD_GOOGLE_DRATINI
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default "duffy" if BOARD_GOOGLE_DUFFY
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default "duffy" if BOARD_GOOGLE_DUFFY_LEGACY
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default "faffy" if BOARD_GOOGLE_FAFFY
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default "hatch" if BOARD_GOOGLE_HATCH
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default "helios" if BOARD_GOOGLE_HELIOS
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default "helios" if BOARD_GOOGLE_HELIOS_DISKSWAP
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@ -17,6 +17,10 @@ config BOARD_GOOGLE_DUFFY
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bool "-> Duffy"
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select BOARD_GOOGLE_BASEBOARD_PUFF
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config BOARD_GOOGLE_FAFFY
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bool "-> Faffy"
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select BOARD_GOOGLE_BASEBOARD_PUFF
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config BOARD_GOOGLE_HATCH
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bool "-> Hatch"
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select BOARD_GOOGLE_BASEBOARD_HATCH
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@ -0,0 +1,4 @@
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## SPDX-License-Identifier: GPL-2.0-only
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ramstage-y += gpio.c
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bootblock-y += gpio.c
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@ -0,0 +1,115 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <baseboard/gpio.h>
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#include <baseboard/variants.h>
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#include <commonlib/helpers.h>
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static const struct pad_config gpio_table[] = {
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/* A16 : SD_OC_ODL */
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PAD_CFG_GPI(GPP_A16, NONE, DEEP),
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/* A18 : LAN_PE_ISOLATE_ODL */
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PAD_CFG_GPO(GPP_A18, 1, DEEP),
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/* A23 : M2_WLAN_INT_ODL */
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PAD_CFG_GPI_APIC(GPP_A23, NONE, PLTRST, LEVEL, INVERT),
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/* B5 : LAN_CLKREQ_ODL */
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PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1),
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/* C0 : SMBCLK */
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PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
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/* C1 : SMBDATA */
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PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
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/* C6: M2_WLAN_WAKE_ODL */
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PAD_CFG_GPI_SCI_LOW(GPP_C6, NONE, DEEP, EDGE_SINGLE),
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/* C7 : LAN_WAKE_ODL */
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PAD_CFG_GPI_SCI_LOW(GPP_C7, NONE, DEEP, EDGE_SINGLE),
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/* C10 : PCH_PCON_RST_ODL */
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PAD_CFG_GPO(GPP_C10, 1, DEEP),
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/* C11 : PCH_PCON_PDB_ODL */
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PAD_CFG_GPO(GPP_C11, 1, DEEP),
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/* C15 : WLAN_OFF_L */
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PAD_CFG_GPO(GPP_C15, 1, DEEP),
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/* E2 : EN_PP_MST_OD */
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PAD_CFG_GPO(GPP_E2, 1, DEEP),
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/* E9 : USB_A0_OC_ODL */
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PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),
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/* E10 : USB_A1_OC_ODL */
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PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1),
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/* F11 : EMMC_CMD */
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PAD_CFG_NF(GPP_F11, NONE, DEEP, NF1),
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/* F12 : EMMC_DATA0 */
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PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1),
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/* F13 : EMMC_DATA1 */
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PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1),
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/* F14 : EMMC_DATA2 */
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PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1),
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/* F15 : EMMC_DATA3 */
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PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1),
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/* F16 : EMMC_DATA4 */
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PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1),
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/* F17 : EMMC_DATA5 */
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PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1),
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/* F18 : EMMC_DATA6 */
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PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1),
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/* F19 : EMMC_DATA7 */
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PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),
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/* F20 : EMMC_RCLK */
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PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1),
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/* F21 : EMMC_CLK */
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PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1),
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/* F22 : EMMC_RST_L */
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PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1),
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/* H4: PCH_I2C_PCON_SDA */
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PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
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/* H5: PCH_I2C_PCON_SCL */
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PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
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/* H22 : PWM_PP3300_BIOZZER */
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PAD_CFG_GPO(GPP_H22, 0, DEEP),
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};
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const struct pad_config *override_gpio_table(size_t *num)
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{
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*num = ARRAY_SIZE(gpio_table);
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return gpio_table;
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}
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/* Early pad configuration in bootblock */
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static const struct pad_config early_gpio_table[] = {
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/* B14 : GPP_B14_STRAP */
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PAD_NC(GPP_B14, NONE),
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/* B22 : GPP_B22_STRAP */
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PAD_NC(GPP_B22, NONE),
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/* E19 : GPP_E19_STRAP */
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PAD_NC(GPP_E19, NONE),
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/* E21 : GPP_E21_STRAP */
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PAD_NC(GPP_E21, NONE),
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/* B15 : H1_SLAVE_SPI_CS_L */
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PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1),
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/* B16 : H1_SLAVE_SPI_CLK */
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PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1),
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/* B17 : H1_SLAVE_SPI_MISO_R */
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PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1),
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/* B18 : H1_SLAVE_SPI_MOSI_R */
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PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1),
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/* C14 : BT_DISABLE_L */
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PAD_CFG_GPO(GPP_C14, 0, DEEP),
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/* PCH_WP_OD */
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PAD_CFG_GPI(GPP_C20, NONE, DEEP),
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/* C21 : H1_PCH_INT_ODL */
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PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT),
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/* C23 : WLAN_PE_RST# */
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PAD_CFG_GPO(GPP_C23, 1, DEEP),
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/* E1 : M2_SSD_PEDET */
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PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1),
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/* E5 : SATA_DEVSLP1 */
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PAD_CFG_NF(GPP_E5, NONE, PLTRST, NF1),
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};
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const struct pad_config *variant_early_gpio_table(size_t *num)
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{
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*num = ARRAY_SIZE(early_gpio_table);
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return early_gpio_table;
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}
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@ -0,0 +1,3 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <puff/acpi/dptf.asl>
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@ -0,0 +1,8 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef VARIANT_EC_H
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#define VARIANT_EC_H
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#include <puff/ec.h>
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#endif
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@ -0,0 +1,8 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef VARIANT_GPIO_H
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#define VARIANT_GPIO_H
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#include <baseboard/gpio.h>
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#endif
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@ -0,0 +1,403 @@
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chip soc/intel/cannonlake
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# Enable heci communication
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register "HeciEnabled" = "1"
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# Auto-switch between X4 NVMe and X2 NVMe.
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register "TetonGlacierMode" = "1"
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register "SerialIoDevMode" = "{
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[PchSerialIoIndexI2C0] = PchSerialIoDisabled,
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[PchSerialIoIndexI2C1] = PchSerialIoDisabled,
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[PchSerialIoIndexI2C2] = PchSerialIoPci,
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[PchSerialIoIndexI2C3] = PchSerialIoPci,
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[PchSerialIoIndexI2C4] = PchSerialIoPci,
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[PchSerialIoIndexI2C5] = PchSerialIoPci,
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[PchSerialIoIndexSPI0] = PchSerialIoPci,
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[PchSerialIoIndexSPI1] = PchSerialIoPci,
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[PchSerialIoIndexSPI2] = PchSerialIoDisabled,
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[PchSerialIoIndexUART0] = PchSerialIoSkipInit,
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[PchSerialIoIndexUART1] = PchSerialIoDisabled,
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[PchSerialIoIndexUART2] = PchSerialIoDisabled,
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}"
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# USB configuration
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register "usb2_ports[0]" = "{
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.enable = 1,
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.ocpin = OC2,
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.tx_bias = USB2_BIAS_0MV,
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.tx_emp_enable = USB2_PRE_EMP_ON,
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.pre_emp_bias = USB2_BIAS_11P25MV,
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.pre_emp_bit = USB2_HALF_BIT_PRE_EMP,
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}" # Type-A Port 2
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register "usb2_ports[1]" = "{
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.enable = 1,
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.ocpin = OC1,
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.tx_bias = USB2_BIAS_0MV,
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.tx_emp_enable = USB2_PRE_EMP_ON,
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.pre_emp_bias = USB2_BIAS_28P15MV,
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.pre_emp_bit = USB2_HALF_BIT_PRE_EMP,
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}" # Type-A Port 1
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register "usb2_ports[2]" = "{
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.enable = 1,
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.ocpin = OC3,
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.tx_bias = USB2_BIAS_0MV,
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.tx_emp_enable = USB2_PRE_EMP_ON,
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.pre_emp_bias = USB2_BIAS_28P15MV,
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.pre_emp_bit = USB2_HALF_BIT_PRE_EMP,
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}" # Type-A Port 3
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register "usb2_ports[3]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C Port
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register "usb2_ports[4]" = "{
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.enable = 1,
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.ocpin = OC_SKIP,
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.tx_bias = USB2_BIAS_0MV,
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.tx_emp_enable = USB2_PRE_EMP_ON,
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.pre_emp_bias = USB2_BIAS_28P15MV,
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.pre_emp_bit = USB2_HALF_BIT_PRE_EMP,
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}" # Type-A Port 4
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register "usb2_ports[5]" = "{
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.enable = 1,
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.ocpin = OC0,
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.tx_bias = USB2_BIAS_0MV,
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.tx_emp_enable = USB2_PRE_EMP_ON,
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.pre_emp_bias = USB2_BIAS_28P15MV,
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.pre_emp_bit = USB2_HALF_BIT_PRE_EMP,
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}" # Type-A port 0
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register "usb2_ports[6]" = "USB2_PORT_EMPTY"
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register "usb2_ports[7]" = "USB2_PORT_EMPTY"
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register "usb2_ports[8]" = "USB2_PORT_EMPTY"
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register "usb2_ports[9]" = "{
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.enable = 1,
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.ocpin = OC_SKIP,
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.tx_bias = USB2_BIAS_0MV,
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.tx_emp_enable = USB2_PRE_EMP_ON,
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.pre_emp_bias = USB2_BIAS_28P15MV,
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.pre_emp_bit = USB2_HALF_BIT_PRE_EMP,
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}" # BT
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register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)" # Type-A Port 2
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register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC3)" # Type-A Port 3
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register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port 1
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register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C
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register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC0)" # Type-A Port 0
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register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A Port 4
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# Enable eMMC HS400
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register "ScsEmmcHs400Enabled" = "1"
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# EMMC Tx CMD Delay
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# Refer to EDS-Vol2-14.3.7.
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# [14:8] steps of delay for DDR mode, each 125ps, range: 0 - 39.
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# [6:0] steps of delay for SDR mode, each 125ps, range: 0 - 39.
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register "common_soc_config.emmc_dll.emmc_tx_cmd_cntl" = "0x505"
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# EMMC TX DATA Delay 1
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# Refer to EDS-Vol2-14.3.8.
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# [14:8] steps of delay for HS400, each 125ps, range: 0 - 78.
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# [6:0] steps of delay for SDR104/HS200, each 125ps, range: 0 - 79.
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register "common_soc_config.emmc_dll.emmc_tx_data_cntl1" = "0x911"
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# EMMC TX DATA Delay 2
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# Refer to EDS-Vol2-14.3.9.
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# [30:24] steps of delay for SDR50, each 125ps, range: 0 - 79.
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# [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78.
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# [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 -79.
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# [6:0] steps of delay for SDR12, each 125ps. Range: 0 - 79.
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register "common_soc_config.emmc_dll.emmc_tx_data_cntl2" = "0x1C262828"
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# EMMC RX CMD/DATA Delay 1
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# Refer to EDS-Vol2-14.3.10.
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# [30:24] steps of delay for SDR50, each 125ps, range: 0 - 119.
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# [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78.
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# [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 - 119.
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# [6:0] steps of delay for SDR12, each 125ps, range: 0 - 119.
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register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl1" = "0x1C16583b"
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# EMMC RX CMD/DATA Delay 2
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# Refer to EDS-Vol2-14.3.12.
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# [17:16] stands for Rx Clock before Output Buffer,
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# 00: Rx clock after output buffer,
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# 01: Rx clock before output buffer,
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# 10: Automatic selection based on working mode.
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# 11: Reserved
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# [14:8] steps of delay for Auto Tuning Mode, each 125ps, range: 0 - 39.
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# [6:0] steps of delay for HS200, each 125ps, range: 0 - 79.
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register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl2" = "0x1001D"
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# EMMC Rx Strobe Delay
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# Refer to EDS-Vol2-14.3.11.
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# [14:8] Rx Strobe Delay DLL 1(HS400 Mode), each 125ps, range: 0 - 39.
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# [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps, range: 0 - 39.
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register "common_soc_config.emmc_dll.emmc_rx_strobe_cntl" = "0x1515"
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# Intel HDA - disable I2S Audio SSP1 and DMIC0 as puff variant does not have them.
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register "PchHdaAudioLinkSsp1" = "0"
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register "PchHdaAudioLinkDmic0" = "0"
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# Intel Common SoC Config
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#+-------------------+---------------------------+
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#| Field | Value |
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#+-------------------+---------------------------+
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#| GSPI0 | cr50 TPM. Early init is |
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#| | required to set up a BAR |
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#| | for TPM communication |
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#| | before memory is up |
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#| I2C0 | RFU |
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#| I2C2 | PS175 |
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#| I2C3 | MST |
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#| I2C4 | Audio |
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#+-------------------+---------------------------+
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register "common_soc_config" = "{
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.gspi[0] = {
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.speed_mhz = 1,
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.early_init = 1,
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},
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.i2c[0] = {
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.speed = I2C_SPEED_FAST,
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.rise_time_ns = 0,
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.fall_time_ns = 0,
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},
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.i2c[2] = {
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.speed = I2C_SPEED_FAST,
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.rise_time_ns = 60,
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.fall_time_ns = 60,
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},
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.i2c[3] = {
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.speed = I2C_SPEED_FAST,
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.rise_time_ns = 60,
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.fall_time_ns = 60,
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},
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.i2c[4] = {
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.speed = I2C_SPEED_FAST,
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.rise_time_ns = 60,
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.fall_time_ns = 60,
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},
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}"
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# PCIe port 7 for LAN
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register "PcieRpEnable[6]" = "1"
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register "PcieRpLtrEnable[6]" = "1"
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# PCIe port 11 (x2) for NVMe hybrid storage devices
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register "PcieRpEnable[10]" = "1"
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register "PcieRpLtrEnable[10]" = "1"
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# Uses CLK SRC 0
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register "PcieClkSrcUsage[0]" = "6"
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register "PcieClkSrcClkReq[0]" = "0"
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# GPIO for SD card detect
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register "sdcard_cd_gpio" = "vSD3_CD_B"
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# SATA port 1 Gen3 Strength
|
||||
# Port1 Tx De-Emphasis = 20*log(0x20/64) = -6dB
|
||||
register "sata_port[1].TxGen3DeEmphEnable" = "1"
|
||||
register "sata_port[1].TxGen3DeEmph" = "0x20"
|
||||
|
||||
device domain 0 on
|
||||
device pci 14.0 on
|
||||
chip drivers/usb/acpi
|
||||
device usb 0.0 on
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB2 Type-A Front Left""
|
||||
register "type" = "UPC_TYPE_A"
|
||||
register "group" = "ACPI_PLD_GROUP(0, 0)"
|
||||
device usb 2.0 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB2 Type-C Port Rear""
|
||||
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
|
||||
register "group" = "ACPI_PLD_GROUP(1, 3)"
|
||||
device usb 2.1 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB2 Type-A Front Right""
|
||||
register "type" = "UPC_TYPE_A"
|
||||
register "group" = "ACPI_PLD_GROUP(0, 1)"
|
||||
device usb 2.2 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB2 Type-A Rear Right""
|
||||
register "type" = "UPC_TYPE_A"
|
||||
register "group" = "ACPI_PLD_GROUP(1, 2)"
|
||||
device usb 2.3 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB2 Type-A Rear Middle""
|
||||
register "type" = "UPC_TYPE_A"
|
||||
register "group" = "ACPI_PLD_GROUP(1, 1)"
|
||||
device usb 2.4 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB2 Type-A Rear Left""
|
||||
register "type" = "UPC_TYPE_A"
|
||||
register "group" = "ACPI_PLD_GROUP(1, 0)"
|
||||
device usb 2.5 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
device usb 2.6 off end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB3 Type-A Front Left""
|
||||
register "type" = "UPC_TYPE_USB3_A"
|
||||
register "group" = "ACPI_PLD_GROUP(0, 0)"
|
||||
device usb 3.0 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB3 Type-A Front Right""
|
||||
register "type" = "UPC_TYPE_USB3_A"
|
||||
register "group" = "ACPI_PLD_GROUP(0, 1)"
|
||||
device usb 3.1 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB3 Type-A Rear Right""
|
||||
register "type" = "UPC_TYPE_USB3_A"
|
||||
register "group" = "ACPI_PLD_GROUP(1, 2)"
|
||||
device usb 3.2 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB3 Type-C Rear""
|
||||
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
|
||||
register "group" = "ACPI_PLD_GROUP(1, 3)"
|
||||
device usb 3.3 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB3 Type-A Rear Left""
|
||||
register "type" = "UPC_TYPE_USB3_A"
|
||||
register "group" = "ACPI_PLD_GROUP(1, 0)"
|
||||
device usb 3.4 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB3 Type-A Rear Middle""
|
||||
register "type" = "UPC_TYPE_USB3_A"
|
||||
register "group" = "ACPI_PLD_GROUP(1, 1)"
|
||||
device usb 3.5 on end
|
||||
end
|
||||
end
|
||||
end
|
||||
end # USB xHCI
|
||||
device pci 15.0 off
|
||||
# RFU - Reserved for Future Use.
|
||||
end # I2C #0
|
||||
device pci 15.1 off end # I2C #1
|
||||
device pci 15.2 on
|
||||
chip drivers/i2c/generic
|
||||
register "hid" = ""1AF80175""
|
||||
register "name" = ""PS17""
|
||||
register "desc" = ""Parade PS175""
|
||||
device i2c 4a on end
|
||||
end
|
||||
end # I2C #2, PCON PS175.
|
||||
device pci 15.3 on
|
||||
chip drivers/i2c/generic
|
||||
register "hid" = ""10EC2142""
|
||||
register "name" = ""RTD2""
|
||||
register "desc" = ""Realtek RTD2142""
|
||||
device i2c 4a on end
|
||||
end
|
||||
end # I2C #3, Realtek RTD2142.
|
||||
device pci 19.0 on
|
||||
chip drivers/i2c/generic
|
||||
register "hid" = ""10EC5682""
|
||||
register "name" = ""RT58""
|
||||
register "desc" = ""Realtek RT5682""
|
||||
register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_H0)"
|
||||
register "property_count" = "1"
|
||||
# Set the jd_src to RT5668_JD1 for jack detection
|
||||
register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER"
|
||||
register "property_list[0].name" = ""realtek,jd-src""
|
||||
register "property_list[0].integer" = "1"
|
||||
device i2c 1a on end
|
||||
end
|
||||
end #I2C #4
|
||||
device pci 1a.0 on end # eMMC
|
||||
device pci 1c.6 on
|
||||
chip drivers/net
|
||||
register "customized_leds" = "0x05af"
|
||||
register "wake" = "GPE0_DW1_07" # GPP_C7
|
||||
register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A18)"
|
||||
register "stop_delay_ms" = "12" # NIC needs time to quiesce
|
||||
register "stop_off_delay_ms" = "1"
|
||||
register "has_power_resource" = "1"
|
||||
register "device_index" = "0"
|
||||
device pci 00.0 on end
|
||||
end
|
||||
end # RTL8111H Ethernet NIC
|
||||
device pci 1d.2 on end # PCI Express Port 11 (X2 NVMe)
|
||||
device pci 1e.3 off end # GSPI #1
|
||||
end
|
||||
|
||||
# VR Settings Configuration for 4 Domains
|
||||
#+----------------+-------+-------+-------+-------+
|
||||
#| Domain/Setting | SA | IA | GTUS | GTS |
|
||||
#+----------------+-------+-------+-------+-------+
|
||||
#| Psi1Threshold | 20A | 20A | 20A | 20A |
|
||||
#| Psi2Threshold | 5A | 5A | 5A | 5A |
|
||||
#| Psi3Threshold | 1A | 1A | 1A | 1A |
|
||||
#| Psi3Enable | 1 | 1 | 1 | 1 |
|
||||
#| Psi4Enable | 1 | 1 | 1 | 1 |
|
||||
#| ImonSlope | 0 | 0 | 0 | 0 |
|
||||
#| ImonOffset | 0 | 0 | 0 | 0 |
|
||||
#| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V |
|
||||
#| AcLoadline | 10.04 | 1.81 | 3.19 | 3.19 |
|
||||
#| DcLoadline | 10.04 | 1.81 | 3.19 | 3.19 |
|
||||
#+----------------+-------+-------+-------+-------+
|
||||
#Note: IccMax settings are moved to SoC code
|
||||
register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
|
||||
.vr_config_enable = 1,
|
||||
.psi1threshold = VR_CFG_AMP(20),
|
||||
.psi2threshold = VR_CFG_AMP(5),
|
||||
.psi3threshold = VR_CFG_AMP(1),
|
||||
.psi3enable = 1,
|
||||
.psi4enable = 1,
|
||||
.imon_slope = 0x0,
|
||||
.imon_offset = 0x0,
|
||||
.icc_max = 0,
|
||||
.voltage_limit = 1520,
|
||||
.ac_loadline = 1004,
|
||||
.dc_loadline = 1004,
|
||||
}"
|
||||
|
||||
register "domain_vr_config[VR_IA_CORE]" = "{
|
||||
.vr_config_enable = 1,
|
||||
.psi1threshold = VR_CFG_AMP(20),
|
||||
.psi2threshold = VR_CFG_AMP(5),
|
||||
.psi3threshold = VR_CFG_AMP(1),
|
||||
.psi3enable = 1,
|
||||
.psi4enable = 1,
|
||||
.imon_slope = 0x0,
|
||||
.imon_offset = 0x0,
|
||||
.icc_max = 0,
|
||||
.voltage_limit = 1520,
|
||||
.ac_loadline = 181,
|
||||
.dc_loadline = 181,
|
||||
}"
|
||||
|
||||
register "domain_vr_config[VR_GT_UNSLICED]" = "{
|
||||
.vr_config_enable = 1,
|
||||
.psi1threshold = VR_CFG_AMP(20),
|
||||
.psi2threshold = VR_CFG_AMP(5),
|
||||
.psi3threshold = VR_CFG_AMP(1),
|
||||
.psi3enable = 1,
|
||||
.psi4enable = 1,
|
||||
.imon_slope = 0x0,
|
||||
.imon_offset = 0x0,
|
||||
.icc_max = 0,
|
||||
.voltage_limit = 1520,
|
||||
.ac_loadline = 319,
|
||||
.dc_loadline = 319,
|
||||
}"
|
||||
|
||||
register "domain_vr_config[VR_GT_SLICED]" = "{
|
||||
.vr_config_enable = 1,
|
||||
.psi1threshold = VR_CFG_AMP(20),
|
||||
.psi2threshold = VR_CFG_AMP(5),
|
||||
.psi3threshold = VR_CFG_AMP(1),
|
||||
.psi3enable = 1,
|
||||
.psi4enable = 1,
|
||||
.imon_slope = 0x0,
|
||||
.imon_offset = 0x0,
|
||||
.icc_max = 0,
|
||||
.voltage_limit = 1520,
|
||||
.ac_loadline = 319,
|
||||
.dc_loadline = 319,
|
||||
}"
|
||||
|
||||
end
|
||||
Loading…
Reference in New Issue