x86: bootblock: remove linking and program flow from build system
The build system was previously determining the flow and linking scripts bootblock code by the order of files added to the bootblock_inc bootblock-y variables.Those files were then concatenated together and built by a myriad of make rules. Now bootblock.S and bootblock.ld is added so that bootblock can be built and linked using the default build rules. CHIPSET_BOOTBLOCK_INCLUDE is introduced in order to allow the chipset code to place include files in the path of the bootblock program -- a replacement for the chipset_bootblock_inc make variable. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built vortex, rambi, and some asus boards. Change-Id: Ida4571cbe6eed65e77ade98b8d9ad056353c53f9 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11495 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Aaron Durbin
parent
6c950da54c
commit
3953e3947d
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@ -67,65 +67,41 @@ CBFS_BASE_ADDRESS=$(call int-add, $(call int-subtract, 0xffffffff $(CONFIG_CBFS_
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ifeq ($(CONFIG_ARCH_BOOTBLOCK_X86_32)$(CONFIG_ARCH_BOOTBLOCK_X86_64),y)
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bootblock-srcs += $(src)/arch/x86/failover.ld
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bootblock-srcs += $(src)/cpu/x86/16bit/entry16.ld
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bootblock-srcs += $(src)/cpu/x86/16bit/reset16.ld
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bootblock-srcs += $(src)/arch/x86/id.ld
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ifeq ($(CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE),y)
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bootblock-srcs += $(src)/cpu/intel/fit/fit.ld
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endif
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# Add the assembly file that pulls in the rest of the dependencies in
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# the right order. Make sure the auto generated bootblock.inc is a proper
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# dependency. Make the same true for the linker sript.
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bootblock-y += bootblock.S
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$(obj)/arch/x86/bootblock.bootblock.o: $(objgenerated)/bootblock.inc
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# TODO: Why can't this use the real bootblock-y += xxx.S mechanism instead?
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bootblock_inc = $(src)/arch/x86/prologue.inc
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bootblock_inc += $(src)/cpu/x86/16bit/entry16.inc
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bootblock_inc += $(src)/cpu/x86/16bit/reset16.inc
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bootblock_inc += $(src)/cpu/x86/32bit/entry32.inc
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bootblock_inc += $(src)/arch/x86/id.inc
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ifeq ($(CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE),y)
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bootblock_inc += $(src)/cpu/intel/fit/fit.inc
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endif
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bootblock_inc += $(chipset_bootblock_inc)
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ifeq ($(CONFIG_SSE),y)
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bootblock_inc += $(src)/cpu/x86/sse_enable.inc
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endif
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bootblock_inc += $(objgenerated)/bootblock.inc
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bootblock_inc += $(src)/arch/x86/walkcbfs.S
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bootblock-y += bootblock.ld
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$(obj)/arch/x86/bootblock.bootblock.ld: $(objgenerated)/bootblock.ld
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bootblock_romccflags := -mcpu=i386 -O2 -D__PRE_RAM__ -D__BOOTBLOCK__
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ifeq ($(CONFIG_SSE),y)
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bootblock_romccflags := -mcpu=k7 -msse -O2 -D__PRE_RAM__ -D__BOOTBLOCK__
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endif
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$(objgenerated)/bootblock.ld: $$(filter %.ld,$$(bootblock-objs))
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# This is a hack in case there are no per chipset linker files.
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$(objgenerated)/empty:
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touch $@
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$(objgenerated)/bootblock.ld: $$(filter-out $(obj)/arch/x86/bootblock.bootblock.ld, $$(filter %.ld,$$(bootblock-objs))) $(objgenerated)/empty
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@printf " GEN $(subst $(obj)/,,$(@))\n"
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cat $^ >> $@.tmp
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mv $@.tmp $@
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$(objgenerated)/bootblock_inc.S: $$(bootblock_inc)
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@printf " GEN $(subst $(obj)/,,$(@))\n"
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printf '$(foreach crt0,$(bootblock_inc),#include "$(crt0)"\n)' > $@
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$(objgenerated)/bootblock.o: $(objgenerated)/bootblock.s
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@printf " CC $(subst $(obj)/,,$(@))\n"
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$(CC_bootblock) $(CFLAGS_bootblock) -c -o $@ $< > $(basename $@).disasm
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$(objgenerated)/bootblock.s: $(objgenerated)/bootblock_inc.S $(obj)/config.h $(obj)/build.h
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@printf " CC $(subst $(obj)/,,$(@))\n"
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$(CC_bootblock) -MMD -x assembler-with-cpp -E -I$(src)/include -I$(src)/arch/x86/include -I$(obj) -include $(obj)/build.h -include $(obj)/config.h -I. -I$(src) $< -o $@
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$(objgenerated)/bootblock.inc: $(src)/arch/x86/$(subst ",,$(CONFIG_BOOTBLOCK_SOURCE)) $(objutil)/romcc/romcc $(OPTION_TABLE_H) $(KCONFIG_AUTOHEADER)
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@printf " ROMCC $(subst $(obj)/,,$(@))\n"
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$(CC_bootblock) $(CPPFLAGS_bootblock) -MM -MT$(objgenerated)/bootblock.inc \
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$< > $(objgenerated)/bootblock.inc.d
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$(ROMCC) -c -S $(bootblock_romccflags) -I. $(CPPFLAGS_bootblock) $< -o $@
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$(objcbfs)/bootblock.debug: $(objgenerated)/bootblock.o $(objgenerated)/bootblock.ld
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$(objcbfs)/bootblock.debug: $(obj)/arch/x86/bootblock.bootblock.o $(obj)/arch/x86/bootblock.bootblock.ld
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@printf " LINK $(subst $(obj)/,,$(@))\n"
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ifeq ($(CONFIG_ARCH_BOOTBLOCK_X86_32),y)
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$(LD_bootblock) -m elf_i386 --oformat elf32-i386 -static -o $@ -L$(obj) $< -T $(objgenerated)/bootblock.ld
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$(LD_bootblock) -m elf_i386 --oformat elf32-i386 -static -o $@ -L$(obj) $< -T $(obj)/arch/x86/bootblock.bootblock.ld
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else
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$(LD_bootblock) -m elf_x86_64 --oformat elf64-x86-64 -static -o $@ -L$(obj) $< -T $(objgenerated)/bootblock.ld
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$(LD_bootblock) -m elf_x86_64 --oformat elf64-x86-64 -static -o $@ -L$(obj) $< -T $(obj)/arch/x86/bootblock.bootblock.ld
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endif
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@ -0,0 +1,51 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2015 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc.
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*/
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/* This file assembles the bootblock program by the order of the includes. Thus,
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* it's extremely important that one pays very careful attention to the order
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* of the includes. */
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#include <arch/x86/prologue.inc>
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#include <cpu/x86/16bit/entry16.inc>
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#include <cpu/x86/16bit/reset16.inc>
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#include <cpu/x86/32bit/entry32.inc>
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#include <arch/x86/id.inc>
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#if IS_ENABLED(CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE)
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#include <cpu/intel/fit/fit.inc>
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#endif
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#ifdef CONFIG_CHIPSET_BOOTBLOCK_INCLUDE
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#include CONFIG_CHIPSET_BOOTBLOCK_INCLUDE
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#endif
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#if IS_ENABLED(CONFIG_SSE)
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#include <cpu/x86/sse_enable.inc>
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#endif
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/*
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* This bootblock.inc file is generated by ROMCC. The above program flow
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* falls through to this point. ROMCC assumes the last function it parsed
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* is the main function and it places its instructions at the beginning of
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* the generated file. Moreover, any library/common code needed in bootblock
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* needs to come after bootblock.inc.
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*/
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#include <generated/bootblock.inc>
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#include <arch/x86/walkcbfs.S>
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@ -0,0 +1,29 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2015 Google Inc
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc.
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*/
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#include <arch/x86/failover.ld>
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#include <cpu/x86/16bit/entry16.ld>
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#include <cpu/x86/16bit/reset16.ld>
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#include <arch/x86/id.ld>
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#if IS_ENABLED(CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE)
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#include <cpu/intel/fit/fit.ld>
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#endif
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/* Include generated .ld files. */
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#include <generated/bootblock.ld>
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@ -1,3 +1,5 @@
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#include <build.h>
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.section ".id", "a", @progbits
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.globl __id_start
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@ -77,4 +77,8 @@ config PLL_500_375_33
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endchoice
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config CHIPSET_BOOTBLOCK_INCLUDE
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string
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default "cpu/dmp/vortex86ex/chipset_bootblock.inc"
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endif
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@ -23,8 +23,6 @@ subdirs-y += ../../x86/lapic
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subdirs-y += ../../x86/cache
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subdirs-y += ../../x86/smm
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chipset_bootblock_inc += $(src)/cpu/dmp/vortex86ex/biosdata.inc
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chipset_bootblock_inc += $(src)/cpu/dmp/vortex86ex/biosdata_ex.inc
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bootblock-y += biosdata.ld
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bootblock-y += biosdata_ex.ld
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@ -37,7 +37,7 @@
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.section ".dmp_kbd_fw_part1", "a", @progbits
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#include "src/cpu/dmp/vortex86ex/dmp_kbd_fw_part1.inc"
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#include "dmp_kbd_fw_part1.inc"
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.previous
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@ -0,0 +1,2 @@
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#include "biosdata.inc"
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#include "biosdata_ex.inc"
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@ -3,3 +3,11 @@ config NORTHBRIDGE_VIA_VX800
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select HAVE_DEBUG_RAM_SETUP
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select HAVE_DEBUG_SMBUS
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select LATE_CBMEM_INIT
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if NORTHBRIDGE_VIA_VX800
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config CHIPSET_BOOTBLOCK_INCLUDE
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string
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default "northbridge/via/vx800/romstrap.inc"
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endif
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@ -25,7 +25,6 @@ ramstage-y += vga.c
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ramstage-y += lpc.c
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ramstage-y += ide.c
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chipset_bootblock_inc += $(src)/northbridge/via/vx800/romstrap.inc
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bootblock-y += romstrap.ld
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endif
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@ -42,4 +42,8 @@ config VGA_BIOS_ID
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string
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default "1106,7122"
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config CHIPSET_BOOTBLOCK_INCLUDE
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string
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default "northbridge/via/vx900/romstrap.inc"
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endif
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@ -46,7 +46,6 @@ ramstage-y += lpc.c
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ramstage-y += ./../../../drivers/pc80/vga/vga_io.c
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chipset_bootblock_inc += $(src)/northbridge/via/vx900/romstrap.inc
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bootblock-y += romstrap.ld
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endif
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@ -171,4 +171,8 @@ config REFCODE_BLOB_FILE
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endif # HAVE_REFCODE_BLOB
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config CHIPSET_BOOTBLOCK_INCLUDE
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string
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default "soc/intel/baytrail/bootblock/timestamp.inc"
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endif
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@ -1,6 +1,5 @@
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ifeq ($(CONFIG_SOC_INTEL_BAYTRAIL),y)
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subdirs-y += bootblock
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subdirs-y += microcode
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subdirs-y += romstage
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subdirs-y += ../../../cpu/x86/lapic
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@ -1 +0,0 @@
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chipset_bootblock_inc += $(src)/soc/intel/baytrail/bootblock/timestamp.inc
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@ -198,4 +198,8 @@ config ME_BIN_PATH
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depends on HAVE_ME_BIN
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default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/me.bin"
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config CHIPSET_BOOTBLOCK_INCLUDE
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string
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default "soc/intel/braswell/bootblock/timestamp.inc"
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endif
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@ -1,6 +1,5 @@
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ifeq ($(CONFIG_SOC_INTEL_BRASWELL),y)
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subdirs-y += bootblock
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subdirs-y += microcode
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subdirs-y += romstage
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subdirs-y += ../../../cpu/x86/lapic
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@ -1 +0,0 @@
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chipset_bootblock_inc += $(src)/soc/intel/braswell/bootblock/timestamp.inc
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@ -272,4 +272,8 @@ config LOCK_MANAGEMENT_ENGINE
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If unsure, say N.
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config CHIPSET_BOOTBLOCK_INCLUDE
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string
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default "soc/intel/broadwell/bootblock/timestamp.inc"
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endif
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@ -1,6 +1,5 @@
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ifeq ($(CONFIG_SOC_INTEL_BROADWELL),y)
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subdirs-y += bootblock
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subdirs-y += microcode
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subdirs-y += romstage
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subdirs-y += ../../../cpu/x86/lapic
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@ -1 +0,0 @@
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chipset_bootblock_inc += $(src)/soc/intel/broadwell/bootblock/timestamp.inc
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@ -200,4 +200,8 @@ config UART_DEBUG
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select DRIVERS_UART_8250MEM
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select DRIVERS_UART_8250MEM_32
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config CHIPSET_BOOTBLOCK_INCLUDE
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string
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default "soc/intel/skylake/bootblock/timestamp.inc"
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endif
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@ -1,6 +1,5 @@
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ifeq ($(CONFIG_SOC_INTEL_SKYLAKE),y)
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subdirs-y += bootblock
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subdirs-y += microcode
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subdirs-y += romstage
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subdirs-y += ../../../cpu/intel/microcode
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@ -1 +0,0 @@
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chipset_bootblock_inc += $(src)/soc/intel/skylake/bootblock/timestamp.inc
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@ -41,4 +41,9 @@ config CK804_NUM
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config HPET_MIN_TICKS
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hex
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default 0xfa
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config CHIPSET_BOOTBLOCK_INCLUDE
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string
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default "southbridge/nvidia/ck804/romstrap.inc"
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endif
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@ -21,7 +21,6 @@ romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += enable_usbdebug.c
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ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c
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romstage-y += early_smbus.c
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chipset_bootblock_inc += $(src)/southbridge/nvidia/ck804/romstrap.inc
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bootblock-y += romstrap.ld
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endif
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@ -42,4 +42,8 @@ config MCP55_PCI_E_X_3
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int
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default 4
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config CHIPSET_BOOTBLOCK_INCLUDE
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string
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default "southbridge/nvidia/mcp55/romstrap.inc"
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endif
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@ -24,7 +24,6 @@ ifeq ($(CONFIG_MCP55_USE_AZA),y)
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ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/hda_verb.c
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endif
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chipset_bootblock_inc += $(src)/southbridge/nvidia/mcp55/romstrap.inc
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bootblock-y += romstrap.ld
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endif
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@ -4,10 +4,18 @@ config SOUTHBRIDGE_SIS_SIS966
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select HAVE_USBDEBUG
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select HAVE_HARD_RESET
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if SOUTHBRIDGE_SIS_SIS966
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config BOOTBLOCK_SOUTHBRIDGE_INIT
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string
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default "southbridge/sis/sis966/bootblock.c" if SOUTHBRIDGE_SIS_SIS966
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default "southbridge/sis/sis966/bootblock.c"
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config EHCI_BAR
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hex
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default 0xfef00000 if SOUTHBRIDGE_SIS_SIS966
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default 0xfef00000
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config CHIPSET_BOOTBLOCK_INCLUDE
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string
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default "southbridge/sis/sis966/romstrap.inc"
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endif
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@ -15,7 +15,6 @@ ramstage-y += reset.c
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romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += enable_usbdebug.c
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ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c
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chipset_bootblock_inc += $(src)/southbridge/sis/sis966/romstrap.inc
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bootblock-y += romstrap.ld
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endif
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@ -51,4 +51,8 @@ config VIDEO_MB
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default -1 if K8M890_VIDEO_MB_CMOS
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depends on SOUTHBRIDGE_VIA_K8M890_VGA_EN
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config CHIPSET_BOOTBLOCK_INCLUDE
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string
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default "southbridge/via/k8t890/romstrap.inc"
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endif # SOUTHBRIDGE_K8T890
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@ -10,7 +10,6 @@ ramstage-y += traf_ctrl.c
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ramstage-y += error.c
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ramstage-y += chrome.c
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|
||||
chipset_bootblock_inc += $(src)/southbridge/via/k8t890/romstrap.inc
|
||||
bootblock-y += romstrap.ld
|
||||
|
||||
endif
|
||||
|
|
|
|||
Loading…
Reference in New Issue