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mainboard/intel/cannonlake_rvp: SMBus, SAGV and Skip FSP MPInit in devicetree 

Set SMBus, SAGV and Skip FSP MPInit configuration from devicetree.cb

Change-Id: Ic810b003bf7fb13447d5d5dcd49cfcc31785b440
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/21198
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Pratik Prajapati 2017-08-24 17:35:55 -07:00 committed by Aaron Durbin
parent 9027e1ba2f
commit 39648bb54b
2 changed files with 10 additions and 0 deletions
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5
src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb
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@ -4,6 +4,11 @@ chip soc/intel/cannonlake
device lapic 0 on end device lapic 0 on end
end end
# FSP configuration
register "SaGv" = "3"
register "FspSkipMpInit" = "1"
register "SmbusEnable" = "1"
device domain 0 on device domain 0 on
device pci 00.0 on end # Host Bridge device pci 00.0 on end # Host Bridge
device pci 02.0 on end # Integrated Graphics Device device pci 02.0 on end # Integrated Graphics Device

5
src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb
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@ -4,6 +4,11 @@ chip soc/intel/cannonlake
device lapic 0 on end device lapic 0 on end
end end
# FSP configuration
register "SaGv" = "3"
register "FspSkipMpInit" = "1"
register "SmbusEnable" = "1"
device domain 0 on device domain 0 on
device pci 00.0 on end # Host Bridge device pci 00.0 on end # Host Bridge
device pci 02.0 on end # Integrated Graphics Device device pci 02.0 on end # Integrated Graphics Device