arch/riscv: Enable U-mode/S-mode counters (stime, etc.)

Change-Id: Ie62f60b2e237fa4921384e3894569ae29639f563
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/16262
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

src/arch/riscv/virtual_memory.c

@@ -218,4 +218,8 @@ void mstatus_init(void)
 			| (1 << CAUSE_FAULT_STORE)
 			| (1 << CAUSE_USER_ECALL)
 	);
+
+	/* Enable all user/supervisor-mode counters */
+	write_csr(mscounteren, 0b111);
+	write_csr(mucounteren, 0b111);
 }