From 397c15026ecd449b81cbc2beb714175ee911e3e7 Mon Sep 17 00:00:00 2001 From: Jonathon Hall Date: Fri, 21 Jul 2023 13:33:59 -0400 Subject: [PATCH] soc/intel/jasperlake: Set GPE_STS and GPE_EN register bases Jasper Lake was missing these bases, so attempting to enable an SCI would poke unrelated registers starting from offset 0. Set them so GPEs can be enabled. GPE is used on the Librem 11 for the keyboard dock connector, its sense signal on GPP_D4 raises a GPE which is used to indicate tablet/laptop mode to the OS. The register offsets are documented in the datasheet volume 2 (Intel document 634545), all groups' GPE_STS/GPE_EN start at the same offsets. Change-Id: Ib6b9b9a79e9cc4467e609eaf591ec4e87b78d617 Signed-off-by: Jonathon Hall Reviewed-on: https://review.coreboot.org/c/coreboot/+/78097 Reviewed-by: Eric Lai Tested-by: build bot (Jenkins) --- src/soc/intel/jasperlake/gpio.c | 10 ++++++++++ src/soc/intel/jasperlake/include/soc/gpio_defs.h | 2 ++ 2 files changed, 12 insertions(+) diff --git a/src/soc/intel/jasperlake/gpio.c b/src/soc/intel/jasperlake/gpio.c index 42eb183aff..3376aaa245 100644 --- a/src/soc/intel/jasperlake/gpio.c +++ b/src/soc/intel/jasperlake/gpio.c @@ -74,6 +74,8 @@ static const struct pad_community jsl_communities[TOTAL_GPIO_COMM] = { .host_own_reg_0 = HOSTSW_OWN_REG_0, .gpi_int_sts_reg_0 = GPI_INT_STS_0, .gpi_int_en_reg_0 = GPI_INT_EN_0, + .gpi_gpe_sts_reg_0 = GPI_GPE_STS_0, + .gpi_gpe_en_reg_0 = GPI_GPE_EN_0, .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, .gpi_smi_en_reg_0 = GPI_SMI_EN_0, .gpi_nmi_sts_reg_0 = GPI_NMI_STS_0, @@ -96,6 +98,8 @@ static const struct pad_community jsl_communities[TOTAL_GPIO_COMM] = { .host_own_reg_0 = HOSTSW_OWN_REG_0, .gpi_int_sts_reg_0 = GPI_INT_STS_0, .gpi_int_en_reg_0 = GPI_INT_EN_0, + .gpi_gpe_sts_reg_0 = GPI_GPE_STS_0, + .gpi_gpe_en_reg_0 = GPI_GPE_EN_0, .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, .gpi_smi_en_reg_0 = GPI_SMI_EN_0, .gpi_nmi_sts_reg_0 = GPI_NMI_STS_0, @@ -118,6 +122,8 @@ static const struct pad_community jsl_communities[TOTAL_GPIO_COMM] = { .host_own_reg_0 = HOSTSW_OWN_REG_0, .gpi_int_sts_reg_0 = GPI_INT_STS_0, .gpi_int_en_reg_0 = GPI_INT_EN_0, + .gpi_gpe_sts_reg_0 = GPI_GPE_STS_0, + .gpi_gpe_en_reg_0 = GPI_GPE_EN_0, .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, .gpi_smi_en_reg_0 = GPI_SMI_EN_0, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, @@ -138,6 +144,8 @@ static const struct pad_community jsl_communities[TOTAL_GPIO_COMM] = { .host_own_reg_0 = HOSTSW_OWN_REG_0, .gpi_int_sts_reg_0 = GPI_INT_STS_0, .gpi_int_en_reg_0 = GPI_INT_EN_0, + .gpi_gpe_sts_reg_0 = GPI_GPE_STS_0, + .gpi_gpe_en_reg_0 = GPI_GPE_EN_0, .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, .gpi_smi_en_reg_0 = GPI_SMI_EN_0, .gpi_nmi_sts_reg_0 = GPI_NMI_STS_0, @@ -160,6 +168,8 @@ static const struct pad_community jsl_communities[TOTAL_GPIO_COMM] = { .host_own_reg_0 = HOSTSW_OWN_REG_0, .gpi_int_sts_reg_0 = GPI_INT_STS_0, .gpi_int_en_reg_0 = GPI_INT_EN_0, + .gpi_gpe_sts_reg_0 = GPI_GPE_STS_0, + .gpi_gpe_en_reg_0 = GPI_GPE_EN_0, .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, .gpi_smi_en_reg_0 = GPI_SMI_EN_0, .gpi_nmi_sts_reg_0 = GPI_NMI_STS_0, diff --git a/src/soc/intel/jasperlake/include/soc/gpio_defs.h b/src/soc/intel/jasperlake/include/soc/gpio_defs.h index 8f6f5f7298..09d50e733d 100644 --- a/src/soc/intel/jasperlake/include/soc/gpio_defs.h +++ b/src/soc/intel/jasperlake/include/soc/gpio_defs.h @@ -249,6 +249,8 @@ #define HOSTSW_OWN_REG_0 0xc0 #define GPI_INT_STS_0 0x100 #define GPI_INT_EN_0 0x120 +#define GPI_GPE_STS_0 0x140 +#define GPI_GPE_EN_0 0x160 #define GPI_SMI_STS_0 0x180 #define GPI_SMI_EN_0 0x1a0 #define GPI_NMI_STS_0 0x1c0