From 3990da0bfe18e3b76751fd35fef9e5ec55c2fd29 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Mon, 15 Nov 2021 17:25:54 +0200 Subject: [PATCH] soc/intel/denverton_ns: Fix MRC_RW_CACHE MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit It is required to set WPD (Write Protect Disable) bit to make it possible to use MRC_RW_CACHE region with CACHE_MRC_SETTINGS=y. Change-Id: Iacab44b00d08c9bdc18bc3bdcb88833634c0b02e Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/60091 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/soc/intel/denverton_ns/bootblock/bootblock.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/soc/intel/denverton_ns/bootblock/bootblock.c b/src/soc/intel/denverton_ns/bootblock/bootblock.c index cb2503ae40..0846c8e474 100644 --- a/src/soc/intel/denverton_ns/bootblock/bootblock.c +++ b/src/soc/intel/denverton_ns/bootblock/bootblock.c @@ -84,6 +84,7 @@ void bootblock_soc_early_init(void) #if (CONFIG(CONSOLE_SERIAL)) early_uart_init(); #endif + fast_spi_early_init(DEFAULT_SPI_BASE); }; void bootblock_soc_init(void)