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soc/intel: Hook up `SOC_INTEL_DISABLE_IGD` to `InternalGfx` UPD 

Commit 0591348833 introduced this Kconfig
option inside soc/intel/common scope. However, it was only hooked up in
commit d74cd60b81 for Alder Lake, and in
commit 99157c1f4a for Tiger Lake. Hook up
the `SOC_INTEL_DISABLE_IGD` Kconfig option to all other platforms which
have the `InternalGfx` UPD.

Change-Id: Icd1379a835b445a6d4b028ebde5a3e355ee5b67b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52100
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Angel Pons 2021-04-05 11:40:11 +02:00 committed by Patrick Georgi
parent 691020e22b
commit 3993d38ae6
4 changed files with 7 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
src/soc/intel/cannonlake/romstage/fsp_params.c
View File

@ -12,6 +12,7 @@
#include <soc/msr.h>
#include <soc/pci_devs.h>
#include <soc/romstage.h>
#include <types.h>
#include <vendorcode/google/chromeos/chromeos.h>
#include "../chip.h"
@ -29,7 +30,8 @@ static void soc_memory_init_params(FSPM_UPD *mupd, const config_t *config)
* Probe for no IGD and disable InternalGfx and panel power to prevent a
* crash in FSP-M.
*/
if (dev && dev->enabled && pci_read_config16(SA_DEV_IGD, PCI_VENDOR_ID) != 0xffff) {
const bool igd_on = !CONFIG(SOC_INTEL_DISABLE_IGD) && dev && dev->enabled;
if (igd_on && pci_read_config16(SA_DEV_IGD, PCI_VENDOR_ID) != 0xffff) {
/* Set IGD stolen size to 64MB. */
m_cfg->InternalGfx = 1;
m_cfg->IgdDvmt50PreAlloc = 2;

4
src/soc/intel/icelake/romstage/fsp_params.c
View File

@ -16,8 +16,8 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
const struct device *dev = pcidev_path_on_root(SA_DEVFN_IGD);
uint32_t mask = 0;
if (!dev || !dev->enabled) {
/* Skip IGD initialization in FSP if device is disabled in devicetree.cb. */
if (CONFIG(SOC_INTEL_DISABLE_IGD) || !dev || !dev->enabled) {
/* Skip IGD initialization in FSP if device is disabled */
m_cfg->InternalGfx = 0;
m_cfg->IgdDvmt50PreAlloc = 0;
} else {

2
src/soc/intel/jasperlake/romstage/fsp_params.c
View File

@ -22,7 +22,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
* Otherwise, skip IGD init in FSP.
*/
dev = pcidev_path_on_root(SA_DEVFN_IGD);
m_cfg->InternalGfx = is_dev_enabled(dev);
m_cfg->InternalGfx = !CONFIG(SOC_INTEL_DISABLE_IGD) && is_dev_enabled(dev);
m_cfg->IgdDvmt50PreAlloc = m_cfg->InternalGfx ? 0xFE : 0;
m_cfg->TsegSize = CONFIG_SMM_TSEG_SIZE;

2
src/soc/intel/skylake/romstage/fsp_params.c
View File

@ -112,7 +112,7 @@ static void soc_primary_gfx_config_params(FSP_M_CONFIG *m_cfg,
const struct device *dev;
dev = pcidev_path_on_root(SA_DEVFN_IGD);
m_cfg->InternalGfx = dev && dev->enabled;
m_cfg->InternalGfx = !CONFIG(SOC_INTEL_DISABLE_IGD) && dev && dev->enabled;
/*
* If iGPU is enabled, set IGD stolen size to 64MB. The FBC