soc/intel/cannonlake: Add postcar stage support

Initialize postcar frame once finish FSP memoryinit

Change-Id: I888d471fa620b7fc9f8975524a31f662e1fc5079
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/20534
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Lijian Zhao 2017-07-11 12:33:22 -07:00 committed by Martin Roth
parent 4cfae2f574
commit 399c022a8c
5 changed files with 38 additions and 4 deletions

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@ -43,6 +43,7 @@ postcar-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c
postcar-$(CONFIG_FSP_CAR) += temp_ram_exit.c
postcar-$(CONFIG_FSP_CAR) += util.c
postcar-$(CONFIG_DISPLAY_FSP_HEADER) += header_display.c
postcar-y += hand_off_block.c
CPPFLAGS_common += -I$(src)/drivers/intel/fsp2_0/include

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@ -23,6 +23,8 @@ config CPU_SPECIFIC_OPTIONS
select HAVE_INTEL_FIRMWARE
select INTEL_CAR_NEM_ENHANCED
select PLATFORM_USES_FSP2_0
select POSTCAR_CONSOLE
select POSTCAR_STAGE
select RELOCATABLE_RAMSTAGE
select SOC_INTEL_COMMON
select SOC_INTEL_COMMON_BLOCK_SA

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@ -5,20 +5,23 @@ subdirs-y += ../../../cpu/intel/microcode
subdirs-y += ../../../cpu/x86/mtrr
subdirs-y += ../../../cpu/x86/tsc
bootblock-$(CONFIG_DRIVERS_UART_8250MEM) += uart.c
bootblock-y += bootblock/bootblock.c
bootblock-y += bootblock/cpu.c
bootblock-y += bootblock/pch.c
bootblock-y += bootblock/report_platform.c
bootblock-y += gpio.c
bootblock-$(CONFIG_UART_DEBUG) += uart.c
romstage-y += cbmem.c
romstage-y += reset.c
romstage-$(CONFIG_DRIVERS_UART_8250MEM) += uart.c
romstage-$(CONFIG_UART_DEBUG) += uart.c
ramstage-y += cbmem.c
ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += reset.c
ramstage-$(CONFIG_DRIVERS_UART_8250MEM) += uart.c
ramstage-$(CONFIG_UART_DEBUG) += uart.c
postcar-y += memmap.c
postcar-$(CONFIG_UART_DEBUG) += uart.c
CPPFLAGS_common += -I$(src)/soc/intel/cannonlake/include/fsp20
CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp2_0/cannonlake

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@ -14,6 +14,10 @@
*/
#include <arch/io.h>
#include <arch/symbols.h>
#include <assert.h>
#include <cpu/x86/mtrr.h>
#include <cpu/x86/msr.h>
#include <cbmem.h>
#include <console/console.h>
#include <fsp/util.h>
@ -25,6 +29,8 @@
asmlinkage void car_stage_entry(void)
{
bool s3wake;
struct postcar_frame pcf;
uintptr_t top_of_ram;
struct chipset_power_state *ps;
console_init();
@ -36,7 +42,25 @@ asmlinkage void car_stage_entry(void)
timestamp_add_now(TS_START_ROMSTAGE);
s3wake = ps->prev_sleep_state == ACPI_S3;
fsp_memory_init(s3wake);
die("Get out from FSP memoryinit. \n");
if (postcar_frame_init(&pcf, 1 * KiB))
die("Unable to initialize postcar frame.\n");
/*
* We need to make sure ramstage will be run cached. At this
* point exact location of ramstage in cbmem is not known.
* Instruct postcar to cache 16 megs under cbmem top which is
* a safe bet to cover ramstage.
*/
top_of_ram = (uintptr_t) cbmem_top();
printk(BIOS_DEBUG, "top_of_ram = 0x%lx\n", top_of_ram);
top_of_ram -= 16*MiB;
postcar_frame_add_mtrr(&pcf, top_of_ram, 16*MiB, MTRR_TYPE_WRBACK);
/* Cache the ROM as WP just below 4GiB. */
postcar_frame_add_mtrr(&pcf, 0xFFFFFFFF - CONFIG_ROM_SIZE + 1,
CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT);
run_postcar_phase(&pcf);
}
void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)

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@ -13,6 +13,8 @@
* GNU General Public License for more details.
*/
#define __SIMPLE_DEVICE__
#include <assert.h>
#include <console/uart.h>
#include <device/pci_def.h>
@ -60,8 +62,10 @@ void pch_uart_init(void)
gpio_configure_pads(p->pads, ARRAY_SIZE(p->pads));
}
#if IS_ENABLED(CONFIG_DRIVERS_UART_8250MEM)
uintptr_t uart_platform_base(int idx)
{
/* We can only have one serial console at a time */
return UART_DEBUG_BASE_ADDRESS;
}
#endif