soc/amd/picasso: Update southbridge
Picasso's FCH has many similarities to Stoney Ridge, so few changes are necessary. The most notable changes are: * Update the index values for the C00/C01 interrupt routing * FORCE_STPCLK_RETRY is not present * PCIB is not defined * FCH MISC Registers 0xfed80e00 numbering has changed * C-state base moves from PM register to MSR * Add option to determine the intended MUX settion for LPC vs. eMMC * Remove the LEGACY_FREE option Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: I69dfc4a875006639aa330385680d150331840e40 Reviewed-on: https://review.coreboot.org/c/coreboot/+/33770 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Marshall Dawson
Martin Roth
parent
06fd982030
commit
39a4ac1502
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@ -178,12 +178,6 @@ config AHCI_ROM_ID
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endif # PICASSO_SATA_MODE = 2 || PICASSO_SATA_MODE = 5
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config PICASSO_LEGACY_FREE
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bool "System is legacy free"
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help
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Select y if there is no keyboard controller in the system.
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This sets a variable in ACPI.
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config SERIRQ_CONTINUOUS_MODE
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bool
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default n
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@ -251,6 +245,12 @@ config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ
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int
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default 133
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config PICASSO_LPC_IOMUX
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bool
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help
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Picasso's LPC bus signals are MUXed with some of the EMMC signals.
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Select this option if LPC signals are required.
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config MAINBOARD_POWER_RESTORE
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def_bool n
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help
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@ -135,7 +135,7 @@ void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt)
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fadt->day_alrm = 0; /* 0x7d these have to be */
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fadt->mon_alrm = 0; /* 0x7e added to cmos.layout */
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fadt->century = 0; /* 0x7f to make rtc alarm work */
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fadt->iapc_boot_arch = FADT_BOOT_ARCH; /* See table 5-10 */
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fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042;
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fadt->res2 = 0; /* reserved, MUST be 0 ACPI 3.0 */
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fadt->flags = ACPI_FADT_WBINVD | /* See table 5-10 ACPI 3.0a spec */
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ACPI_FADT_C1_SUPPORTED |
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@ -20,12 +20,6 @@
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#include <arch/acpi.h>
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#if CONFIG(PICASSO_LEGACY_FREE)
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#define FADT_BOOT_ARCH ACPI_FADT_LEGACY_FREE
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#else
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#define FADT_BOOT_ARCH (ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042)
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#endif
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#ifndef FADT_PM_PROFILE
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#define FADT_PM_PROFILE PM_UNSPECIFIED
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#endif
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@ -2,7 +2,7 @@
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2014 Sage Electronic Engineering, LLC.
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* Copyright (C) 2017 Advanced Micro Devices, Inc.
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* Copyright (C) 2019 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@ -21,7 +21,10 @@
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* PIRQ and device routing - these define the index into the
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* FCH PCI_INTR 0xC00/0xC01 interrupt routing table.
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*/
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/*
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* PIRQ and device routing - these define the index into the
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* FCH PCI_INTR 0xC00/0xC01 interrupt routing table.
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*/
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#define PIRQ_NC 0x1f /* Not Used */
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#define PIRQ_A 0x00 /* INT A */
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#define PIRQ_B 0x01 /* INT B */
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@ -31,7 +34,7 @@
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#define PIRQ_F 0x05 /* INT F */
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#define PIRQ_G 0x06 /* INT G */
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#define PIRQ_H 0x07 /* INT H */
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#define PIRQ_MISC 0x08 /* Miscellaneous IRQ Settings - See FCH Spec */
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#define PIRQ_MISC 0x08 /* Miscellaneous IRQ Settings */
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#define PIRQ_MISC0 0x09 /* Miscellaneous0 IRQ Settings */
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#define PIRQ_MISC1 0x0a /* Miscellaneous1 IRQ Settings */
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#define PIRQ_MISC2 0x0b /* Miscellaneous2 IRQ Settings */
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@ -40,22 +43,39 @@
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#define PIRQ_SIRQC 0x0e /* Serial IRQ INTC */
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#define PIRQ_SIRQD 0x0f /* Serial IRQ INTD */
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#define PIRQ_SCI 0x10 /* SCI IRQ */
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#define PIRQ_SMBUS 0x11 /* SMBUS 14h.0 */
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#define PIRQ_SMBUS 0x11 /* SMBUS */
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#define PIRQ_ASF 0x12 /* ASF */
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#define PIRQ_HDA 0x13 /* HDA 14h.2 */
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#define PIRQ_FC 0x14 /* FC */
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/* 0x13-0x15 reserved */
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#define PIRQ_PMON 0x16 /* Performance Monitor */
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#define PIRQ_SD 0x17 /* SD */
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#define PIRQ_SDIO 0x1a /* SDIO */
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#define PIRQ_EHCI 0x30 /* USB EHCI 12h.0 */
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#define PIRQ_XHCI 0x34 /* USB XHCI 10h.0 */
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#define PIRQ_SATA 0x41 /* SATA 11h.0 */
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/* 0x1b-0x1f reserved */
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#define PIRQ_CIR 0x20 /* CIR, no IRQ connected */
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#define PIRQ_GPIOA 0x21 /* GPIOa from PAD_FANIN0 */
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#define PIRQ_GPIOB 0x22 /* GPIOb from PAD_FANOUT0 */
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#define PIRQ_GPIOC 0x23 /* GPIOc no IRQ connected */
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/* 0x24-0x48 reserved */
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#define PIRQ_SATA 0x41 /* SATA */
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/* 0x42 reserved */
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#define PIRQ_EMMC 0x43 /* eMMC */
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/* 0x44-0x4f reserved */
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#define PIRQ_GPP0 0x50 /* GPPInt0 */
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#define PIRQ_GPP1 0x51 /* GPPInt1 */
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#define PIRQ_GPP2 0x52 /* GPPInt2 */
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#define PIRQ_GPP3 0x53 /* GPPInt3 */
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/* 0x54-0x61 reserved */
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#define PIRQ_GPIO 0x62 /* GPIO Controller Interrupt */
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#define PIRQ_I2C0 0x70
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#define PIRQ_I2C1 0x71
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#define PIRQ_I2C2 0x72
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#define PIRQ_I2C3 0x73
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#define PIRQ_UART0 0x74
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#define PIRQ_UART1 0x75
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/* 0x63-0x6f reserved */
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#define PIRQ_I2C0 0x70 /* I2C0 */
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#define PIRQ_I2C1 0x71 /* I2C1 */
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#define PIRQ_I2C2 0x72 /* I2C2 */
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#define PIRQ_I2C3 0x73 /* I2C3 */
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#define PIRQ_UART0 0x74 /* UART0 */
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#define PIRQ_UART1 0x75 /* UART1 */
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#define PIRQ_I2C4 0x76 /* I2C4 */
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#define PIRQ_I2C5 0x77 /* I2C5 */
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#define PIRQ_UART2 0x78 /* UART2 */
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#define PIRQ_UART3 0x79 /* UART3 */
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/* 0x7a-0x7f reserved */
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#endif /* __AMD_PCI_INT_DEFS_H__ */
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@ -1,7 +1,7 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2017 Advanced Micro Devices, Inc.
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* Copyright (C) 2019 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@ -21,6 +21,8 @@
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#define SOC_EARLY_VMTRR_FLASH 1
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#define SOC_EARLY_VMTRR_TEMPRAM 2
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#define CSTATE_BASE_REG 0xc0010073
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void picasso_init_cpus(struct device *dev);
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int get_cpu_count(void);
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void check_mca(void);
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@ -30,15 +30,14 @@
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/* Power management registers: 0xfed80300 or index/data at IO 0xcd6/cd7 */
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#define PM_DECODE_EN 0x00
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#define SMBUS_ASF_IO_EN BIT(4)
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#define CF9_IO_EN BIT(1)
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#define LEGACY_IO_EN BIT(0)
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#define SMB_ASF_IO_BASE 0x01 /* part of PM_DECODE_EN in PPR */
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#define PM_ISA_CONTROL 0x04
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#define MMIO_EN BIT(1)
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#define PM_PCI_CTRL 0x08
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#define FORCE_SLPSTATE_RETRY BIT(25)
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#define FORCE_STPCLK_RETRY BIT(24)
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#define SMB_ASF_IO_BASE 0x01 /* part of PM_DECODE_EN */
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#define PWR_RESET_CFG 0x10
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#define TOGGLE_ALL_PWR_GOOD BIT(1)
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@ -94,8 +93,6 @@
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#define PM_RST_CTRL1 0xbe
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#define SLPTYPE_CONTROL_EN BIT(5)
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#define PM_RST_STATUS 0xc0
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#define PM_PCIB_CFG 0xea
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#define PM_GENINT_DISABLE BIT(0)
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#define PM_LPC_GATING 0xec
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#define PM_LPC_AB_NO_BYPASS_EN BIT(2)
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#define PM_LPC_A20_EN BIT(1)
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@ -105,13 +102,13 @@
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/* SMBUS MMIO offsets 0xfed80a00 */
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#define SMBHSTSTAT 0x0
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#define SMBHST_STAT_FAILED 0x10
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#define SMBHST_STAT_COLLISION 0x08
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#define SMBHST_STAT_ERROR 0x04
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#define SMBHST_STAT_INTERRUPT 0x02
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#define SMBHST_STAT_BUSY 0x01
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#define SMBHST_STAT_FAILED BIT(4)
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#define SMBHST_STAT_COLLISION BIT(3)
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#define SMBHST_STAT_ERROR BIT(2)
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#define SMBHST_STAT_INTERRUPT BIT(1)
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#define SMBHST_STAT_BUSY BIT(0)
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#define SMBHST_STAT_CLEAR 0xff
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#define SMBHST_STAT_NOERROR 0x02
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#define SMBHST_STAT_NOERROR BIT(1)
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#define SMBHST_STAT_VAL_BITS 0x1f
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#define SMBHST_STAT_ERROR_BITS 0x1c
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@ -149,32 +146,27 @@
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/* FCH MISC Registers 0xfed80e00 */
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#define GPP_CLK_CNTRL 0x00
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#define GPP_CLK2_REQ_MAP_SHIFT 8
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#define GPP_CLK2_REQ_MAP_MASK (0xf << GPP_CLK2_REQ_MAP_SHIFT)
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#define GPP_CLK2_REQ_MAP_CLK_REQ2 3
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#define GPP_CLK0_REQ_MAP_SHIFT 0
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#define GPP_CLK0_REQ_MAP_MASK (0xf << GPP_CLK0_REQ_MAP_SHIFT)
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#define GPP_CLK0_REQ_MAP_CLK_REQ0 1
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#define GPP_CLK0_REQ_SHL 0
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#define GPP_CLK1_REQ_SHL 2
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#define GFX_CLK0_REQ_SHL 4
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#define GPP_CLK2_REQ_SHL 6
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#define GPP_CLK3_REQ_SHL 8
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#define GFX_CLK1_REQ_SHL 10
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#define GPP_CLK_REQ_MAP_MASK0 (3 << GPP_CLK0_REQ_SHL)
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#define GPP_CLK_REQ_MAP_CLK0 (1 << GPP_CLK0_REQ_SHL)
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#define GPP_CLK_REQ_MAP_MASK1 (3 << GPP_CLK1_REQ_SHL)
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#define GPP_CLK_REQ_MAP_CLK1 (1 << GPP_CLK1_REQ_SHL)
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#define GFX_CLK_REQ_MAP_MASK0 (3 << GFX_CLK0_REQ_SHL)
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#define GFX_CLK_REQ_MAP_CLK0 (1 << GFX_CLK0_REQ_SHL)
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#define GPP_CLK_REQ_MAP_MASK2 (3 << GPP_CLK2_REQ_SHL)
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#define GPP_CLK_REQ_MAP_CLK2 (1 << GPP_CLK2_REQ_SHL)
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#define GPP_CLK_REQ_MAP_MASK3 (3 << GPP_CLK3_REQ_SHL)
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#define GPP_CLK_REQ_MAP_CLK3 (1 << GPP_CLK3_REQ_SHL)
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#define GFX_CLK_REQ_MAP_MASK1 (3 << GPP_CLK1_REQ_SHL)
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#define GFX_CLK_REQ_MAP_CLK1 (1 << GPP_CLK1_REQ_SHL)
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#define MISC_CGPLL_CONFIG1 0x08
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#define CG1PLL_SPREAD_SPECTRUM_ENABLE BIT(0)
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#define MISC_CGPLL_CONFIG3 0x10
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#define CG1PLL_REFDIV_SHIFT 0
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#define CG1PLL_REFDIV_MASK (0x3ff << CG1PLL_REFDIV_SHIFT)
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#define CG1PLL_FBDIV_SHIFT 10
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#define CG1PLL_FBDIV_MASK (0xfff << CG1PLL_FBDIV_SHIFT)
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#define MISC_CGPLL_CONFIG4 0x14
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#define SS_STEP_SIZE_DSFRAC_SHIFT 0
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#define SS_STEP_SIZE_DSFRAC_MASK (0xffff << SS_STEP_SIZE_DSFRAC_SHIFT)
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#define SS_AMOUNT_DSFRAC_SHIFT 16
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#define SS_AMOUNT_DSFRAC_MASK (0xffff << SS_AMOUNT_DSFRAC_SHIFT)
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#define MISC_CGPLL_CONFIG5 0x18
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#define SS_AMOUNT_NFRAC_SLIP_SHIFT 8
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#define SS_AMOUNT_NFRAC_SLIP_MASK (0xf << SS_AMOUNT_NFRAC_SLIP_SHIFT)
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#define MISC_CGPLL_CONFIG6 0x1c
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#define CG1PLL_LF_MODE_SHIFT 9
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#define CG1PLL_LF_MODE_MASK (0x1ff << CG1PLL_LF_MODE_SHIFT)
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#define MISC_CLK_CNTL1 0x40
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#define CG1PLL_FBDIV_TEST BIT(26)
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#define BP_X48M0_OUTPUT_EN BIT(2) /* 1=En, unlike Hudson, Kern */
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#define OSCOUT1_CLK_OUTPUT_ENB BIT(2) /* 0 = Enabled, 1 = Disabled */
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#define OSCOUT2_CLK_OUTPUT_ENB BIT(7) /* 0 = Enabled, 1 = Disabled */
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@ -215,7 +207,9 @@
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#define FCH_AOAC_DEV_I2C4 9
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#define FCH_AOAC_DEV_UART0 11
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#define FCH_AOAC_DEV_UART1 12
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#define FCH_AOAC_DEV_UART2 16
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#define FCH_AOAC_DEV_AMBA 17
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#define FCH_AOAC_DEV_ESPI 27
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/* Bit definitions for Device D3 Control AOACx0000[40...7E] step 2 */
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#define FCH_AOAC_TARGET_DEVICE_STATE (BIT(0) + BIT(1))
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@ -323,8 +317,8 @@ void southbridge_final(void *chip_info);
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void southbridge_init(void *chip_info);
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void sb_read_mode(u32 mode);
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void sb_set_spi100(u16 norm, u16 fast, u16 alt, u16 tpm);
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void bootblock_fch_early_init(void);
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void bootblock_fch_init(void);
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void fch_pre_init(void);
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void fch_early_init(void);
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/**
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* @brief Save the UMA bize
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*
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@ -163,7 +163,6 @@ static void sb_slp_typ_handler(void)
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/* Do not send SMI before AcpiPm1CntBlkx00[SlpTyp] */
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pci_ctrl = pm_read32(PM_PCI_CTRL);
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pci_ctrl &= ~FORCE_SLPSTATE_RETRY;
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pci_ctrl |= FORCE_STPCLK_RETRY;
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pm_write32(PM_PCI_CTRL, pci_ctrl);
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/* Enable SlpTyp */
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@ -17,6 +17,7 @@
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#include <device/mmio.h>
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#include <bootstate.h>
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#include <cpu/x86/smm.h>
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#include <cpu/x86/msr.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ops.h>
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@ -26,6 +27,7 @@
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#include <amdblocks/acpimmio.h>
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#include <amdblocks/lpc.h>
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#include <amdblocks/acpi.h>
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#include <soc/cpu.h>
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#include <soc/southbridge.h>
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#include <soc/smbus.h>
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#include <soc/smi.h>
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@ -54,6 +56,7 @@ const static int aoac_devs[] = {
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FCH_AOAC_DEV_I2C2,
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FCH_AOAC_DEV_I2C3,
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FCH_AOAC_DEV_I2C4,
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FCH_AOAC_DEV_ESPI,
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};
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/*
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@ -69,7 +72,7 @@ const static struct irq_idx_name irq_association[] = {
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{ PIRQ_C, "INTC#" },
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{ PIRQ_D, "INTD#" },
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{ PIRQ_E, "INTE#" },
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{ PIRQ_F, "INTF#" },
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{ PIRQ_F, "INTF#/GENINT2" },
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{ PIRQ_G, "INTG#" },
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{ PIRQ_H, "INTH#" },
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{ PIRQ_MISC, "Misc" },
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@ -83,14 +86,19 @@ const static struct irq_idx_name irq_association[] = {
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{ PIRQ_SCI, "SCI" },
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{ PIRQ_SMBUS, "SMBUS" },
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{ PIRQ_ASF, "ASF" },
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{ PIRQ_HDA, "HDA" },
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{ PIRQ_FC, "FC" },
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{ PIRQ_PMON, "PerMon" },
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{ PIRQ_SD, "SD" },
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{ PIRQ_SDIO, "SDIOt" },
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{ PIRQ_EHCI, "EHCI" },
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{ PIRQ_XHCI, "XHCI" },
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{ PIRQ_SDIO, "SDIO" },
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{ PIRQ_CIR, "CIR" },
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{ PIRQ_GPIOA, "GPIOa" },
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{ PIRQ_GPIOB, "GPIOb" },
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{ PIRQ_GPIOC, "GPIOc" },
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{ PIRQ_SATA, "SATA" },
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{ PIRQ_EMMC, "eMMC" },
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{ PIRQ_GPP0, "GPP0" },
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{ PIRQ_GPP1, "GPP1" },
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{ PIRQ_GPP2, "GPP2" },
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{ PIRQ_GPP3, "GPP3" },
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{ PIRQ_GPIO, "GPIO" },
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{ PIRQ_I2C0, "I2C0" },
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{ PIRQ_I2C1, "I2C1" },
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@ -98,6 +106,10 @@ const static struct irq_idx_name irq_association[] = {
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{ PIRQ_I2C3, "I2C3" },
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{ PIRQ_UART0, "UART0" },
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{ PIRQ_UART1, "UART1" },
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{ PIRQ_I2C4, "I2C4" },
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{ PIRQ_I2C5, "I2C5" },
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{ PIRQ_UART2, "UART2" },
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{ PIRQ_UART3, "UART3" },
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};
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const struct irq_idx_name *sb_get_apic_reg_association(size_t *size)
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|
|
@ -173,31 +185,6 @@ static void sb_enable_lpc(void)
|
|||
pm_io_write8(PM_LPC_GATING, byte);
|
||||
}
|
||||
|
||||
static void sb_lpc_decode(void)
|
||||
{
|
||||
u32 tmp = 0;
|
||||
|
||||
/* Enable I/O decode to LPC bus */
|
||||
tmp = DECODE_ENABLE_PARALLEL_PORT0 | DECODE_ENABLE_PARALLEL_PORT2
|
||||
| DECODE_ENABLE_PARALLEL_PORT4 | DECODE_ENABLE_SERIAL_PORT0
|
||||
| DECODE_ENABLE_SERIAL_PORT1 | DECODE_ENABLE_SERIAL_PORT2
|
||||
| DECODE_ENABLE_SERIAL_PORT3 | DECODE_ENABLE_SERIAL_PORT4
|
||||
| DECODE_ENABLE_SERIAL_PORT5 | DECODE_ENABLE_SERIAL_PORT6
|
||||
| DECODE_ENABLE_SERIAL_PORT7 | DECODE_ENABLE_AUDIO_PORT0
|
||||
| DECODE_ENABLE_AUDIO_PORT1 | DECODE_ENABLE_AUDIO_PORT2
|
||||
| DECODE_ENABLE_AUDIO_PORT3 | DECODE_ENABLE_MSS_PORT2
|
||||
| DECODE_ENABLE_MSS_PORT3 | DECODE_ENABLE_FDC_PORT0
|
||||
| DECODE_ENABLE_FDC_PORT1 | DECODE_ENABLE_GAME_PORT
|
||||
| DECODE_ENABLE_KBC_PORT | DECODE_ENABLE_ACPIUC_PORT
|
||||
| DECODE_ENABLE_ADLIB_PORT;
|
||||
|
||||
/* Decode SIOs at 2E/2F and 4E/4F */
|
||||
if (CONFIG(PICASSO_LEGACY_FREE))
|
||||
tmp |= DECODE_ALTERNATE_SIO_ENABLE | DECODE_SIO_ENABLE;
|
||||
|
||||
lpc_enable_decode(tmp);
|
||||
}
|
||||
|
||||
static void sb_enable_cf9_io(void)
|
||||
{
|
||||
uint32_t reg = pm_read32(PM_DECODE_EN);
|
||||
|
|
@ -262,72 +249,6 @@ void sb_read_mode(u32 mode)
|
|||
& ~SPI_READ_MODE_MASK) | mode);
|
||||
}
|
||||
|
||||
static void setup_spread_spectrum(int *reboot)
|
||||
{
|
||||
uint16_t rstcfg = pm_read16(PWR_RESET_CFG);
|
||||
|
||||
rstcfg &= ~TOGGLE_ALL_PWR_GOOD;
|
||||
pm_write16(PWR_RESET_CFG, rstcfg);
|
||||
|
||||
uint32_t cntl1 = misc_read32(MISC_CLK_CNTL1);
|
||||
|
||||
if (cntl1 & CG1PLL_FBDIV_TEST) {
|
||||
printk(BIOS_DEBUG, "Spread spectrum is ready\n");
|
||||
misc_write32(MISC_CGPLL_CONFIG1,
|
||||
misc_read32(MISC_CGPLL_CONFIG1) |
|
||||
CG1PLL_SPREAD_SPECTRUM_ENABLE);
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
printk(BIOS_DEBUG, "Setting up spread spectrum\n");
|
||||
|
||||
uint32_t cfg6 = misc_read32(MISC_CGPLL_CONFIG6);
|
||||
cfg6 &= ~CG1PLL_LF_MODE_MASK;
|
||||
cfg6 |= (0x0f8 << CG1PLL_LF_MODE_SHIFT) & CG1PLL_LF_MODE_MASK;
|
||||
misc_write32(MISC_CGPLL_CONFIG6, cfg6);
|
||||
|
||||
uint32_t cfg3 = misc_read32(MISC_CGPLL_CONFIG3);
|
||||
cfg3 &= ~CG1PLL_REFDIV_MASK;
|
||||
cfg3 |= (0x003 << CG1PLL_REFDIV_SHIFT) & CG1PLL_REFDIV_MASK;
|
||||
cfg3 &= ~CG1PLL_FBDIV_MASK;
|
||||
cfg3 |= (0x04b << CG1PLL_FBDIV_SHIFT) & CG1PLL_FBDIV_MASK;
|
||||
misc_write32(MISC_CGPLL_CONFIG3, cfg3);
|
||||
|
||||
uint32_t cfg5 = misc_read32(MISC_CGPLL_CONFIG5);
|
||||
cfg5 &= ~SS_AMOUNT_NFRAC_SLIP_MASK;
|
||||
cfg5 |= (0x2 << SS_AMOUNT_NFRAC_SLIP_SHIFT) & SS_AMOUNT_NFRAC_SLIP_MASK;
|
||||
misc_write32(MISC_CGPLL_CONFIG5, cfg5);
|
||||
|
||||
uint32_t cfg4 = misc_read32(MISC_CGPLL_CONFIG4);
|
||||
cfg4 &= ~SS_AMOUNT_DSFRAC_MASK;
|
||||
cfg4 |= (0xd000 << SS_AMOUNT_DSFRAC_SHIFT) & SS_AMOUNT_DSFRAC_MASK;
|
||||
cfg4 &= ~SS_STEP_SIZE_DSFRAC_MASK;
|
||||
cfg4 |= (0x02d5 << SS_STEP_SIZE_DSFRAC_SHIFT)
|
||||
& SS_STEP_SIZE_DSFRAC_MASK;
|
||||
misc_write32(MISC_CGPLL_CONFIG4, cfg4);
|
||||
|
||||
rstcfg |= TOGGLE_ALL_PWR_GOOD;
|
||||
pm_write16(PWR_RESET_CFG, rstcfg);
|
||||
|
||||
cntl1 |= CG1PLL_FBDIV_TEST;
|
||||
misc_write32(MISC_CLK_CNTL1, cntl1);
|
||||
|
||||
*reboot = 1;
|
||||
}
|
||||
|
||||
static void setup_misc(int *reboot)
|
||||
{
|
||||
/* Undocumented register */
|
||||
uint32_t reg = misc_read32(0x50);
|
||||
if (!(reg & BIT(16))) {
|
||||
reg |= BIT(16);
|
||||
|
||||
misc_write32(0x50, reg);
|
||||
*reboot = 1;
|
||||
}
|
||||
}
|
||||
|
||||
static void fch_smbus_init(void)
|
||||
{
|
||||
pm_write8(SMB_ASF_IO_BASE, SMB_BASE_ADDR >> 8);
|
||||
|
|
@ -340,28 +261,27 @@ static void fch_smbus_init(void)
|
|||
}
|
||||
|
||||
/* Before console init */
|
||||
void bootblock_fch_early_init(void)
|
||||
void fch_pre_init(void)
|
||||
{
|
||||
int reboot = 0;
|
||||
|
||||
lpc_enable_rom();
|
||||
/* Turn on LPC in case the PSP didn't use it. However, ensure all
|
||||
* decoding is cleared as the PSP may have enabled decode paths. */
|
||||
sb_enable_lpc();
|
||||
lpc_enable_port80();
|
||||
sb_lpc_decode();
|
||||
lpc_disable_decodes();
|
||||
|
||||
if (CONFIG(POST_IO) && (CONFIG_POST_IO_PORT == 0x80)
|
||||
&& CONFIG(PICASSO_LPC_IOMUX))
|
||||
lpc_enable_port80();
|
||||
lpc_enable_spi_prefetch();
|
||||
sb_init_spi_base();
|
||||
sb_disable_4dw_burst(); /* Must be disabled on CZ(ST) */
|
||||
sb_disable_4dw_burst();
|
||||
sb_set_spi100(SPI_SPEED_33M, SPI_SPEED_33M,
|
||||
SPI_SPEED_16M, SPI_SPEED_16M);
|
||||
enable_acpimmio_decode();
|
||||
fch_smbus_init();
|
||||
sb_enable_cf9_io();
|
||||
setup_spread_spectrum(&reboot);
|
||||
setup_misc(&reboot);
|
||||
|
||||
if (reboot)
|
||||
warm_reset();
|
||||
|
||||
sb_enable_legacy_io();
|
||||
enable_aoac_devices();
|
||||
sb_reset_i2c_slaves();
|
||||
}
|
||||
|
||||
static void print_num_status_bits(int num_bits, uint32_t status,
|
||||
|
|
@ -417,9 +337,10 @@ static void sb_print_pmxc0_status(void)
|
|||
}
|
||||
|
||||
/* After console init */
|
||||
void bootblock_fch_init(void)
|
||||
void fch_early_init(void)
|
||||
{
|
||||
sb_print_pmxc0_status();
|
||||
i2c_soc_early_init();
|
||||
}
|
||||
|
||||
void sb_enable(struct device *dev)
|
||||
|
|
@ -430,6 +351,7 @@ void sb_enable(struct device *dev)
|
|||
static void sb_init_acpi_ports(void)
|
||||
{
|
||||
u32 reg;
|
||||
msr_t cst_addr;
|
||||
|
||||
/* We use some of these ports in SMM regardless of whether or not
|
||||
* ACPI tables are generated. Enable these ports indiscriminately.
|
||||
|
|
@ -439,8 +361,11 @@ static void sb_init_acpi_ports(void)
|
|||
pm_write16(PM1_CNT_BLK, ACPI_PM1_CNT_BLK);
|
||||
pm_write16(PM_TMR_BLK, ACPI_PM_TMR_BLK);
|
||||
pm_write16(PM_GPE0_BLK, ACPI_GPE0_BLK);
|
||||
|
||||
/* CpuControl is in \_PR.CP00, 6 bytes */
|
||||
pm_write16(PM_CPU_CTRL, ACPI_CPU_CONTROL);
|
||||
cst_addr.hi = 0;
|
||||
cst_addr.lo = ACPI_CPU_CONTROL;
|
||||
wrmsr(CSTATE_BASE_REG, cst_addr);
|
||||
|
||||
if (CONFIG(HAVE_SMI_HANDLER)) {
|
||||
/* APMC - SMI Command Port */
|
||||
|
|
@ -453,7 +378,6 @@ static void sb_init_acpi_ports(void)
|
|||
*/
|
||||
reg = pm_read32(PM_PCI_CTRL);
|
||||
reg |= FORCE_SLPSTATE_RETRY;
|
||||
reg &= ~FORCE_STPCLK_RETRY;
|
||||
pm_write32(PM_PCI_CTRL, reg);
|
||||
|
||||
/* Disable SlpTyp feature */
|
||||
|
|
|
|||
Loading…
Reference in New Issue