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haswell: Automatically check if Intel GbE is to be enabled 

If the Intel in-PCH GbE MAC is enabled in the devicetree, then tell MRC
to enable it as well. No one can ever forget to set this option anymore!

Change-Id: I946af36d16c94bb1a0f146604d0329fe6d6ce7e2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43128
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Angel Pons 2020-07-04 01:07:24 +02:00
parent d37b7d89fd
commit 39a6093d79
3 changed files with 4 additions and 2 deletions
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1
src/mainboard/asrock/b85m_pro4/romstage.c
View File

@ -28,7 +28,6 @@ void mb_get_spd_map(uint8_t spd_map[4])
void mainboard_fill_pei_data(struct pei_data *pei_data)
{
pei_data->ec_present = 0;
pei_data->gbe_enable = 1;
struct usb2_port_setting usb2_ports[MAX_USB2_PORTS] = {
/* Length, Enable, OCn#, Location */

1
src/mainboard/lenovo/t440p/romstage.c
View File

@ -49,7 +49,6 @@ void mb_get_spd_map(uint8_t spd_map[4])
void mainboard_fill_pei_data(struct pei_data *pei_data)
{
pei_data->ec_present = 1;
pei_data->gbe_enable = 1;
struct usb2_port_setting usb2_ports[MAX_USB2_PORTS] = {
/* Length, Enable, OCn#, Location */

4
src/northbridge/intel/haswell/romstage.c
View File

@ -3,6 +3,7 @@
#include <arch/romstage.h>
#include <console/console.h>
#include <cf9_reset.h>
#include <device/device.h>
#include <timestamp.h>
#include <cpu/x86/lapic.h>
#include <cbmem.h>
@ -37,6 +38,8 @@ static int make_channel_disabled_mask(const struct pei_data *pd, int ch)
/* The romstage entry point for this platform is not mainboard-specific, hence the name */
void mainboard_romstage_entry(void)
{
const struct device *gbe = pcidev_on_root(0x19, 0);
int wake_from_s3;
struct pei_data pei_data = {
@ -53,6 +56,7 @@ void mainboard_romstage_entry(void)
.temp_mmio_base = 0xfed08000,
.system_type = get_pch_platform_type(),
.tseg_size = CONFIG_SMM_TSEG_SIZE,
.gbe_enable = gbe && gbe->enabled,
.ddr_refresh_2x = CONFIG(ENABLE_DDR_2X_REFRESH),
.max_ddr3_freq = 1600,
};