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mb/google/nissa/var/quandiso: Disable un-used C1 port by daughterboard 

Probe usb ports by FW_CONFIG setting to disable C1 port on quandiso new daughterboard without C1 port.

BUG=b:312094048
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot

Change-Id: I6f702f60c772176e80b3452bf957d10625564102
Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79173
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Robert Chen 2023-11-20 01:39:00 -05:00 committed by Felix Held
parent e94d7d8264
commit 39b19f270c
1 changed files with 15 additions and 3 deletions
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18
src/mainboard/google/brya/variants/quandiso/overridetree.cb
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@ -442,7 +442,11 @@ chip soc/intel/alderlake
chip drivers/intel/pmc_mux/conn
use usb2_port2 as usb2_port
use tcss_usb3_port2 as usb3_port
device generic 1 alias conn1 on end
device generic 1 alias conn1 on
probe DB_USB DB_1C_1A
probe DB_USB DB_1C
probe DB_USB DB_1C_LTE
end
end
end
end
@ -462,7 +466,11 @@ chip soc/intel/alderlake
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
register "use_custom_pld" = "true"
register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))"
device ref tcss_usb3_port2 on end
device ref tcss_usb3_port2 on
probe DB_USB DB_1C_1A
probe DB_USB DB_1C
probe DB_USB DB_1C_LTE
end
end
end
end
@ -482,7 +490,11 @@ chip soc/intel/alderlake
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
register "use_custom_pld" = "true"
register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))"
device ref usb2_port2 on end
device ref usb2_port2 on
probe DB_USB DB_1C_1A
probe DB_USB DB_1C
probe DB_USB DB_1C_LTE
end
end
chip drivers/usb/acpi
register "desc" = ""USB2 Type-A Port A0 (MLB)""