mb/google/nissa/var/quandiso: Disable un-used C1 port by daughterboard
Probe usb ports by FW_CONFIG setting to disable C1 port on quandiso new daughterboard without C1 port. BUG=b:312094048 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot Change-Id: I6f702f60c772176e80b3452bf957d10625564102 Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79173 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -442,7 +442,11 @@ chip soc/intel/alderlake
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chip drivers/intel/pmc_mux/conn
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chip drivers/intel/pmc_mux/conn
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use usb2_port2 as usb2_port
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use usb2_port2 as usb2_port
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use tcss_usb3_port2 as usb3_port
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use tcss_usb3_port2 as usb3_port
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device generic 1 alias conn1 on end
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device generic 1 alias conn1 on
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probe DB_USB DB_1C_1A
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probe DB_USB DB_1C
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probe DB_USB DB_1C_LTE
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end
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end
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end
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end
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end
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end
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end
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@ -462,7 +466,11 @@ chip soc/intel/alderlake
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register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
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register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
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register "use_custom_pld" = "true"
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register "use_custom_pld" = "true"
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register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))"
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register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))"
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device ref tcss_usb3_port2 on end
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device ref tcss_usb3_port2 on
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probe DB_USB DB_1C_1A
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probe DB_USB DB_1C
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probe DB_USB DB_1C_LTE
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end
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end
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end
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end
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end
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end
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end
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@ -482,7 +490,11 @@ chip soc/intel/alderlake
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register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
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register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
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register "use_custom_pld" = "true"
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register "use_custom_pld" = "true"
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register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))"
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register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))"
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device ref usb2_port2 on end
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device ref usb2_port2 on
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probe DB_USB DB_1C_1A
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probe DB_USB DB_1C
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probe DB_USB DB_1C_LTE
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end
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end
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end
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chip drivers/usb/acpi
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chip drivers/usb/acpi
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register "desc" = ""USB2 Type-A Port A0 (MLB)""
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register "desc" = ""USB2 Type-A Port A0 (MLB)""
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