diff --git a/src/soc/intel/common/block/cpu/cpulib.c b/src/soc/intel/common/block/cpu/cpulib.c
index bfa4818450..3f0ee674f4 100644
--- a/src/soc/intel/common/block/cpu/cpulib.c
+++ b/src/soc/intel/common/block/cpu/cpulib.c
@@ -569,3 +569,12 @@ unsigned int smbios_cpu_get_max_speed_mhz(void)
 {
 	return cpu_get_max_turbo_ratio() * CONFIG_CPU_BCLK_MHZ;
 }
+
+void disable_three_strike_error(void)
+{
+	msr_t msr;
+
+	msr = rdmsr(MSR_PREFETCH_CTL);
+	msr.lo = msr.lo | DISABLE_CPU_ERROR;
+	wrmsr(MSR_PREFETCH_CTL, msr);
+}
diff --git a/src/soc/intel/common/block/include/intelblocks/cpulib.h b/src/soc/intel/common/block/include/intelblocks/cpulib.h
index c72e1eaed9..38c43d8c8f 100644
--- a/src/soc/intel/common/block/include/intelblocks/cpulib.h
+++ b/src/soc/intel/common/block/include/intelblocks/cpulib.h
@@ -222,4 +222,11 @@ bool is_sgx_supported(void);
  * Returns true if Key Locker feature is supported otherwise false.
  */
 bool is_keylocker_supported(void);
+
+/*
+ * This function prevents the Three Strike Counter from incrementing.
+ * It helps to collect more useful CPU traces for debugging.
+ */
+void disable_three_strike_error(void);
+
 #endif	/* SOC_INTEL_COMMON_BLOCK_CPULIB_H */
diff --git a/src/soc/intel/common/block/include/intelblocks/msr.h b/src/soc/intel/common/block/include/intelblocks/msr.h
index d4d8732418..9f95e9f7e6 100644
--- a/src/soc/intel/common/block/include/intelblocks/msr.h
+++ b/src/soc/intel/common/block/include/intelblocks/msr.h
@@ -35,6 +35,7 @@
 #define MSR_PREFETCH_CTL	0x1a4
 #define  PREFETCH_L1_DISABLE	(1 << 0)
 #define  PREFETCH_L2_DISABLE	(1 << 2)
+#define   DISABLE_CPU_ERROR		(1 << 11)
 #define MSR_MISC_PWR_MGMT	0x1aa
 #define  MISC_PWR_MGMT_EIST_HW_DIS	(1 << 0)
 #define  MISC_PWR_MGMT_ISST_EN		(1 << 6)