intel/common: use acpi_is_wakeup_s3() in fsp_ramstage.c
acpi_is_wakeup_s3() was introduced in upstream coreboot while the FSP support code was written. Move to using that instead of using the romstage_handoff structure directly. BUG=chrome-os-partner:43636 BRANCH=None TEST=Built, booted, suspended, and resumed on glados. Original-Change-Id: I71601a4be3c981672e25e189c98abb6a676462bf Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/290720 Original-Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: I2ae4d9906e0891080481fb58b941921922a989d3 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11190 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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@ -18,15 +18,16 @@
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* Foundation, Inc.
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*/
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#include <arch/acpi.h>
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#include <cbmem.h>
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#include <cbfs.h>
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#include <console/console.h>
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#include <fsp_util.h>
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#include <lib.h>
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#include <romstage_handoff.h>
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#include <soc/intel/common/memmap.h>
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#include <soc/intel/common/ramstage.h>
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#include <stage_cache.h>
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#include <string.h>
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#include <timestamp.h>
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/* SOC initialization after FSP silicon init */
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@ -176,7 +177,7 @@ static FSP_INFO_HEADER *soc_restore_support_code(void)
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return header->fih;
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}
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static void fsp_run_silicon_init(struct romstage_handoff *handoff)
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static void fsp_run_silicon_init(int is_s3_wakeup)
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{
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FSP_INFO_HEADER *fsp_info_header;
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FSP_SILICON_INIT fsp_silicon_init;
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@ -209,7 +210,7 @@ static void fsp_run_silicon_init(struct romstage_handoff *handoff)
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/* Locate VBT and pass to FSP GOP */
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if (IS_ENABLED(CONFIG_GOP_SUPPORT))
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load_vbt(handoff->s3_resume, &silicon_init_params);
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load_vbt(is_s3_wakeup, &silicon_init_params);
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mainboard_silicon_init_params(&silicon_init_params);
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/* Display the UPD data */
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@ -305,11 +306,9 @@ static int fsp_find_and_relocate(void)
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void intel_silicon_init(void)
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{
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struct romstage_handoff *handoff;
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int is_s3_wakeup = acpi_is_wakeup_s3();
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handoff = cbmem_find(CBMEM_ID_ROMSTAGE_INFO);
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if (handoff != NULL && handoff->s3_resume) {
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if (is_s3_wakeup) {
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printk(BIOS_DEBUG, "FSP: Loading binary from cache\n");
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fsp_update_fih(soc_restore_support_code());
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} else {
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@ -318,7 +317,7 @@ void intel_silicon_init(void)
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fsp_cache_save();
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}
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fsp_run_silicon_init(handoff);
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fsp_run_silicon_init(is_s3_wakeup);
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}
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/* Initialize the UPD parameters for SiliconInit */
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