mb/google/poppy/variants: Set pch_trip_temp to 75C

Similar to Soraka, this change sets the pch_trip_temp value to
75C. This is important so that PMC can shutdown the thermal sensor
when CPU is in C-state and DTS temp <= pch_trip_temp.

BUG=b:74089135

Change-Id: Ic46fa0681796b821dfb014ab91734c960df7846a
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/24968
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This commit is contained in:
Furquan Shaikh 2018-03-01 18:08:06 -08:00
parent fa9f107319
commit 39d3021b16
3 changed files with 9 additions and 0 deletions

View File

@ -264,6 +264,9 @@ chip soc/intel/skylake
# Lock Down # Lock Down
register "chipset_lockdown" = "CHIPSET_LOCKDOWN_COREBOOT" register "chipset_lockdown" = "CHIPSET_LOCKDOWN_COREBOOT"
# PCH Trip Temperature in degree C
register "pch_trip_temp" = "75"
device cpu_cluster 0 on device cpu_cluster 0 on
device lapic 0 on end device lapic 0 on end
end end

View File

@ -234,6 +234,9 @@ chip soc/intel/skylake
# Lock Down # Lock Down
register "chipset_lockdown" = "CHIPSET_LOCKDOWN_COREBOOT" register "chipset_lockdown" = "CHIPSET_LOCKDOWN_COREBOOT"
# PCH Trip Temperature in degree C
register "pch_trip_temp" = "75"
device cpu_cluster 0 on device cpu_cluster 0 on
device lapic 0 on end device lapic 0 on end
end end

View File

@ -282,6 +282,9 @@ chip soc/intel/skylake
# Lock Down # Lock Down
register "chipset_lockdown" = "CHIPSET_LOCKDOWN_COREBOOT" register "chipset_lockdown" = "CHIPSET_LOCKDOWN_COREBOOT"
# PCH Trip Temperature in degree C
register "pch_trip_temp" = "75"
device cpu_cluster 0 on device cpu_cluster 0 on
device lapic 0 on end device lapic 0 on end
end end