mb/google/poppy/variants: Set pch_trip_temp to 75C
Similar to Soraka, this change sets the pch_trip_temp value to 75C. This is important so that PMC can shutdown the thermal sensor when CPU is in C-state and DTS temp <= pch_trip_temp. BUG=b:74089135 Change-Id: Ic46fa0681796b821dfb014ab91734c960df7846a Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/24968 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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@ -264,6 +264,9 @@ chip soc/intel/skylake
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# Lock Down
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# Lock Down
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register "chipset_lockdown" = "CHIPSET_LOCKDOWN_COREBOOT"
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register "chipset_lockdown" = "CHIPSET_LOCKDOWN_COREBOOT"
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# PCH Trip Temperature in degree C
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register "pch_trip_temp" = "75"
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device cpu_cluster 0 on
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device cpu_cluster 0 on
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device lapic 0 on end
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device lapic 0 on end
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end
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end
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@ -234,6 +234,9 @@ chip soc/intel/skylake
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# Lock Down
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# Lock Down
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register "chipset_lockdown" = "CHIPSET_LOCKDOWN_COREBOOT"
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register "chipset_lockdown" = "CHIPSET_LOCKDOWN_COREBOOT"
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# PCH Trip Temperature in degree C
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register "pch_trip_temp" = "75"
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device cpu_cluster 0 on
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device cpu_cluster 0 on
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device lapic 0 on end
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device lapic 0 on end
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end
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end
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@ -282,6 +282,9 @@ chip soc/intel/skylake
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# Lock Down
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# Lock Down
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register "chipset_lockdown" = "CHIPSET_LOCKDOWN_COREBOOT"
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register "chipset_lockdown" = "CHIPSET_LOCKDOWN_COREBOOT"
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# PCH Trip Temperature in degree C
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register "pch_trip_temp" = "75"
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device cpu_cluster 0 on
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device cpu_cluster 0 on
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device lapic 0 on end
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device lapic 0 on end
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end
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end
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