Clean up some DCACHE related options.

In amd/serengeti_cheetah there were duplicates, and USE_DCACHE_RAM is a
boolean value, so make it so.


Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4596 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Patrick Georgi 2009-08-27 12:10:50 +00:00
parent 20c03fb923
commit 39ec29c47e
3 changed files with 6 additions and 30 deletions

View File

@ -5,6 +5,10 @@ source src/cpu/via/Kconfig
source src/cpu/x86/Kconfig
source src/cpu/ppc/Kconfig
config USE_DCACHE_RAM
bool
default n
config DCACHE_RAM_BASE
hex
default 0xffdf8000 if CPU_INTEL_CORE

View File

@ -14,6 +14,7 @@ config BOARD_AMD_SERENGETI_CHEETAH
select SUPERIO_WINBOND_W83627HF
select HAVE_PIRQ_TABLE
select USE_PRINTK_IN_CAR
select USE_DCACHE_RAM
help
AMD Serengeti Cheetah mainboard.
endchoice
@ -23,11 +24,6 @@ config MAINBOARD_DIR
default amd/serengeti_cheetah
depends on BOARD_AMD_SERENGETI_CHEETAH
config USE_DCACHE_RAM
int
default 1
depends on BOARD_AMD_SERENGETI_CHEETAH
config DCACHE_RAM_BASE
hex
default 0xc8000
@ -83,26 +79,6 @@ config PCI_64BIT_PREF_MEM
default 0
depends on BOARD_AMD_SERENGETI_CHEETAH
config USE_DCACHE_RAM
int
default 1
depends on BOARD_AMD_SERENGETI_CHEETAH
config DCACHE_RAM_BASE
hex
default 0xc8000
depends on BOARD_AMD_SERENGETI_CHEETAH
config DCACHE_RAM_SIZE
hex
default 0x08000
depends on BOARD_AMD_SERENGETI_CHEETAH
config DCACHE_RAM_GLOBAL_VAR_SIZE
hex
default 0x01000
depends on BOARD_AMD_SERENGETI_CHEETAH
config USE_FAILOVER_IMAGE
int
default 0

View File

@ -29,6 +29,7 @@ config BOARD_ASUS_M2V_MX_SE
select SOUTHBRIDGE_VIA_K8T890
select SUPERIO_ITE_IT8712F
select USE_PRINTK_IN_CAR
select USE_DCACHE_RAM
help
Asus M2V-MX-SE mainboard.
@ -37,11 +38,6 @@ config MAINBOARD_DIR
default asus/m2v-mx_se
depends on BOARD_ASUS_M2V_MX_SE
config USE_DCACHE_RAM
bool
dafault y
depends on BOARD_ASUS_M2V_MX_SE
config DCACHE_RAM_BASE
hex
default 0xcc000