Clean up some DCACHE related options.
In amd/serengeti_cheetah there were duplicates, and USE_DCACHE_RAM is a boolean value, so make it so. Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4596 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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@ -5,6 +5,10 @@ source src/cpu/via/Kconfig
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source src/cpu/x86/Kconfig
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source src/cpu/ppc/Kconfig
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config USE_DCACHE_RAM
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bool
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default n
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config DCACHE_RAM_BASE
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hex
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default 0xffdf8000 if CPU_INTEL_CORE
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@ -14,6 +14,7 @@ config BOARD_AMD_SERENGETI_CHEETAH
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select SUPERIO_WINBOND_W83627HF
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select HAVE_PIRQ_TABLE
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select USE_PRINTK_IN_CAR
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select USE_DCACHE_RAM
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help
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AMD Serengeti Cheetah mainboard.
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endchoice
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@ -23,11 +24,6 @@ config MAINBOARD_DIR
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default amd/serengeti_cheetah
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depends on BOARD_AMD_SERENGETI_CHEETAH
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config USE_DCACHE_RAM
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int
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default 1
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depends on BOARD_AMD_SERENGETI_CHEETAH
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config DCACHE_RAM_BASE
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hex
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default 0xc8000
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@ -83,26 +79,6 @@ config PCI_64BIT_PREF_MEM
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default 0
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depends on BOARD_AMD_SERENGETI_CHEETAH
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config USE_DCACHE_RAM
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int
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default 1
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depends on BOARD_AMD_SERENGETI_CHEETAH
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config DCACHE_RAM_BASE
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hex
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default 0xc8000
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depends on BOARD_AMD_SERENGETI_CHEETAH
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config DCACHE_RAM_SIZE
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hex
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default 0x08000
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depends on BOARD_AMD_SERENGETI_CHEETAH
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config DCACHE_RAM_GLOBAL_VAR_SIZE
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hex
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default 0x01000
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depends on BOARD_AMD_SERENGETI_CHEETAH
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config USE_FAILOVER_IMAGE
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int
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default 0
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@ -29,6 +29,7 @@ config BOARD_ASUS_M2V_MX_SE
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select SOUTHBRIDGE_VIA_K8T890
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select SUPERIO_ITE_IT8712F
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select USE_PRINTK_IN_CAR
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select USE_DCACHE_RAM
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help
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Asus M2V-MX-SE mainboard.
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@ -37,11 +38,6 @@ config MAINBOARD_DIR
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default asus/m2v-mx_se
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depends on BOARD_ASUS_M2V_MX_SE
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config USE_DCACHE_RAM
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bool
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dafault y
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depends on BOARD_ASUS_M2V_MX_SE
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config DCACHE_RAM_BASE
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hex
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default 0xcc000
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