mb/google/guybrush: disable KBRSTEN
GPIO129 is muxed with KBRST, so setting GPIO129 to low causes reset when KBRSTEN is set to 1. Since reset value of KBRSTEN is 1 we need a logic to clear it. BUG=b:183340503 TEST=build Signed-off-by: Kangheui Won <khwon@chromium.org> Change-Id: I194e8432a14d6105f6bcf12111647f5aad4e2de2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51727 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
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@ -1,9 +1,11 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#include <amdblocks/acpimmio.h>
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#include <amdblocks/amd_pci_util.h>
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#include <baseboard/variants.h>
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#include <device/device.h>
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#include <soc/acpi.h>
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#include <soc/southbridge.h>
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#include <variant/ec.h>
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#include <vendorcode/google/chromeos/chromeos.h>
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@ -88,6 +90,16 @@ static void mainboard_configure_gpios(void)
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{
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size_t base_num_gpios, override_num_gpios;
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const struct soc_amd_gpio *base_gpios, *override_gpios;
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u32 reg;
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/*
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* Disable KBRST feature
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* KBRSTEN is set to 1 on reset and this causes system reset
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* if GPIO 129 is configured as GPO_LOW.
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* */
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reg = pm_read8(PM_RST_CTRL1);
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reg &= ~KBRSTEN;
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pm_write8(PM_RST_CTRL1, reg);
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base_gpios = variant_base_gpio_table(&base_num_gpios);
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override_gpios = variant_override_gpio_table(&override_num_gpios);
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@ -54,6 +54,7 @@
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#define PM_ACPI_RTC_WAKE_EN BIT(29)
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#define PM_RST_CTRL1 0xbe
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#define SLPTYPE_CONTROL_EN BIT(5)
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#define KBRSTEN BIT(4)
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#define PM_LPC_GATING 0xec
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#define PM_LPC_AB_NO_BYPASS_EN BIT(2)
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#define PM_LPC_A20_EN BIT(1)
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