intel/strago: Clean up DDR configuration.
This change includes following changes: - Clean up the DDR configuration and flow. - Removing support for non LPDDR3 boards. - Supporting only LPDDR3 and PMIC config. TEST=Build/flash CB and boot the platform to OS. Change-Id: I8369443da728a4c07e0c1a82040d94034c3542da Signed-off-by: Divagar Mohandass <divagar.mohandass@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/297941 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Jenny Tc <jenny.tc@intel.com> Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/13122 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Divagar Mohandass
Martin Roth
parent
4f4c6e88be
commit
39f84fa662
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@ -21,12 +21,6 @@ config CHROMEOS
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select VBOOT_DYNAMIC_WORK_BUFFER
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select VIRTUAL_DEV_SWITCH
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config DISPLAY_SPD_DATA
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bool "Display Memory Serial Presence Detect Data"
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default n
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help
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When enabled displays the memory configuration data.
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config DYNAMIC_VNN_SUPPORT
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bool "Enables support for Dynamic VNN"
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default n
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@ -14,8 +14,6 @@
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## GNU General Public License for more details.
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##
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subdirs-y += spd
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romstage-y += boardid.c
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romstage-$(CONFIG_MAINBOARD_HAS_CHROMEOS) += chromeos.c
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romstage-$(CONFIG_ENABLE_BUILTIN_COM1) += com_init.c
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@ -25,32 +25,8 @@
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#include "onboard.h"
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#include <boardid.h>
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/* All FSP specific code goes in this block */
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void mainboard_romstage_entry(struct romstage_params *rp)
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{
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struct pei_data *ps = rp->pei_data;
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mainboard_fill_spd_data(ps);
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/* Call back into chipset code with platform values updated. */
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romstage_common(rp);
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}
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void mainboard_memory_init_params(struct romstage_params *params,
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MEMORY_INIT_UPD *memory_params)
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{
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int id;
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id = board_id();
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if (id == BOARD_BCRD2) {
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memory_params->PcdMemoryTypeEnable = MEM_LPDDR3;
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memory_params->PcdDvfsEnable = 0;
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} else {
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memory_params->PcdMemoryTypeEnable = MEM_DDR3;
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memory_params->PcdMemorySpdPtr =
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(u32)params->pei_data->spd_data_ch0;
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memory_params->PcdMemChannel0Config =
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params->pei_data->spd_ch0_config;
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memory_params->PcdMemChannel1Config =
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params->pei_data->spd_ch1_config;
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}
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memory_params->PcdMemoryTypeEnable = MEM_LPDDR3;
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}
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@ -1,38 +0,0 @@
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2013 Google Inc.
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## Copyright (C) 2015 Intel Corp.
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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romstage-y += spd.c
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SPD_BIN = $(obj)/spd.bin
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SPD_SOURCES = samsung_2GiB_dimm_K4B4G1646Q-HYK0
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SPD_SOURCES += hynix_2GiB_dimm_HMT425S6CFR6A_H5TC4G63CFR
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SPD_SOURCES += samsung_2GiB_dimm_K4B4G1646Q-HYK0
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SPD_SOURCES += hynix_2GiB_dimm_HMT425S6CFR6A_H5TC4G63CFR
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SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex)
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# Include spd rom data
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$(SPD_BIN): $(SPD_DEPS)
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for f in $+; \
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do for c in $$(cat $$f | grep -v ^#); \
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do printf $$(printf '\%o' 0x$$c); \
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done; \
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done > $@
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cbfs-files-y += spd.bin
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spd.bin-file := $(SPD_BIN)
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spd.bin-type := spd
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@ -1,32 +0,0 @@
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92 12 0b 03 04 19 02 02
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03 52 01 08 0a 00 fe 00
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69 78 69 3c 69 11 18 81
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20 08 3c 3c 01 40 83 01
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 0f 11 62 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 80 ad 01
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00 00 00 00 00 00 ff ab
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48 4d 54 34 32 35 53 36
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41 46 52 36 41 2d 50 42
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20 20 4e 30 80 ad 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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ff ff ff ff ff ff ff ff
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ff ff ff ff ff ff ff ff
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ff ff ff ff ff ff ff ff
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ff ff ff ff ff ff ff ff
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ff ff ff ff ff ff ff ff
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ff ff ff ff ff ff ff ff
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ff ff ff ff ff ff ff ff
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ff ff ff ff ff ff ff ff
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ff ff ff ff ff ff ff ff
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ff ff ff ff ff ff ff ff
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@ -1,32 +0,0 @@
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92 13 0B 03 04 19 02 02
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03 52 01 08 0A 00 FE 00
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69 78 69 3C 69 11 18 81
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20 08 3C 3C 01 40 83 01
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00 00 00 00 00 00 00 00
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00 88 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 0F 11 62 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 80 AD 01
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00 00 00 00 00 00 C9 C0
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48 4D 54 34 32 35 53 36
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43 46 52 36 41 2D 50 42
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20 20 4E 30 80 AD 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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FF FF FF FF FF FF FF FF
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FF FF FF FF FF FF FF FF
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FF FF FF FF FF FF FF FF
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FF FF FF FF FF FF FF FF
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FF FF FF FF FF FF FF FF
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FF FF FF FF FF FF FF FF
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FF FF FF FF FF FF FF FF
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FF FF FF FF FF FF FF FF
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FF FF FF FF FF FF FF FF
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FF FF FF FF FF FF FF FF
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@ -1,32 +0,0 @@
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92 12 0B 03 04 19 02 02
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03 11 01 08 0A 00 FE 00
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69 78 69 3C 69 11 18 81
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20 08 3C 3C 01 40 83 05
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00 00 00 00 00 00 00 00
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88 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 0F 01 02 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 80 CE 01
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00 00 00 00 00 00 6C F9
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4D 34 37 31 42 35 36 37
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34 51 48 30 2D 59 4B 30
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20 20 00 00 80 CE 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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@ -1,116 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2013 Google Inc.
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* Copyright (C) 2015 Intel Corp.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <cbfs.h>
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#include <console/console.h>
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#include <lib.h>
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#include <soc/gpio.h>
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#include <soc/romstage.h>
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#include <string.h>
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#define SPD_SIZE 256
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#define SATA_GP3_PAD_CFG0 0x5828
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#define I2C3_SCL_PAD_CFG0 0x5438
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#define MF_PLT_CLK1_PAD_CFG0 0x4410
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#define I2C3_SDA_PAD_CFG0 0x5420
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/*
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* 0b0000 - 4GiB total - 2 x 2GiB Samsung K4B4G1646Q-HYK0 1600MHz
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* 0b0001 - 4GiB total - 2 x 2GiB Hynix H5TC4G63CFR-PBA 1600MHz
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* 0b0010- 2GiB total - 1 x 2GiB Samsung K4B4G1646Q-HYK0 1600MHz
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* 0b0011 - 2GiB total - 1 x 2GiB Hynix H5TC4G63CFR-PBA 1600MHz
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*/
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static const uint32_t dual_channel_config = (1 << 0);
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static void *get_spd_pointer(char *spd_file_content, int total_spds, int *dual)
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{
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int ram_id = 0;
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ram_id |= get_gpio(COMMUNITY_GPSOUTHWEST_BASE, SATA_GP3_PAD_CFG0) << 0;
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ram_id |= get_gpio(COMMUNITY_GPSOUTHWEST_BASE, I2C3_SCL_PAD_CFG0) << 1;
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ram_id |= get_gpio(COMMUNITY_GPSOUTHEAST_BASE, MF_PLT_CLK1_PAD_CFG0)
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<< 2;
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ram_id |= get_gpio(COMMUNITY_GPSOUTHWEST_BASE, I2C3_SDA_PAD_CFG0) << 3;
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/*
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* There are only 2 SPDs supported on Cyan Board:
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* Samsung 4G:0000 & Hynix 2G:0011
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*/
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/*
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* RAMID0 on the first boot does not read the correct value,so checking
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* bit 1 is enough as WA
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*/
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if (ram_id > 0)
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ram_id = 3;
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printk(BIOS_DEBUG, "ram_id=%d, total_spds: %d\n", ram_id, total_spds);
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if (ram_id >= total_spds)
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return NULL;
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/* Single channel configs */
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if (dual_channel_config & (1 << ram_id))
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*dual = 1;
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return &spd_file_content[SPD_SIZE * ram_id];
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}
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/* Copy SPD data for on-board memory */
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void mainboard_fill_spd_data(struct pei_data *ps)
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{
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char *spd_file;
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size_t spd_file_len;
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void *spd_content;
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int dual_channel = 0;
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/* Find the SPD data in CBFS. */
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spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD,
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&spd_file_len);
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if (!spd_file)
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die("SPD data not found.");
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if (spd_file_len < SPD_SIZE)
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die("Missing SPD data.");
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/*
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* Both channels are always present in SPD data. Always use matched
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* DIMMs so use the same SPD data for each DIMM.
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*/
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spd_content = get_spd_pointer(spd_file,
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spd_file_len / SPD_SIZE,
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&dual_channel);
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if (IS_ENABLED(CONFIG_DISPLAY_SPD_DATA) && spd_content != NULL) {
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printk(BIOS_DEBUG, "SPD Data:\n");
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hexdump(spd_content, SPD_SIZE);
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printk(BIOS_DEBUG, "\n");
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}
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/*
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* Set SPD and memory configuration:
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* Memory type: 0=DimmInstalled,
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* 1=SolderDownMemory,
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* 2=DimmDisabled
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*/
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if (spd_content != NULL) {
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ps->spd_data_ch0 = spd_content;
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ps->spd_ch0_config = 1;
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if (dual_channel) {
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ps->spd_data_ch1 = spd_content;
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ps->spd_ch1_config = 1;
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} else {
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ps->spd_ch1_config = 2;
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}
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}
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}
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