mediatek: Share GPIO external interrupts (EINT) code among similar SoCs

Refactor GPIO EINT code which can be reused among similar SoCs.

BUG=b:80501386
BRANCH=none
TEST=emerge-elm coreboot; emerge-kukui coreboot

Change-Id: Ib01b43cf1aa4082d7d968fe1ef82f75e8cf05b8b
Signed-off-by: Chuanjia Liu <Chuanjia.Liu@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/29837
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>

src/soc/mediatek/common/gpio.c

@@ -126,3 +126,64 @@ void gpio_output(gpio_t gpio, int value)
 	gpio_set_dir(gpio, GPIO_DIRECTION_OUT);
 	gpio_set_mode(gpio, GPIO_MODE);
 }
+
+enum {
+	MAX_EINT_REG_BITS = 32,
+};
+
+static void pos_bit_calc_for_eint(gpio_t gpio, u32 *pos, u32 *bit)
+{
+	*pos = gpio.id / MAX_EINT_REG_BITS;
+	*bit = gpio.id % MAX_EINT_REG_BITS;
+}
+
+int gpio_eint_poll(gpio_t gpio)
+{
+	u32 pos;
+	u32 bit;
+	u32 status;
+
+	pos_bit_calc_for_eint(gpio, &pos, &bit);
+
+	status = (read32(&mtk_eint->sta.regs[pos]) >> bit) & 0x1;
+
+	if (status)
+		write32(&mtk_eint->ack.regs[pos], 1 << bit);
+
+	return status;
+}
+
+void gpio_eint_configure(gpio_t gpio, enum gpio_irq_type type)
+{
+	u32 pos;
+	u32 bit, mask;
+
+	pos_bit_calc_for_eint(gpio, &pos, &bit);
+	mask = 1 << bit;
+
+	/* Make it an input first. */
+	gpio_input_pullup(gpio);
+
+	write32(&mtk_eint->d0en[pos], mask);
+
+	switch (type) {
+	case IRQ_TYPE_EDGE_FALLING:
+		write32(&mtk_eint->sens_clr.regs[pos], mask);
+		write32(&mtk_eint->pol_clr.regs[pos], mask);
+		break;
+	case IRQ_TYPE_EDGE_RISING:
+		write32(&mtk_eint->sens_clr.regs[pos], mask);
+		write32(&mtk_eint->pol_set.regs[pos], mask);
+		break;
+	case IRQ_TYPE_LEVEL_LOW:
+		write32(&mtk_eint->sens_set.regs[pos], mask);
+		write32(&mtk_eint->pol_clr.regs[pos], mask);
+		break;
+	case IRQ_TYPE_LEVEL_HIGH:
+		write32(&mtk_eint->sens_set.regs[pos], mask);
+		write32(&mtk_eint->pol_set.regs[pos], mask);
+		break;
+	}
+
+	write32(&mtk_eint->mask_clr.regs[pos], mask);
+}

src/soc/mediatek/common/include/soc/gpio_common.h

@@ -16,6 +16,10 @@
 #ifndef SOC_MEDIATEK_COMMON_GPIO_H
 #define SOC_MEDIATEK_COMMON_GPIO_H
 
+#include <soc/gpio_base.h>
+#include <stddef.h>
+#include <stdint.h>
+
 enum pull_enable {
 	GPIO_PULL_DISABLE = 0,
 	GPIO_PULL_ENABLE = 1,
@@ -26,4 +30,59 @@ enum pull_select {
 	GPIO_PULL_UP = 1,
 };
 
+void gpio_set_pull(gpio_t gpio, enum pull_enable enable,
+		   enum pull_select select);
+void gpio_set_mode(gpio_t gpio, int mode);
+
+enum gpio_irq_type {
+	IRQ_TYPE_EDGE_RISING,
+	IRQ_TYPE_EDGE_FALLING,
+	IRQ_TYPE_LEVEL_HIGH,
+	IRQ_TYPE_LEVEL_LOW,
+};
+
+struct eint_section {
+	uint32_t	regs[7];
+	uint32_t	align1[9];
+};
+
+struct eint_regs {
+	struct eint_section sta;
+	struct eint_section ack;
+	struct eint_section mask;
+	struct eint_section mask_set;
+	struct eint_section mask_clr;
+	struct eint_section sens;
+	struct eint_section sens_set;
+	struct eint_section sens_clr;
+	struct eint_section soft;
+	struct eint_section soft_set;
+	struct eint_section soft_clr;
+	struct eint_section rsv00;
+	struct eint_section pol;
+	struct eint_section pol_set;
+	struct eint_section pol_clr;
+	struct eint_section rsv01;
+	uint32_t	    d0en[7];
+	uint32_t	    rsv02;
+	uint32_t	    d1en[7];
+};
+
+check_member(eint_regs, d1en, 0x420);
+
+static struct eint_regs *const mtk_eint = (void *)(EINT_BASE);
+
+/*
+ * Firmware never enables interrupts on this platform.  This function
+ * reads current EINT status and clears the pending interrupt.
+ *
+ * Returns 1 if the interrupt was pending, else 0.
+ */
+int gpio_eint_poll(gpio_t gpio);
+
+/*
+ * Configure a GPIO to handle external interrupts (EINT) of given irq type.
+ */
+void gpio_eint_configure(gpio_t gpio, enum gpio_irq_type type);
+
 #endif

src/soc/mediatek/mt8173/gpio.c

@@ -19,7 +19,6 @@
 
 enum {
 	MAX_GPIO_NUMBER = 134,
-	MAX_EINT_REG_BITS = 32,
 };
 
 static void pos_bit_calc(gpio_t gpio, u32 *pos, u32 *bit)
@@ -28,12 +27,6 @@ static void pos_bit_calc(gpio_t gpio, u32 *pos, u32 *bit)
 	*bit = gpio.id % MAX_GPIO_REG_BITS;
 }
 
-static void pos_bit_calc_for_eint(gpio_t gpio, u32 *pos, u32 *bit)
-{
-	*pos = gpio.id / MAX_EINT_REG_BITS;
-	*bit = gpio.id % MAX_EINT_REG_BITS;
-}
-
 void gpio_set_pull(gpio_t gpio, enum pull_enable enable,
 		   enum pull_select select)
 {
@@ -63,54 +56,3 @@ void gpio_set_pull(gpio_t gpio, enum pull_enable enable,
 	}
 	write16(en_reg, 1L << bit);
 }
-
-int gpio_eint_poll(gpio_t gpio)
-{
-	u32 pos;
-	u32 bit;
-	u32 status;
-
-	pos_bit_calc_for_eint(gpio, &pos, &bit);
-
-	status = (read32(&mt8173_eint->sta.regs[pos]) >> bit) & 0x1;
-
-	if (status)
-		write32(&mt8173_eint->ack.regs[pos], 1 << bit);
-
-	return status;
-}
-
-void gpio_eint_configure(gpio_t gpio, enum gpio_irq_type type)
-{
-	u32 pos;
-	u32 bit, mask;
-
-	pos_bit_calc_for_eint(gpio, &pos, &bit);
-	mask = 1 << bit;
-
-	/* Make it an input first. */
-	gpio_input_pullup(gpio);
-
-	write32(&mt8173_eint->d0en[pos], mask);
-
-	switch (type) {
-	case IRQ_TYPE_EDGE_FALLING:
-		write32(&mt8173_eint->sens_clr.regs[pos], mask);
-		write32(&mt8173_eint->pol_clr.regs[pos], mask);
-		break;
-	case IRQ_TYPE_EDGE_RISING:
-		write32(&mt8173_eint->sens_clr.regs[pos], mask);
-		write32(&mt8173_eint->pol_set.regs[pos], mask);
-		break;
-	case IRQ_TYPE_LEVEL_LOW:
-		write32(&mt8173_eint->sens_set.regs[pos], mask);
-		write32(&mt8173_eint->pol_clr.regs[pos], mask);
-		break;
-	case IRQ_TYPE_LEVEL_HIGH:
-		write32(&mt8173_eint->sens_set.regs[pos], mask);
-		write32(&mt8173_eint->pol_set.regs[pos], mask);
-		break;
-	}
-
-	write32(&mt8173_eint->mask_clr.regs[pos], mask);
-}

src/soc/mediatek/mt8173/include/soc/gpio.h

@@ -31,10 +31,6 @@ enum external_power {
 	GPIO_EINT_1P8V = 1,
 };
 
-typedef struct {
-	u32 id;
-} gpio_t;
-
 #define PIN(id, name, func1, func2, func3, func4, func5, func6, func7) \
 	PAD_##name##_ID = id, \
 	PAD_##name##_FUNC_##func1 = 1, \
@@ -364,60 +360,6 @@ check_member(gpio_regs, hsic_ctrl[3], 0xe50);
 
 static struct gpio_regs *const mtk_gpio = (void *)(GPIO_BASE);
 
-void gpio_set_pull(gpio_t gpio, enum pull_enable enable,
-		   enum pull_select select);
-void gpio_set_mode(gpio_t gpio, int mode);
 void gpio_init(enum external_power);
 
-enum gpio_irq_type {
-	IRQ_TYPE_EDGE_RISING,
-	IRQ_TYPE_EDGE_FALLING,
-	IRQ_TYPE_LEVEL_HIGH,
-	IRQ_TYPE_LEVEL_LOW,
-};
-
-struct eint_section {
-	uint32_t	regs[7];
-	uint32_t	align1[9];
-};
-
-struct eint_regs {
-	struct eint_section sta;
-	struct eint_section ack;
-	struct eint_section mask;
-	struct eint_section mask_set;
-	struct eint_section mask_clr;
-	struct eint_section sens;
-	struct eint_section sens_set;
-	struct eint_section sens_clr;
-	struct eint_section soft;
-	struct eint_section soft_set;
-	struct eint_section soft_clr;
-	struct eint_section rsv00;
-	struct eint_section pol;
-	struct eint_section pol_set;
-	struct eint_section pol_clr;
-	struct eint_section rsv01;
-	uint32_t	    d0en[7];
-	uint32_t	    rsv02;
-	uint32_t	    d1en[7];
-};
-
-check_member(eint_regs, d1en, 0x420);
-
-static struct eint_regs *const mt8173_eint = (void *)(EINT_BASE);
-
-/*
- * Firmware never enables interrupts on this platform.  This function
- * reads current EINT status and clears the pending interrupt.
- *
- * Returns 1 if the interrupt was pending, else 0.
- */
-int gpio_eint_poll(gpio_t gpio);
-
-/*
- * Configure a GPIO to handle external interrupts (EINT) of given irq type.
- */
-void gpio_eint_configure(gpio_t gpio, enum gpio_irq_type type);
-
 #endif /* SOC_MEDIATEK_MT8173_GPIO_H */

src/soc/mediatek/mt8173/include/soc/gpio_base.h

@@ -0,0 +1,24 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 MediaTek Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#ifndef SOC_MEDIATEK_MT8173_GPIO_BASE_H
+#define SOC_MEDIATEK_MT8173_GPIO_BASE_H
+
+#include <stdint.h>
+
+typedef struct {
+	u32 id;
+} gpio_t;
+
+#endif

src/soc/mediatek/mt8183/include/soc/addressmap.h

@@ -26,8 +26,9 @@ enum {
 	INFRACFG_AO_BASE	= IO_PHYS + 0x00001000,
 	GPIO_BASE		= IO_PHYS + 0x00005000,
 	SPM_BASE		= IO_PHYS + 0x00006000,
-	RGU_BASE                = IO_PHYS + 0x00007000,
+	RGU_BASE		= IO_PHYS + 0x00007000,
 	GPT_BASE		= IO_PHYS + 0x00008000,
+	EINT_BASE		= IO_PHYS + 0x0000B000,
 	APMIXED_BASE		= IO_PHYS + 0x0000C000,
 	PWRAP_BASE		= IO_PHYS + 0x0000D000,
 	EMI_BASE		= IO_PHYS + 0x00219000,
@@ -35,7 +36,7 @@ enum {
 	DRAMC_CH_BASE		= IO_PHYS + 0x00228000,
 	AUXADC_BASE		= IO_PHYS + 0x01001000,
 	UART0_BASE		= IO_PHYS + 0x01002000,
-	SPI0_BASE               = IO_PHYS + 0x0100A000,
+	SPI0_BASE		= IO_PHYS + 0x0100A000,
 	SPI1_BASE		= IO_PHYS + 0x01010000,
 	SPI2_BASE		= IO_PHYS + 0x01012000,
 	SPI3_BASE		= IO_PHYS + 0x01013000,

src/soc/mediatek/mt8183/include/soc/gpio.h

@@ -26,17 +26,6 @@ enum {
 	GPIO_MODE_BITS = 4,
 };
 
-typedef union {
-	u32 raw;
-	struct {
-		u32 id     : 8;
-		u32 flag   : 3;
-		u32 bit    : 5;
-		u32 base   : 8;
-		u32 offset : 8;
-	};
-} gpio_t;
-
 #define IOCFG_TO_GPIO_BASE(x) ((x >> 16) & 0xff)
 #define GPIO_TO_IOCFG_BASE(x) ((void *)(IOCFG_RT_BASE & 0xff000000) + \
 			       ((x) << 16))
@@ -628,8 +617,4 @@ check_member(gpio_regs, mode[22].val, 0x460);
 
 static struct gpio_regs *const mtk_gpio = (void *)(GPIO_BASE);
 
-void gpio_set_pull(gpio_t gpio, enum pull_enable enable,
-		   enum pull_select select);
-void gpio_set_mode(gpio_t gpio, int mode);
-
 #endif

src/soc/mediatek/mt8183/include/soc/gpio_base.h

@@ -0,0 +1,31 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 MediaTek Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#ifndef SOC_MEDIATEK_MT8183_GPIO_BASE_H
+#define SOC_MEDIATEK_MT8183_GPIO_BASE_H
+
+#include <stdint.h>
+
+typedef union {
+	u32 raw;
+	struct {
+		u32 id     : 8;
+		u32 flag   : 3;
+		u32 bit    : 5;
+		u32 base   : 8;
+		u32 offset : 8;
+	};
+} gpio_t;
+
+#endif