mb/google/hatch: do UART pad configuration at board-level
UART pad configuration should not be done in common code, because that may cause short circuits, when the user sets a wrong UART index. Thus, add the corresponding pads to the early UART gpio table for the board as a first step. Common UART pad config code then gets dropped in CB:48829. Also switch to `bootblock_mainboard_early_init` to configure the pads in early bootblock before console initialization, to make the console work as early as possible. The board does not do any other gpio configuration in bootblock, so this should not influence behaviour in a negative way (e.g. breaking overrides). Change-Id: I62ffbe36bd7b7675aa0f41a8c6e9214d04ad4ae5 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49428 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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1b77a487d6
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3a2d4000ce
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@ -4,7 +4,7 @@
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#include <bootblock_common.h>
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#include <soc/gpio.h>
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static void early_config_gpio(void)
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void bootblock_mainboard_early_init(void)
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{
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const struct pad_config *variant_early_table;
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size_t variant_gpios;
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@ -12,8 +12,3 @@ static void early_config_gpio(void)
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variant_early_table = variant_early_gpio_table(&variant_gpios);
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gpio_configure_pads(variant_early_table, variant_gpios);
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}
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void bootblock_mainboard_init(void)
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{
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early_config_gpio();
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}
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@ -152,6 +152,10 @@ static const struct pad_config early_gpio_table[] = {
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PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1),
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/* B18 : H1_SLAVE_SPI_MOSI_R */
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PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1),
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/* C8 : UART_PCH_RX_DEBUG_TX */
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PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1),
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/* C9 : UART_PCH_TX_DEBUG_RX */
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PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1),
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/* C14 : BT_DISABLE_L */
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PAD_CFG_GPO(GPP_C14, 0, DEEP),
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/* PCH_WP_OD */
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@ -78,6 +78,10 @@ static const struct pad_config early_gpio_table[] = {
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PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1),
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/* B18 : H1_SLAVE_SPI_MOSI_R */
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PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1),
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/* C8 : UART_PCH_RX_DEBUG_TX */
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PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1),
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/* C9 : UART_PCH_TX_DEBUG_RX */
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PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1),
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/* C14 : BT_DISABLE_L */
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PAD_CFG_GPO(GPP_C14, 0, DEEP),
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/* PCH_WP_OD */
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@ -50,6 +50,10 @@ static const struct pad_config early_gpio_table[] = {
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PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1),
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/* B18 : H1_SLAVE_SPI_MOSI_R */
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PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1),
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/* C8 : UART_PCH_RX_DEBUG_TX */
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PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1),
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/* C9 : UART_PCH_TX_DEBUG_RX */
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PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1),
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/* C14 : BT_DISABLE_L */
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PAD_CFG_GPO(GPP_C14, 0, DEEP),
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/* PCH_WP_OD */
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@ -114,6 +114,10 @@ static const struct pad_config early_gpio_table[] = {
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PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1),
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/* B18 : H1_SLAVE_SPI_MOSI_R */
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PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1),
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/* C8 : UART_PCH_RX_DEBUG_TX */
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PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1),
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/* C9 : UART_PCH_TX_DEBUG_RX */
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PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1),
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/* C14 : BT_DISABLE_L */
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PAD_CFG_GPO(GPP_C14, 0, DEEP),
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/* PCH_WP_OD */
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@ -80,6 +80,10 @@ static const struct pad_config early_gpio_table[] = {
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PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1),
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/* B18 : H1_SLAVE_SPI_MOSI_R */
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PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1),
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/* C8 : UART_PCH_RX_DEBUG_TX */
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PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1),
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/* C9 : UART_PCH_TX_DEBUG_RX */
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PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1),
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/* C14 : BT_DISABLE_L */
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PAD_CFG_GPO(GPP_C14, 0, DEEP),
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/* PCH_WP_OD */
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@ -210,6 +210,10 @@ static const struct pad_config early_gpio_table[] = {
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PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1),
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/* B18 : H1_SLAVE_SPI_MOSI_R */
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PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1),
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/* C8 : UART_PCH_RX_DEBUG_TX */
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PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1),
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/* C9 : UART_PCH_TX_DEBUG_RX */
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PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1),
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/* C14 : BT_DISABLE_L */
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PAD_CFG_GPO(GPP_C14, 0, DEEP),
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/* PCH_WP_OD */
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@ -96,6 +96,10 @@ static const struct pad_config early_gpio_table[] = {
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PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1),
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/* B18 : H1_SLAVE_SPI_MOSI_R */
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PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1),
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/* C8 : UART_PCH_RX_DEBUG_TX */
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PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1),
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/* C9 : UART_PCH_TX_DEBUG_RX */
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PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1),
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/* C14 : BT_DISABLE_L */
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PAD_CFG_GPO(GPP_C14, 0, DEEP),
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/* PCH_WP_OD */
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@ -54,6 +54,10 @@ static const struct pad_config early_gpio_table[] = {
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PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1),
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/* B18 : H1_SLAVE_SPI_MOSI_R */
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PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1),
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/* C8 : UART_PCH_RX_DEBUG_TX */
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PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1),
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/* C9 : UART_PCH_TX_DEBUG_RX */
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PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1),
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/* C14 : BT_DISABLE_L */
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PAD_CFG_GPO(GPP_C14, 0, DEEP),
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/* PCH_WP_OD */
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@ -110,6 +110,10 @@ static const struct pad_config early_gpio_table[] = {
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PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1),
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/* B18 : H1_SLAVE_SPI_MOSI_R */
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PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1),
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/* C8 : UART_PCH_RX_DEBUG_TX */
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PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1),
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/* C9 : UART_PCH_TX_DEBUG_RX */
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PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1),
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/* C14 : BT_DISABLE_L */
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PAD_CFG_GPO(GPP_C14, 0, DEEP),
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/* PCH_WP_OD */
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@ -118,6 +118,10 @@ static const struct pad_config early_gpio_table[] = {
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PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1),
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/* B18 : H1_SLAVE_SPI_MOSI_R */
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PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1),
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/* C8 : UART_PCH_RX_DEBUG_TX */
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PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1),
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/* C9 : UART_PCH_TX_DEBUG_RX */
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PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1),
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/* C14 : BT_DISABLE_L */
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PAD_CFG_GPO(GPP_C14, 0, DEEP),
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/* PCH_WP_OD */
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@ -70,6 +70,10 @@ static const struct pad_config early_gpio_table[] = {
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PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1),
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/* B18 : H1_SLAVE_SPI_MOSI_R */
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PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1),
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/* C8 : UART_PCH_RX_DEBUG_TX */
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PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1),
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/* C9 : UART_PCH_TX_DEBUG_RX */
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PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1),
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/* C14 : BT_DISABLE_L */
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PAD_CFG_GPO(GPP_C14, 0, DEEP),
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/* PCH_WP_OD */
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