mb/google/octopus: Create phaser variant
This creates a phaser variant for octopus. Nothing is set in the variant files here; everything is picked up from baseboard. BUG=b:78572180 TEST=None Change-Id: Ia03e8af91741f1f7aa3a42ac28688b8b6a708932 Signed-off-by: Justin TerAvest <teravest@chromium.org> Reviewed-on: https://review.coreboot.org/25877 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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@ -41,6 +41,7 @@ config VARIANT_DIR
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string
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default "yorp" if BOARD_GOOGLE_YORP
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default "bip" if BOARD_GOOGLE_BIP
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default "phaser" if BOARD_GOOGLE_PHASER
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default "octopus" if BOARD_GOOGLE_OCTOPUS
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config DEVICETREE
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@ -51,6 +52,7 @@ config MAINBOARD_PART_NUMBER
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string
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default "Yorp" if BOARD_GOOGLE_YORP
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default "Bip" if BOARD_GOOGLE_BIP
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default "Phaser" if BOARD_GOOGLE_PHASER
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default "Octopus" if BOARD_GOOGLE_OCTOPUS
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config MAINBOARD_FAMILY
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@ -62,6 +64,7 @@ config GBB_HWID
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depends on CHROMEOS
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default "YORP TEST 7755" if BOARD_GOOGLE_YORP
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default "BIP TEST 5732" if BOARD_GOOGLE_BIP
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default "PHASER TEST 7167" if BOARD_GOOGLE_PHASER
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default "OCTOPUS TEST 6859" if BOARD_GOOGLE_OCTOPUS
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config HAS_TPM
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@ -10,3 +10,7 @@ config BOARD_GOOGLE_BIP
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bool "Bip"
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select BOARD_GOOGLE_BASEBOARD_OCTOPUS
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select BASEBOARD_OCTOPUS_LAPTOP
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config BOARD_GOOGLE_PHASER
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bool "Phaser"
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select BOARD_GOOGLE_BASEBOARD_OCTOPUS
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select BASEBOARD_OCTOPUS_LAPTOP
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@ -0,0 +1,16 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2018 Google LLC
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <baseboard/acpi/dptf.asl>
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@ -0,0 +1,21 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2018 Google LLC
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef MAINBOARD_EC_H
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#define MAINBOARD_EC_H
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#include <baseboard/ec.h>
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#endif
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@ -0,0 +1,21 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2018 Google LLC
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
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* GNU General Public License for more details.
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*/
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#ifndef MAINBOARD_GPIO_H
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#define MAINBOARD_GPIO_H
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#include <baseboard/gpio.h>
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#endif /* MAINBOARD_GPIO_H */
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