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soc/mediatek/mt8186: disable VSRAM_CORE 

VSRAM_CORE is not used on kingler/krabby, so we disable it.
This implementation is according to chapter 3.7 in MT8186 Functional
Specification.

BUG=b:220071688
TEST=the rail steadily shows 0V in either S0, S3, and S5.

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I5256f6a2c0ca5a951dc79f564575b526a84463fd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62253
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Rex-BC Chen 2022-02-21 11:44:47 +08:00 committed by Felix Held
parent eee62c1537
commit 3a3920263a
1 changed files with 4 additions and 0 deletions
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4
src/soc/mediatek/mt8186/mt6366.c
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@ -167,6 +167,10 @@ static struct pmic_setting init_setting[] = {
{0x1BCC, 0x70F, 0x7F7F, 0}, {0x1BCC, 0x70F, 0x7F7F, 0},
{0x1C9E, 0x38, 0x7F, 0}, {0x1C9E, 0x38, 0x7F, 0},
{0x1CA0, 0x70F, 0x7F7F, 0}, {0x1CA0, 0x70F, 0x7F7F, 0},
/* VSRAM_CORE: set SW mode */
{0x1CA4, 0x1, 0xFFFF, 0},
/* VSRAM_CORE: SW set OFF */
{0x1C9C, 0x0, 0xFFFF, 0},
{0x1EA2, 0x1B, 0x1F, 0}, {0x1EA2, 0x1B, 0x1F, 0},
{0x1EA4, 0xC00, 0x1C00, 0}, {0x1EA4, 0xC00, 0x1C00, 0},
{0x1EA6, 0xC00, 0x1C00, 0}, {0x1EA6, 0xC00, 0x1C00, 0},