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sb/intel/ibexpeak: Don't clear PMBASE regs in romstage 

X201 boots fine without it.

Change-Id: I20a8e598b07bf0a059dcb47651d1a26456863673
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35769
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Arthur Heymans 2019-10-03 07:17:18 +02:00
parent 39f8a1aaf9
commit 3a46e02964
2 changed files with 0 additions and 66 deletions
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29
src/mainboard/lenovo/x201/romstage.c
View File

@ -94,21 +94,6 @@ static void rcba_config(void)
early_usb_init(mainboard_usb_ports); early_usb_init(mainboard_usb_ports);
} }
static inline void write_acpi32(u32 addr, u32 val)
{
outl(val, DEFAULT_PMBASE | addr);
}
static inline void write_acpi16(u32 addr, u16 val)
{
outw(val, DEFAULT_PMBASE | addr);
}
static inline u32 read_acpi32(u32 addr)
{
return inl(DEFAULT_PMBASE | addr);
}
static void set_fsb_frequency(void) static void set_fsb_frequency(void)
{ {
u8 block[5]; u8 block[5];
@ -179,20 +164,6 @@ void mainboard_romstage_entry(void)
outb(0x50, 0x15ec); outb(0x50, 0x15ec);
outb(inb(0x15ee) & 0x70, 0x15ee); outb(inb(0x15ee) & 0x70, 0x15ee);
write_acpi16(0x2, 0x0);
write_acpi32(0x28, 0x0);
write_acpi32(0x2c, 0x0);
if (!s3resume) {
read_acpi32(0x4);
read_acpi32(0x20);
read_acpi32(0x34);
write_acpi16(0x0, 0x900);
write_acpi32(0x20, 0xffff7ffe);
write_acpi32(0x34, 0x56974);
pci_write_config8(PCH_LPC_DEV, GEN_PMCON_3,
pci_read_config8(PCH_LPC_DEV, GEN_PMCON_3) | 2);
}
early_thermal_init(); early_thermal_init();
timestamp_add_now(TS_BEFORE_INITRAM); timestamp_add_now(TS_BEFORE_INITRAM);

37
src/mainboard/packardbell/ms2290/romstage.c
View File

@ -90,29 +90,6 @@ static void rcba_config(void)
early_usb_init(mainboard_usb_ports); early_usb_init(mainboard_usb_ports);
} }
static inline void write_acpi32(u32 addr, u32 val)
{
outl(val, DEFAULT_PMBASE | addr);
}
static inline void write_acpi16(u32 addr, u16 val)
{
outw(val, DEFAULT_PMBASE | addr);
}
static inline u32 read_acpi32(u32 addr)
{
return inl(DEFAULT_PMBASE | addr);
}
// unused func - used for RE
#if 0
static inline u16 read_acpi16(u32 addr)
{
return inw(DEFAULT_PMBASE | addr);
}
#endif
void mainboard_romstage_entry(void) void mainboard_romstage_entry(void)
{ {
u32 reg32; u32 reg32;
@ -168,20 +145,6 @@ void mainboard_romstage_entry(void)
/* Enable SMBUS. */ /* Enable SMBUS. */
enable_smbus(); enable_smbus();
write_acpi16(0x2, 0x0);
write_acpi32(0x28, 0x0);
write_acpi32(0x2c, 0x0);
if (!s3resume) {
read_acpi32(0x4);
read_acpi32(0x20);
read_acpi32(0x34);
write_acpi16(0x0, 0x900);
write_acpi32(0x20, 0xffff7ffe);
write_acpi32(0x34, 0x56974);
pci_write_config8(PCH_LPC_DEV, GEN_PMCON_3,
pci_read_config8(PCH_LPC_DEV, GEN_PMCON_3) | 2);
}
early_thermal_init(); early_thermal_init();
timestamp_add_now(TS_BEFORE_INITRAM); timestamp_add_now(TS_BEFORE_INITRAM);