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spd/lp5: Update memory configuration of H9JCNNNFA5MLYR-N6E 

Update bitWidthPerChannel in memory_parts.json and re-generate the SPD.
Then the device boots successfully with DDR H9JCNNNFA5MLYR-N6E.

BUG=b:261530632
BRANCH=None
TEST=util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5

Change-Id: Ib78c2e28394206b59c41b6b28cf24d8a756f7ae9
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70741
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
This commit is contained in:
Frank Wu 2022-12-14 10:03:50 +08:00 committed by Karthik Ramasubramanian
parent 315d3264b6
commit 3a4e201a21
3 changed files with 3 additions and 3 deletions
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2
spd/lp5/memory_parts.json
View File

@ -181,7 +181,7 @@
"attribs": {
"densityPerDieGb": 8,
"diesPerPackage": 8,
"bitWidthPerChannel": 16,
"bitWidthPerChannel": 8,
"ranksPerChannel": 2,
"speedMbps": 6400
}

2
spd/lp5/set-0/parts_spd_manifest.generated.txt
View File

@ -16,6 +16,6 @@ MT62F1G32D2DS-026 WT:B,spd-7.hex
MT62F2G32D4DS-026 WT:B,spd-8.hex
K3KL8L80CM-MGCT,spd-7.hex
K3KL9L90CM-MGCT,spd-8.hex
H9JCNNNFA5MLYR-N6E,spd-9.hex
H58G66BK7BX067,spd-8.hex
H58G56BK7BX068,spd-7.hex
H9JCNNNFA5MLYR-N6E,spd-4.hex

2
spd/lp5/set-1/parts_spd_manifest.generated.txt
View File

@ -16,6 +16,6 @@ MT62F1G32D2DS-026 WT:B,spd-7.hex
MT62F2G32D4DS-026 WT:B,spd-8.hex
K3KL8L80CM-MGCT,spd-7.hex
K3KL9L90CM-MGCT,spd-8.hex
H9JCNNNFA5MLYR-N6E,spd-9.hex
H58G66BK7BX067,spd-8.hex
H58G56BK7BX068,spd-7.hex
H9JCNNNFA5MLYR-N6E,spd-4.hex